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TRANSCRIPT
Nov 27 2012
RJ33J3BA0DT
Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written permission
of the company.
When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
（1） Please do verify the validity of this part after assembling it in customer’s products, when customer wants to make catalogue and instruction manual based on the specification sheet
of this part.
（2） The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (3), even for
the following application areas, be sure to observe the precautions given in Paragraph (3).
Never use the products for the equipment listed in Paragraph (4).
Office electronics
・ Instrumentation and measuring equipment
・ Machine tools
・ Audiovisual equipment
・ Home appliance
・ Communication equipment other than for trunk lines
（3） Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
・ Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
・ Mainframe computers
・ Traffic control systems
・ Gas leak detectors and automatic cutoff devices
・ Rescue and security equipment
・ Other safety devices and safety equipment, etc
（4） Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy.
・ Aerospace equipment
・ Communications equipment for trunk lines
・ Control equipment for the nuclear power industry
・ Medical equipment related to life support, etc.
（5） Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company.
Please direct all queries and regarding the products covered herein to a sales representative of the company.
RJ33J3BA0DT
CONTENTS
1 DESCRIPTION ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 2
1.1 Features
1.2 Applications
2 ARRANGEMENT OF PIXELS AND COLOR FILTERS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 3
3 PIN CONFIGURATION ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 4
4 ABSOLUTE MAXIMUM RATINGS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 4
4.1 CCD, VDr Power sequence
5 RECOMMENDED OPERATING CONDITIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 8
6 CHARACTERISTICS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 9
7 DRIVE TIMING CHART ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 10
8 EXAMPLE OF STANDARD OPERATING CIRCUIT ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 21
9 PECIFICATION FOR BLEMISH ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 22
10 PRECAUTIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 24
9.1 Package Breakage
9.2 Electrostatic Damage
9.3 Dust and Contamination
9.4 Other
11 PACKAGE OUTLINES AND PACKING SPECIFICATIONS ‥‥‥‥‥‥‥‥‥‥‥‥ 26
RJ33J3BA0DT 1
1 DESCRIPTION
The RJ33J3BA0DT is a 1/3-type solid-state image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With approximately 1,320,000 pixels, the sensor provides
a high resolution stable color image.
1 . 1 Features
1）Optical size : 6.00 mm (Aspect ratio 4:3)
2）Progressive scan format
3）Square pixel
4）Number of total pixels : Horizontal 1372 × vertical 986
Number of image pixels : Horizontal 1320 × vertical 976
Number of effective pixels : Horizontal 1280 × vertical 960
Pixel pitch : Horizontal 3.75μm × vertical 3.75μm
Number of optical black pixels : Horizontal ; 12 front and 40 rear
: Vertical ; 8 front and2 rear
Number of dummy bits : Horizontal ; 4, Vertical ; 2
5）R, G and B primary color mosaic filters
6）Supports monitoring mode
7）Built-in overflow drain voltage output circuit, and reset gate voltage circuit
8）Variable electronic shutter
9）Low fixed pattern noise and lag
10）No burn-in and no image distortion
11）Blooming suppression structure
12）Built-in output amplifier
13）N-type silicon substrate, N-MOS process,
Not designed or rated as radiation hardened
1 . 2 Applications
1）Electronic still cameras, video capturing devices for PCs, etc
2）Pattern recognition
※ The circuit diagram and others included in this specifications are intended for use to explain typical application examples. Therefore, we take no responsibility for any problem as may occur due to the
use of the included circuit and for any problem with industrial proprietary rights or other rights.
1,230k effective pixels
6.00 mm
9
60
1,280
RJ33J3BA0DT 2
2 ARRANGEMENT OF PIXELS AND COLOR FILTERS
Pin arrangement of the vertical readout clock
(1, 976)
1A G B G B G B G B G B
1B R G R G R G R G R G
1C G B G B G B G B G B
1D R G R G R G R G R G
1A G B G B G B G B G B
1B R G R G R G R G R G
1C G B G B G B G B G B
1D R G R G R G R G R G
1A G B G B G B G B G B
1B R G R G R G R G R G
1C G B G B G B G B G B
1D R G R G R G R G R G
(1, 1) (1320, 1)
(1320, 976)
Optical black （40 pixels）
Optical black （12 pixels）
1 pin
Image pixels
1320（H）× 976（V）
Optical black （8 pixels）
Dummy bit（2 pixels）
Optical black （2 pixels）
RJ33J3BA0DT 3
3 PIN CONFIGURATION(TOP VIEW)
OS GND φV1A φV1B φV1C φV1D φV2 φV3 φV4 φVS1AφVS3A φVS2
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
OD GND φRS φLH1 φH1 φH2 OFD OOFD PW φVS1BφVS3B φVS4
Symbol Pin name OD Output transistor drain OS Output signals φRS Reset transistor clock φV1A,φV1B,φV1C,φV1D, φV2,φV3,φV4, φVS1AφVS1B,φVS2, φVS3A,φVS3B,φVS4
Vertical shift register clock
φLH1,φH1,φH2 Horizontal shift resister clock OFD Overflow drain OOFD Output overflow drain PW P_well GND Ground
4 ABSOLUTE MAXIMUM RATINGS
（TA=25）
Parameter Symbol Ratings UnitOutput transistor drain voltage VOD 0 to +15.4 V Overflow drain voltage VOFD Internal output (Note 1) Reset gate clock voltage VφRS Internal output (Note 2) Vertical shift register clock voltage VφV VPW to +15.4 V Horizontal shift register clock voltage VφH -0.3 to +5.1 V Voltage difference between P_well and vertical clock VPW-VφV -23.8 to +0 V Voltage difference between vertical clocks VφV-VφV 0 to +9.9 (Note 3) V Storage temperature TSTG -40 to +80 Ambient operating temperature TOPR -20 to +70
(Note 1) Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 22.5 Vp-p.
(Note 2) Do not connect to DC voltage directly. When φRS is connected to GND, connect VOD to GND. Reset gate clock is applied below 5.1 Vp-p.
(Note 3) When clock width is below 10 μs, and clock duty factor is below 0.1 %, voltage difference between adjoining vertical clocks are guaranteed up to 15.4 V. Do not change allφV during 0.5μs before rising edge of VφVH pulse and after falling edge of VφVH pulse. Do not change directly into VφVL→VφVH or VφVH→VφVL.
RJ33J3BA0DT 4
4.1 CCD, VDr Power sequence
<< DC Voltage >>VDriverPower AFE powerAFE_Power(3.3V/1.8V)
VH、VHH、OD VDr:VHH, VH andCCD:OD
VL=PW VDr:VL, CCD:PW
<< Clock >>φV1A～φVs4 VM Vertical shift
register clock
φOFD
〔※H-CLOCKS Horizontal shift
(φH1/2,φR,φLH1) register clock
PeriodC
PeriodB
PeriodA
Don't switch during periodA,B,C( Keep GND level )
Power ON sequence
Turn on power in order of VDD→VH( =VHH=OD )→VL( =PW ) and after that apply the clocks. All φV pin of CCD should be ＶＭ[Intermediate(0V)]level during period A ,B,C. φOFD pin of CCD should be Low level during period A ,B,C. Period A：Turn on VH with the condition that all φV pulse is VM[Intermediate( 0V )]level.
Period B：Turn on VL( =PW ) after VH( =VHH=OD ) voltage reach to higher than 90% of its typical voltage. Period C：Start φV clocks after VL( =PW ) voltage reach to lower than 90% of its typical voltage.
Power OFF sequence
Turn off power in reverse order of Power ON. At Power OFF sequence, it is not problem any power reach to 0V earlier ( caused by difference of time constant of decoupling capacitor ).
But in case of turn on again, turn on should be done in order shown above after all voltage of power reach less than 10% of its typical value.
( AFE power < AFE power *0.1 & VH < VH*0.1 & VL > VL*0.1 )
Restriction matter of φV and φOFD switching 1) Please turn on power in condition that all φV pulse is VM[Intermediate(0V)]level.
NGVφVH
VφVM
VφVL
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
φV1A～φVs4(One or more)
NG
PeriodA or B or C
Keep VφVM
Keep VφVM
PeriodA or B or C
2) Please turn on power in condition that φOFD pulse is Low level.
NG
PeriodA or B or C
Keep Vlow
Vlow
Vhigh
φOFD
RJ33J3BA0DT 5
3) Please avoid same time ( <50ns ) switching of φV and φOFD.
VφVHVφVM
VφVL
Vlow
Vhigh
VφVH
VφVM
VφVL
Vlow
Vhigh
VφVH
VφVM
VφVL
Vlow
Vhigh
NG
NG
φOFD
VφVH
VφVM
VφVL
Vlow
Vhigh
φV1A～φVs4(One or more)
φOFD
φV1A～φVs4(One or more)
φOFD
φV1A～φVs4(One or more)
φOFD
φV1A～φVs4(One or more)
Avoid same time switching
NG
NG
Avoid same time switching
Avoid same time switchingAvoid same time switching
4)Please avoid switching of φV during period that φOFD is High.
VφVH
VφVM
VφVL
Vlow
VhighφOFD
VφVH
VφVM
VφVL
Vlow
Vhigh
φV1A～φVs4(One or more)
φOFD
φV1A～φVs4(One or more)NG NG
Avoid φV switching AvoidφV switching
5) Start or stop ΦV switching at the arbitrary point on timing chart of CCD spec. except following period. φV clock should not start or stop at,
5-1)Exposure period of long time exposure ( all φV =L )
φV1A～φVs4(All φV)
VφVH
VφVM
VφVL
Don't start or stop φV switching
All φ V = VφVL
5-2)During period that φOFD=High.
VφVH
VφVM
VφVL
Vlow
Vhigh
φOFD
φV1A～φVs4(One or more)
Don't start or stop φV switching
5-3)During period that φV=High.
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
Don't start or stop φV switching
RJ33J3BA0DT 6
6) Only in case of clock width is below 10μs and clock duty factor is below 0.1%, voltage difference between adjoining vertical clocks are guaranteed up to 15.4V. Only if all the following conditions are satisfied, VH pulse is allowed. 6-1) Width is 10μs or less.
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
Max width is 10μs
6-2) Clock duty factor is 0.1% or less.
Max clock duty is 0.1%
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
6-3) Ajoining gate level is 0V.
VφVH
VφVM
VφVL
φV1A～φVs4(Adjoining φV)
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
NG
Keep VφVM
Adjoining vertical clock gate: See Table.1
7) Don't change all φV during 0.5μs before rising edge of VφVH pulse and after falling edge of VφVH pulse.
Min width is 0.5μs
VφVH
VφVM
VφVL
VφVH
VφVM
VφVL
φV1A～φVs4(Others φV)
φV1A～φVs4(Others φV)
VφVH
VφVM
VφVL
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
φV1A～φVs4(One or more)
VφVH
VφVM
VφVL
VφVH
VφVM
VφVL
φV1A～φVs4(Others φV)
φV1A～φVs4(Others φV)
VφVH
VφVM
VφVL
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
φV1A～φVs4(One or more)
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
Min width is 0.5μs
Min width is 0.5μs
Min width is 0.5μs
Min width is 0.5μs
Min width is 0.5μs
8) Don't change φV directly into VφVL→VφVH or VφVH → VφVL.
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)
VφVH
VφVM
VφVL
φV1A～φVs4(One or more)NG NG
9) Please change mode follow timing chart in CCD spec. * This sequence explanation specify at Sharp CCD pin. Please check with AFE vender about sequence of AFE.
RJ33J3BA0DT 7
V1A
V1B
V1C
V1D
V2
V3
V4
VS1
AV
S1B
VS2
VS3
AV
S3B
VS4
V1A
V1B
V1C
V1D
V2
V3
V4
VS1
A
VS1
B
VS2
VS3
A
VS3
B
VS4
Adj
oini
ng p
inΦVpin
Tab
le.1
Inf
orm
atio
n fo
r ad
join
ing
Ver
tica
l clo
ck g
ate
pin
( ΦV
pin ）
RJ33J3BA0DT 8
5 RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min. Typ. Max. Unit
Ambient operating temperature TOPR 25.0
Output transistor drain voltage VOD 13.1 13.5 13.9 V
Overflow drain clock p-p level (Note 1) VφOFD 19.3 20.0 20.7 V
Ground GND 0.0 V
P_well voltage (Note 2) VPW -6.8 VφVL V
Vertical shift register
clock
LOW level VφV1AL, VφV1BL, VφV1CL, VφV1DL,
VφV2L, VφV3L, VφV4L,VφVS1AL, VφVS1BL,
VφVS2L, VφVS3AL,
VφVS3BL, VφVS4L
-6.8 -6.5 -6.2 V
INTERMEDIATE
level
VφV1AI, VφV1BI, VφV1CI, VφV1DI,
VφV2I, VφV3I, VφV4I,VφVS1AI, VφVS1BI,
VφVS2I, VφVS3AI,
VφVS3BI, VφVS4I
0.0 V
HIGH level VφV1AH, VφV1BH, VφV1CH, VφV1DH
13.1 13.5 13.9 V
Horizontal shift
register clock
LOW level VφH1L,VφH2L -0.05 0.0 0.05 V
HIGH level VφH1H,VφH2H 3.15 3.6 V
Reset gate clock p-p level (Note 1) VφRS 3.15 3.6 V
Vertical shift register clock frequency
(Note 3)
fφV1A,fφV1B,fφV2
fφV3,,fφV4 29.8 KHz
Horizontal shift register clock frequency fH1,fH2 45.0 MHz
Reset gate clock frequency fφRS 45.0 MHz
（Note 1） Use the circuit parameter indicated in “7 EXAMPLE OF STANDARD OPERATING CIRCUIT” (P.23), and do not connect to DC voltage directly.
（Note 2） VPW is set below VφＶＬ that is low level of vertical shift register clock, or is used with the same
power supply that is connected to VL of V driver IC.
（Note 3） At frame accumulation mode.
※ To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on VPW first and
then turn on other powers and pulses.
Do not connect the device to or disconnect it from the plug socket while power is being applied.
RJ33J3BA0DT 9
6 CHARACTERISTICS (Drive method : 1/30s frame accumulation)
TA：+25, but +60 for parameter No.4 and No.5.
Operating conditions : the typical values specified in “5 RECOMMENDED OPERATING CONDITIONS”.
Color temperature of light source : 3200K, IR cut-off filter (CM-500,1 mmt) is used.
No. Parameter Symbol Note Minimum Typical Maximum Unit
1 Standard output voltage VO 1 150 mV
2 Photo response non-uniformity PRNU 2 10 %
3 Saturation output voltage VSAT 3 TBD mV
4 Dark output voltage VDARK 4 0.5 3.0 mV
5 Dark signal non-uniformity DSNU 5 0.5 2.0 mV
6 Sensitivity(Green channel) R(G) 6 600 mV
7 Smear ratio SMR 7 -110 dB
8 Image lag AI 8 1.0 %
9 Blooming suppression ratio ABL 9 1000
10 Output transistor drain current IOD 6.0 9.0 mA
【 Notes 】
1 The average output voltage of G signal under the uniform illumination. The standard exposure
conditions are defined as when VO is 150 mV.
2 The image area is divided into 10 × 10 segments under the standard exposure conditions. Each segment’s
voltage is the average output voltage of all pixels within the segment. PRNU is defined by
（Vmax - Vmin） / VO, where Vmax and Vmin are the maximum and minimum values of each
segment’s voltage respectively.
3 The image area is divided into 10 × 10 segments. Each segment’s voltage is the average output voltages
of all pixels within the segment. Vsat is the minimum segment’s voltage under 10 times exposure of
the standard exposure conditions.
4 The average output voltage under non-exposure conditions.
5 The image area is divided into 10 × 10 segments under non-exposure conditions. DSNU is defined
by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each
segment’s voltage respectively.
6 The average output voltage of G signal when a 1000 lux light source with a 90 % reflector is
imaged by a lens of F4, f50 mm.
7 The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical
image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period
to the maximum output voltage in the V/10 square.
8 The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by
the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard
output voltage.
9 The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL
is defined by the ratio of the exposure at the standard conditions to the exposure at a point where
blooming is observed.
【 Comment 】
Within the recommended operating conditions of VOD, VOFD of the internal output satisfies with ABL and VSAT.
RJ33J3BA0DT 10
7 DRIVE TIMING CHART
Pul
se d
iagr
am in
mov
e de
tail
is s
how
n in
fig
ures
(ⅰ
) to
(ⅱ
) af
ter
next
pag
e
HD
No.
HD
VD
3
Ver
tica
l tra
nsfe
r ti
min
g 【
Fra
me
accu
mul
atio
n m
ode】
fck
=45
MH
z 30
fps
OF
DC
…HＩ
…
Ｉ Ｉ Ｉ L
ΦV
1A
… …… … … …
LＩ
4
(45M
Hz)
1513
clk/
H
… …
←←
←( ⅰ
)
10Φ
VS
2
1 87Φ
V4
ΦV
365 12
ΦV
S3b
ΦV
S3a
112
ΦO
FD
3Φ
V1C
ΦV
S1b
9
ΦV
S1a
ΦV
S4
13
ΦV
1B
L LＩ L
ΦV
1D
LＩ Ｉ
ΦV
2
D1
D2
OB
1O
B2
…R
GG
BG
BO
B1
974
975
←←
←( ⅰ
)( ⅱ
988
H)
OB
3O
B4
67
8
OB
2O
B5
2R
GO
B6
1G
BR
G 3O
B7
OB
897
6
… … … … … … …
←…
←←
←←
←11
12←
←←
←←
1314
21
23
45
1516
910
3
OS
989
990
991
117
…98
798
8
RJ33J3BA0DT 11
1Ｈ
2Ｈ15
13,0
30
015
13,0
30
0HD ΦL
H1ΦH
2AΦ
H2B
ΦRS
OS
400
720
ΦV1A
BCD
H1
11
11
1x
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦV2
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦV3
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
082
0ΦV
4L
01
11
11
11
00
00
00
00
00
00
00
00
00
00
00
00
00
0
ΦVs1
aH
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
ΦVs1
bH
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
ΦVs2
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦVs3
aL
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
ΦVs3
bL
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
ΦVs4
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦOFD
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
＊
Keep
ove
r the
per
iods
indi
cated
in th
is tim
ing
char
t whe
n ve
rtica
l tra
nsfe
r clo
ck p
ulse
is o
verla
ppin
g.
Rea
dout
tim
ing
【Fra
me a
ccum
ulati
on m
ode 】
fck=
45M
Hz 3
0fps
（ⅱ
）1c
lk =
22.
2ns (
= 1
/45.
0MHz
)
RJ33J3BA0DT 12
1513
,0
300
HD
00
11
11
11
1
0544
5505
1244
5505
1245
0505
1244
555
136
ΦH
1A,Φ
H1B
11
11
11
11
1Φ
LH
105
4455
0512
4455
0512
4505
0512
4455
5
ΦH
2A,Φ
H2B
00
00
00
00
0
0544
5505
1244
5505
1245
0505
1244
555
ΦR
S
0544
5505
1244
5505
1245
0505
1244
555
OS
ofd
-ｔ１
ｔ２ｔ３
ｔ４ｔ５
ｔ６ｔ７
ｔ８
47
92
ΦV
1AB
CD
H1
11
00
01
11
75
120
ΦV
2H
11
11
10
00
1
33
106
ΦV
3L
00
11
11
10
0
61
134
ΦV
4L
00
00
11
11
1
47
92
ΦV
s1a
H1
11
00
01
11
47
92
ΦV
s1b
H1
11
00
01
11
75
120
ΦV
s2H
11
11
10
00
1
33
106
ΦV
s3a
L0
01
11
11
00
33
106
ΦV
s3b
L0
01
11
11
00
61
134
ΦV
s4L
00
00
11
11
1
030
ΦO
FD
L1
00
00
00
00
＊
Kee
p ov
er th
e pe
riod
s in
dica
ted
in th
is ti
min
g ch
art w
hen
vert
ical
tran
sfer
clo
ck p
ulse
is o
verl
appi
ng.
Hor
izon
tal t
rans
fer
tim
ing
【Fr
ame
accu
mul
atio
n m
ode 】
fck
=45
MH
z 30
fps
（ⅱ
）1c
lk =
22.
2ns
( =
1/4
5.0M
Hz
)
RJ33J3BA0DT 13
Puls
e di
agra
m in
mov
e de
tail
is sh
own
in fi
gure
s (ⅰ
) to
(ⅱ) a
fter n
ext p
age
HD
No.
HD
VD
40
② V
ertic
al tr
ansf
er ti
min
g 【
4-p
ixel
s add
ition
[VG
A],
60 fr
ames
/s )
】
36
29 30 31 32
41 42 43B
444
3733
8
234 35
38ou
tput
sig
nal
B1
B2
B3
ΦV
1B
ΦV
1D
L
2
ΦO
FD
3Φ
V1C
ΦV
S1b
9
ΦV
S1a
ΦV
S3a
1110Φ
VS2
ΦV
S41312
ΦV
S3b
7Φ
V4
ΦV
365
ΦV
2
←←
(ⅰ)
←←
←←
←←
←←
324
915
16…
250
14(ⅰ
)←
←←
(ⅱ 2
47H
)←
OS
Ｉ Ｉ Ｉ L
4
ΦV
1A1 8
110
112
34
56
7
26 277
…17←
←←
13
39
(45M
Hz)
3005
clk/
H
128
91
224
624
724
8
22 23
13 14 1543
1019
51
17 186
B2
966
962
2521
9 11 1220
2824
963
972
B5
B6
B7
B8
16
974
975
976
970
971
Not
for u
se…
973
969
961
B1
965
… …………
967
964
968
…
Ｉ
… … … … … …Ｉ
…
Ｉ… …
L Ｉ Ｉ
… …
OFD
C…
LL L
… …
L
…
RJ33J3BA0DT 14
1H
2H3H
3005
,0
300
3005
,0
300
3005
,0
300
HD
00
11
11
11
11
11
11
11
11
11
11
11
11
11
11
01
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦH
1Φ
LH1
ΦH
2Φ
RSO
S
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
200
520
11
1415
1490
2235
2310
2435
2510
ΦV
1AH
11
11
11
ｘｘ
11
11
11
11
11
11
11
11
11
11
11
11
00
01
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1020
1340
114
1514
9022
3523
1024
3525
10Φ
V1B
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
1ｘ
11
10
00
11
11
11
11
11
11
11
11
11
00
01
11
11
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
2660
2980
1415
1490
2235
2310
2435
2510
10
ΦV
1CH
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
00
01
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
ｘ1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1840
2160
1415
1490
122
3523
1024
3525
10Φ
V1D
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
00
11
11
11
11
11
11
11
ｘ1
11
00
01
11
11
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
1465
1540
2285
2360
2485
2560
ΦV
2H
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
00
01
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1390
1515
2210
2335
2410
2535
ΦV
3L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
11
11
00
00
00
00
00
00
00
00
11
11
10
00
11
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
1440
1565
2260
2385
2460
2585
ΦV
4L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
11
11
00
00
00
00
00
00
00
00
11
11
10
00
11
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
1415
1490
2235
2310
2435
2510
ΦV
s1a
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
00
11
11
11
11
11
11
11
11
11
00
01
11
11
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
1415
1490
2235
2310
2435
2510
ΦV
s1b
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
00
11
11
11
11
11
11
11
11
11
00
01
11
11
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
1465
1540
2285
2360
2485
2560
ΦV
s2H
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
00
01
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1390
1515
2210
2335
2410
2535
ΦV
s3a
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
11
11
10
00
00
00
00
00
00
00
01
11
11
00
01
11
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
1390
1515
2210
2335
2410
2535
ΦV
s3b
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
11
11
10
00
00
00
00
00
00
00
01
11
11
00
01
11
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
1440
1565
2260
2385
2460
2585
ΦV
s4L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
11
11
00
00
00
00
00
00
00
00
11
11
10
00
11
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦO
FDL
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
＊
Kee
p ov
er th
e pe
riods
indi
cate
d in
this
timin
g ch
art w
hen
verti
cal t
rans
fer c
lock
pul
se is
ove
rlapp
ing.
② H
oriz
onta
l tra
nsfe
r tim
ing
【 4
-pix
els a
dditi
on[V
GA
], 60
fram
es/s
) 】（
ⅰ）
1clk
= 2
2.2n
s ( =
1/4
5.0M
Hz )
RJ33J3BA0DT 15
3005
,0
300
HD
00
00
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
5542
542
612
2712
2816
29Φ
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1Φ
LH
155
425
426
1227
1228
ΦH
20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
55
ΦR
S
55
OS
t1t1
t2t3
t4t5
t6t7
t8t1
t2t3
t4t5
t6t7
t8ttt
1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
ttt1
t2t3
t4t5
t6t7
t8t1
t2t3
t4t5
t6t7
t8
452
527
652
727
1254
1329
1454
1529
ΦV
1AB
CD
H1
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
502
577
702
777
1304
1379
1504
1579
ΦV
2H
11
11
11
11
11
11
11
11
11
11
00
01
11
11
00
01
11
11
11
11
11
11
11
11
11
11
00
01
11
11
00
01
1
427
552
627
752
1229
1354
1429
1554
ΦV
3L
00
00
00
00
00
00
00
00
01
11
11
00
01
11
11
00
00
00
00
00
00
00
00
00
01
11
11
00
01
11
11
00
0
477
602
677
802
1279
1404
1479
1604
ΦV
4L
00
00
00
00
00
00
00
00
00
01
11
11
00
01
11
11
00
00
00
00
00
00
00
00
00
01
11
11
00
01
11
11
0
452
527
652
727
1254
1329
1454
1529
ΦV
s1a
H1
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
11
11
11
11
11
11
11
11
10
00
11
11
10
00
11
11
5012
525
032
545
252
765
272
785
292
710
5211
2712
5413
2914
5415
29Φ
Vs1
bH
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
1
100
175
300
375
502
577
702
777
902
977
1102
1177
1304
1379
1504
1579
ΦV
s2H
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
1
427
552
627
752
1229
1354
1429
1554
ΦV
s3a
L0
00
00
00
00
00
00
00
00
11
11
10
00
11
11
10
00
00
00
00
00
00
00
00
00
11
11
10
00
11
11
10
00
2515
022
535
042
755
262
775
282
795
210
2711
5212
2913
5414
2915
54Φ
Vs3
bL
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
0
7520
027
540
047
760
267
782
787
710
0210
7712
0212
7914
0414
7916
04Φ
Vs4
L0
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
11
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
ΦO
FDL
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
＊
Kee
p ov
er th
e pe
riod
s in
dica
ted
in th
is ti
min
g ch
art w
hen
vert
ical
tran
sfer
clo
ck p
ulse
is o
verl
appi
ng.
② H
oriz
onta
l tra
nsfe
r tim
ing
【 4
-pix
els
addi
tion[
VG
A],
60
fram
es/s
) 】
（ⅱ
）1c
lk =
22.
2ns
( =
1/45
.0M
Hz
)
RJ33J3BA0DT 16
Pulse
dia
gram
in m
ove
deta
il is
show
n in
figu
res (ⅰ
) to
( ⅱ) a
fter n
ext p
age
HD
No.
HD
VD
1 2 3 4 5 6 7 8 9 10 11 12 13
(45M
Hz)
1868
clk/
H
③ V
ertic
al t
rans
fer
timin
g 【c
ente
r cu
t ou
t m
ode[
Cen
ter
732l
ine]
】
853
852
……
…
…
…12
012
112
284
9
…
……
Not
for u
se
…
850
851
…
119
……
…
……
……
…
……
…
……
…
……
…
……
…
……
…1s
tage
＝
43
2 cl
k1s
tage
＝
43
2 cl
k
……
…12
8 lin
e tra
nsfe
r12
8 lin
e tra
nsfe
r
……
Fast
shift
tran
sfer
Fast
shift
tran
sfer
……
32H
× 4
stag
e ＝
128
satg
e
40
32H
× 4
stag
e ＝
128
satg
e
……
…… …
…
←←
……77
077
177
3←
( ⅳ)
…
I
←6
…( ⅱ
)
I
OFD
CHL L
ΦV
S4
I
ΦV
S2
ΦV
S3b
ΦO
FD
I I
…… ……
Not
for u
se
I L L
……
…
392
34
535
3637
OS
( ⅲ )
138
I L L I
←…
12
802
767
768
769
…77
2
ΦV
1A
766
ΦV
1B
3( ⅰ
)←
←80
1←←
( ⅰ)
←←
←←
…
ΦV
1C
ΦV
S1b
ΦV
S1a
ΦV
S3a
ΦV
4
ΦV
3
ΦV
2
ΦV
1D
RJ33J3BA0DT 17
1Ｈ
2Ｈ18
68,0
30
018
68,0
30
0H
D
ΦH
1AΦ
H1B
ΦLH
1Φ
H2A
ΦH
2BΦ
RSO
S
400
720
ΦV
1ABC
DH
11
11
11
x1
11
11
11
11
11
11
11
11
11
11
11
11
11
1
ΦV
2H
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
ΦV
3L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
082
0Φ
V4
L0
11
11
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦV
s1a
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦV
s1b
H1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦV
s2H
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1
ΦV
s3a
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦV
s3b
L0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦV
s4L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
ΦO
FDL
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
＊
Kee
p ov
er th
e per
iods
indi
cate
d in
this
timin
g ch
art w
hen
verti
cal t
rans
fer c
lock
pul
se is
ove
rlapp
ing.
③ R
eado
ut ti
min
g 【c
ente
r cut
out
mod
e[Ce
nter
732
line]
】(ⅰ
)1c
lk =
22.
2ns (
= 1
/45.
0MH
z )
RJ33J3BA0DT 18
18
68,0
30
0H
D0
01
11
11
11
11
11
11
11
1
0544
5505
1244
5505
12450
505124
4555
492
ΦH
11
11
11
11
11
11
11
11
11
1Φ
LH1
0544
5505
1244
5505
1245
0505
1244
555
ΦH
20
00
00
00
00
00
00
00
00
0
0544
5505
1244
5505
1245
0505
1244
555
ΦRS
0544
5505
1244
5505
1245
0505
1244
555
OS
ofd
t1t2
t3t4
t5t6
t7t8
t9t1
0t1
1t1
2t1
3t1
4t1
5t1
6
114
276
ΦV
1ABC
DH
11
11
00
00
00
11
11
11
11
222
384
ΦV
2H
11
11
11
11
00
00
00
11
11
6033
0Φ
V3
L0
01
11
11
11
11
10
00
00
0
168
438
ΦV
4L
00
00
00
11
11
11
11
11
00
114
276
ΦV
s1a
H1
11
10
00
00
01
11
11
11
1
114
276
ΦV
s1b
H1
11
10
00
00
01
11
11
11
1
222
384
ΦV
s2H
11
11
11
11
00
00
00
11
11
6033
0Φ
Vs3
aL
00
11
11
11
11
11
00
00
00
6033
0Φ
Vs3
bL
00
11
11
11
11
11
00
00
00
168
438
ΦV
s4L
00
00
00
11
11
11
11
11
00
050
ΦO
FDL
10
00
00
00
00
00
00
00
00
＊
Kee
p ov
er th
e pe
riods
indi
cate
d in
this
timin
g ch
art w
hen
verti
cal t
rans
fer c
lock
pul
se is
ove
rlapp
ing.
③ H
oriz
onta
l tra
nsfe
r tim
ing
【cen
ter c
ut o
ut m
ode[
Cent
er 7
32lin
e]】(
ⅱ )
1clk
= 2
2.2n
s ( =
1/4
5.0M
Hz
)
RJ33J3BA0DT 19
18
68,0
30
018
68,0
H
D0
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
0
ΦH1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦLH
1Φ
H20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦRS
OS
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
168
330
600
762
1032
1194
1464
1626
ΦV1
ABC
DH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
276
438
708
870
1140
1302
1572
1734
ΦV2
H1
11
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
114
384
546
816
978
1248
1410
1680
ΦV3
L0
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
00
222
492
654
924
1086
1356
1518
1788
ΦV4
L0
00
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
168
330
600
762
1032
1194
1464
1626
ΦVs
1aH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
168
330
600
762
1032
1194
1464
1626
ΦVs
1bH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
276
438
708
870
1140
1302
1572
1734
ΦVs
2H
11
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
1
114
384
546
816
978
1248
1410
1680
ΦVs
3aL
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
0
114
384
546
816
978
1248
1410
1680
ΦVs
3bL
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
0
222
492
654
924
1086
1356
1518
1788
ΦVs
4L
00
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
0
050
ΦOF
DL
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
＊
Keep
ove
r the
per
iods
indi
cated
in th
is tim
ing
char
t whe
n ve
rtica
l tra
nsfe
r clo
ck p
ulse
is o
verla
ppin
g.
③ F
ast s
hift
trans
fer t
imin
g 【c
ente
r cut
out
mod
e[Ce
nter
732
line]
】(ⅲ
)1c
lk =
22.
2ns (
= 1
/45.
0MHz
)
RJ33J3BA0DT 20
18
68,0
30
018
68,0
H
D0
00
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
0
ΦH1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ΦLH
1Φ
H20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ΦRS
OS
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
t1t2
t3t4
t5t6
t7t8
168
330
600
762
1032
1194
1464
1626
ΦV1
ABC
DH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
276
438
708
870
1140
1302
1572
1734
ΦV2
H1
11
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
114
384
546
816
978
1248
1410
1680
ΦV3
L0
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
00
222
492
654
924
1086
1356
1518
1788
ΦV4
L0
00
00
01
11
11
00
01
11
11
00
01
11
11
00
01
11
11
00
168
330
600
762
1032
1194
1464
1626
ΦVs
1aH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
168
330
600
762
1032
1194
1464
1626
ΦVs
1bH
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
1
276
438
708
870
1140
1302
1572
1734
ΦVs
2H
11
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
11
1
114
384
546
816
978
1248
1410
1680
ΦVs
3aL
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
0
114
384
546
816
978
1248
1410
1680
ΦVs
3bL
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
00
0
222
492
654
924
1086
1356
1518
1788
ΦVs
4L
00
00
00
11
11
10
00
11
11
10
00
11
11
10
00
11
11
10
0
050
ΦOF
DL
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
＊
Kee
p ov
er th
e per
iods
indi
cated
in th
is tim
ing
char
t whe
n ve
rtica
l tra
nsfe
r clo
ck p
ulse
is o
verla
ppin
g.
③ C
harg
e sw
ept
tran
sfer
tim
ing【
cent
er c
ut o
ut m
ode[
Cen
ter
732l
ine]
】(ⅳ
)1c
lk =
22.
2ns (
= 1
/45.
0MHz
)
RJ33J3BA0DT 21
8 EXAMPLE OF STANDARD OPERATING CIRCUIT
2SC
1623
/2S
C46
17
or
equi
vale
nt
5.6
kΩ15
kΩ 1
00 kΩ
2SC
1623
/2SC
4617
47Ω
2.2μ
F o
r eq
uiva
lent
33kΩ
1μF
1S28
37/D
A12
1 o
r eq
uiva
lent
100kΩ
or
equi
vale
nt
VH
680p
F
+
+
－
R≦
2.2Ω
R≦
2.2Ω
2SC
2404
/V
DD
2SC
4627
o
r eq
uiva
lent
1KΩ
GND
φvS4
φv4
φvS3B
φvS3A
POFD
S3AX
GND
φvS4
φvS3B
φvS1B
PW
OOFD
OFD
ΦH2
ΦH1
LH1
φRS
GND
OD
VL
VL
VH
VH
S4X
VD
D
OFD
X
.H
1CX
S3B
X1C
X4X
2XS2
XH
1BX
H1D
X1B
X1D
XS1
BX
3XH
1AX
VD
DV
HV
HV
LV
L
GND
1AX
S1AX
φvS1A
φv1A
φvS1B
φv1B
φv2
φv1C
φvS2
φv1D
φv3
GND
φvS2
φvS3A
φvS1A
φv4
φv3
φv2
φv1D
φv1C
φv1B
φv1A
GND
OS
1AX
H1A
X1B
XH
1BX
1CX
H1C
X1D
XH
1DX
S1A
XS
1BX 2X
S2X 3X
S3A
XS
3BX 4X
4LX
S4X
54
1211
10
0.1μ
F
49
3938
4740
4143
4445
1S28
37/D
A12
1
4833
4642
37
1920
18
28 27 26 25
16
22 21
5
17
168
109
7
2423
2122
13
1511
122
414
136
1413
20 19 18 1715
6451 52
LR
3668
7U50 636260 6156 59
2457
2358
RJ3
3J3B
A0D
T
55
29
53 54
30
3635
34
16
9
31
32
328
7
φRS
φH1
φH2
VOD
VL(VPW)
OFDC
VH
RJ33J3BA0DT 22
9 SPECIFICATION FOR BLEMISH (1/30 s frame accumulation)
1） Definition of blemish
Level of blemish
(mV)
Permitted number of
blemish Comment
White blemish
(Exposed)
50 ≦ Ｂ 0 ・See fig.9-1(ａ), fig.9-2.
・Vout ＝ Vstd Ｂ ＜ 50 no count
Black blemish
(Exposed)
120≦ Ｂ 0
55≦ Ｂ ＜120 10
40≦ Ｂ ＜ 55 10
Ｂ ＜ 40 no count
White blemish
(Non-Exposed)
100＜ Ｂ 0 ・See fig.9-1(ｂ), fig.9-2
・Ｎ≦４０
・Ｍ＋Ｎ≦６４
20＜ Ｂ ≦100 Ｎ
2.5＜ Ｂ ≦ 20 Ｍ
Ｂ ≦2.5 no count
White blemish
(Shutter mode)
5.0≦ Ｂ 0 ・See fig.9-1(ａ), fig.9-2. ・Vout ＝ Vstd/10
・The electronic shutter
speed is set at 1/10000 s
Ｂ ＜5.0 no count
Black blemish
(Shutter mode)
5.0≦ Ｂ 0
Ｂ ＜5.0 no count
＊Total number of white blemish (non-exposed:20＜Ｂ≦100) and black blemish (exposed:
55≦Ｂ＜120)are less than 2 in arbitrary 8×8 pixels areas(ignore color filter).
ex. The defects are less than 2 in the subsequent area surrounded by bold lines.
《note》 ・ B ：Blemish level defined in fig. 9-1.
・ Vout ：Average output voltage
・ Vstd ：150 mV (The average output voltage of G signal). The standard
output voltage defined in the specification of the characteristics.
Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ
Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ
Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ
Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ
Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ
Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ
Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ
Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ
Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ Ｇ Ｂ
Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ Ｒ Ｇ
RJ33J3BA0DT 23
【MEASURING CONDITION】
・ Ｔａ： 60
・ Measuring block diagram
CCD output Amplifier output
The output voltage is measured at the CCD output.
The gain of the amplifier is adjusted to the unity between the CCD output and the amplifier output.
White blemish
B
B
Black blemish
Vout
B
（a）Exposed （b）Non-exposed
fig. 9-1 Definition of blemish level
(The wave form is the luminance signal measured at the Amplifier output)
【MEASURING AREA】
1320(Image area)
4
968
4
16 1288 16
fig. 9-2 Definition of the measuring area
ＣＣＤ ＣＤＳ ＡＭＰ
・ Exclusive area
RJ33J3BA0DT 24
10 PRECAUTIONS
10.1 Package Breakage
In order to prevent the package from being broken, observe the following instructions:
1） The CCD is a precise optical component and the package material is plastic. Therefore,
・Take care not to drop the device when mounting, handling, or transporting.
・Avoid giving a shock to the package. Especially when leads are fixed to the
socket or the circuit board, small shock could break the package more easily
than when the package isn’t fixed.
2） When mounting the package on the housing, be sure that the package is not bent. － If a bent package is forced into place between a hard plate or the like, the package may be broken.
3） If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore,
・Do not hit the glass cap.
・Do not give a shock large enough to cause distortion.
・Do not scrub or scratch the glass surface.
－ Even a soft cloth or applicator, if dry, could cause flaws to scratch the glass. 10.2 Electrostatic Damage
As compared with general MOS-LSI, CCD has lower ESD.
Therefore, take the following antistatic measures when handling the CCD:
1） Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 MΩ between the human body and
the ground to be on the safe side.
2） When directly handling the device with the fingers, hold the part without leads and do not touch any lead.
3） To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic
b. do not attach any tape or labels
c. do not clean the glass surface with dust-cleaning tape
4） When storing or transporting the device, put it in a container of conductive material.
RJ33J3BA0DT 25
10.3 Dust and Contamination
Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar.
In order to minimize dust or contamination on the glass surface, take the following precautions:
1） Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be,
if possible, class 1,000 at least.)
2） Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended:
・Dust from static electricity should be blown off with an ionized air blower.
For anti-electrostatic measures, however, ground all the leads on the device before blowing off
the dust.
・The contamination on the glass surface should be wiped off with a clean applicator soaked
in Isopropyl alcohol. Wipe slowly and gently in one direction only.
－ Frequently replace the applicator and do not use the same applicator to clean more than
one device.
※ Note: In most cases, dust and contamination are unavoidable, even before the device is first used.
It is, therefore, recommend that the above procedures should be taken to wipe out dust and
contamination before using the device.
10.4 Other
1） Soldering should be manually performed within 5 seconds at 350 maximum at the tip of soldering
iron.
2） Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD.
3） Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters.
ＲＪ３３Ｊ３ＢＡ０ＤＴ 2611 PACKAGE OUTLINE AND PACKING SPECIFICATION
１．Package Outline Specification Refer to attached drawing. （The seal resin stick out from the package shall be passed. And,the seal resins are two kinds of colors,while and transparency.） ２．Markings
Marking contents （１）．Product name ： R J3 3 J 3 B A 0 DT
（２）．Company name ： ＳＨＡＲＰ （３）．Country of origin： ＪＡＰＡＮ
（４）．Date code ： ＹＹ ＷＷ Ｘ ＸＸ
Denotes the production ref.code.(1～2 figures)
Denotes the production day of the week.
１ ２ ３ ４ ５ ６ ７
SUN. MON. TUE. WED. THU. FRI. SAT.
Denotes the production week.
（01,02,03,…,52,53）
Denotes the production year.
(Lower two digits of the year.)
Positions of markings are shown in the package outline drawing. But,markings shown in that drawing are not provided any measurements of their characters
and their positions. ３．Packing Specification ３－１．Packing materials
Material Name Material Spec. Purpose
Cover Tape Plastic film(1device/tape) Glass lid covering
Device case Cardboard(540devices/case) Device tray fixing
Device tray Conductive plastic
(90devices/tray)
Device packing(6trays/case)
Cover tray Conductive plastic(1tray/case) Device packing
PP band Polypropylene Device tray fixing
Buffer Cardboard(2sheets/case) Shock absorber of device tray
Plastic film bag Plastic film Device tray fixing
Tape Paper Sealing plastic film bag and device case
Label Paper Indicates part number,quantity and date of
manufacture
３－２．External appearance of packing Refer to attached drawing ４．Precaution １）．Before unpacking, confirm the imports of the chapter "Handling Precaution" in this device
specification. ２）．Unpacking should be done on the stand treated with anti-ESD. At that time, the same
anti-ESD treatment should be done to operator's body, too.
ISSUE NUMBER
２６１１２ＡＤＣ
ＲＪ３３Ｊ３ＢＡ０ＤＴ 27
Product Information Notification based on Chinese law, Management Methods for Controlling Pollution by Electronic Information Products.
Names and Contents of the Toxic and Hazardous Substances or Elements in the Product
：indicates that the content of the toxic and hazardous substance in all the homogeneous materials of the part is below the concentration limit requirement as described in SJ/T 11363-2006.
×：indicates that the content of the toxic and hazardous substance in at least one homogeneous material of the part exceeds the concentration limit requirement as described in SJ/T 11363-2006 standard.
HexavalentChromium
（Cr(VI)）
PolybrominatedBiphenyls（PBB）
PolybrominatedDiphenylEthers
（PBDE）
Lead（Pb）
Mercury（Hg）
Cadmium（Cd）
５．Chemical substance information in the product
ISSUE NUMBER
２６１１２ＡＤＣ
ＲＪ３３Ｊ３ＢＡ０ＤＴ 28
RJ33J3
０ ３
材質 MATERIAL 仕上 FINISH
SHARP CORPORATION
ELECTRONIC COMPONENTS AND DEVICES GROUP
名称
NAME
コード
CODE
図番
DRAWING No.
Assembly Process Technology Development Dept
BA0DT
ＲＪ３３Ｊ３ＢＡ０ＤＴ 29
RJ33J3BA0DT
RJ33J3BA0DT
' 1 2 . 0 6 . 1 1
材質 MATERIAL 仕上 FINISH
SHARP CORPORATION
ELECTRONIC COMPONENTS AND DEVICES GROUP
名称
NAME
コードCODE
図番
DRAWING No.
Assembly Process Technology Development Dept