rf power management attach

A MARKET TRAINING MODULE

FREDERIK DOSTAL MARCH 2016

RF Power Management Attach

Agenda

► Introduction► Typical RF signal chain► Overview of Power Management RF Attach at ADI► RF Attach blocks► Examples

SDR Catalina AD936x Transceiver Mykonos AD9370 RF DAC Barium AD9162 PLL/VCO ADF4355 GaN Amplifier voltage generation

► Additional LC Filters► ADP5003► Summary

Approximate training time

20 minutes - 24 SlidesPower Management

RF – Signal Chain

Introduction

► With the Hittite acquisition in 2014, Analog Devices became a market and technology leader in many RF applications.

► To enable ADI‘s RF customer‘s to build the best possible systems, high quality power rails are needed:

► Attach Power improves the signal-chain performance e.g. ADI’s low-noise LDO portfolio has been shown to improve VCO/PLL’s performance

► Time-to-Market by ADI optimized power solution

► Risk Reduction by ADI pre-characterized signal-chain performance

► “One-Stop” Customer Support by ADI professional engineering team

Analog Devices

Power Management

Typical RF signal chainVector Signal Analysis for Instrumentation & Aerospace and Defense

2. Pre-regulation with switching regulators

Overview RF Attach key Power Management product areas

1. Ultra-low noise Linear Regulators (LDOs)Enhance RF Signal Chain performance

4. System rail generation uPMUs3. Negative voltage generation

RF Attach blocks and power requirments 1

► Clock & Timing Products– Power requirements: Very low noise rails. Noise causes jitter– Solution: Lowest noise LDOs. (Integrated on some products)

► PLLs, VCOs, PLLVCOs– Power requirements: Very low noise analog rails. Noise degrades phase noise

performance– Solution: Lowest noise LDOs

– Power requirements : Fast slewing low noise variable voltage 1-20V for VCO tuning voltage used in PLL+VCO control loop

– Solution: Boost converter + HV LDO + OP AMP

► ADCs, DACs and T&H Amps– Power requirements: Multiple Digital and Low Noise Analog rails. Noise shows

up in RF spectrum as phase noise or spurs. Sequencing.– Solution: Multiple Buck Converters + LDOs, PMU. May require

Negative switcher + Negative LDO

► Baseband (Diff Amps, DVGA)– Power requirements: Low noise analog rails. Noise degrades phase noise

performance– Solution: Low noise LDOs


► Detectors (RMS, Envelope, SDVLA)

– Power requirements: Low noise, low current single positive rail

– Solutions: LDO

► IF, E-band, V-band Transceivers – Power requirements: Multiple Low Noise Analog rails. Noise shows up in RF

phase noise or spurs. Complex voltage sequencing.– Solutions: Multiple Buck Converters + LDOs, PMU? Will require

Negative switchers + Negative LDOs

► Power Amplifiers– Power requirements: Low Noise, high current positive rail (GaN requires 20-50V);

Lower current negative bias, sequencing– Solutions: Buck or Boost Converter + LDOs. Will often require

negativeSwitcher, LDO. New Automatic Bias Controller ADP5600

► HDR Products (Fiber Optic MD, HSL, NW)– MD Power requirements: Low Noise, Low voltage positive rail, Pos or Neg bias,

possible sequencing – Solutions: Buck or Boost Converter and/or LDOs. May require

negativeSwitcher, LDO.


– HSL Power requirements: Low Noise, Low voltage positive, and/or negative rail – Solutions: Buck or Boost Converter and/or LDOs. May require

negativeSwitcher, LDO.

– NW Power requirements: Multiple Digital rails. Voltage sequencing– Solutions: Multiple Buck or Boost Converter. PMU?

► Control Products (SW, ATT)– Power requirements: High Frequency SOI switches require low current neg bias– Solutions: Negative Switcher and/or LDO.

► Frequency Conversion Products (Active Mixer, Up/Down Converter)– Power requirements: One or Multiple Low Noise Analog rails. – Solutions: Multiple Buck Converters + LDOs,

9

The Need for Ultra Low Noise LDOs

What is the jitter requirement for a 25G lane?With every generation, lane speeds increase and jitter requirements scale accordingly

Speed(Lane Speed) Period Jitter Requirement

10G(2.5G)

40G(10G)

100G(25G)

400ps

100ps

40ps

800fs

200fs

80fs

75% reduction

60% reduction

Example 1: AD936x/Catalina Software Defined Radio Power Requirements

► 17 power supply balls spanning over three power domains supplying different circuits in the part► Current drawn from different power supply domains depends on end customer application► Intelligent power management and layout design to optimize performance

► Detailed information in Catalina documentation:

Power Domain Voltage range Max current range

Analog supply domain 1.3V (+/-3%) 180mA – 1050mA

Interface supply domain 1.2V – 2.5V 150mA

GPO power supply domain 1.3V – 3.3V 1mA – 100mA

Example 1: ADP5040 Supply for AD936x in noise sensitive applications with ADP1755 LDO

MODE

VIN2C1

10uF

VIN 3.6V to 5.5V

AGND

12

TP

FPWM

AUTO

17

L1 - 1uH

PGND

VOUT1

SWVIN1

C34.7uF

C510uF

7 8

12

9

BUCK1.2A

11

R325.5K

FB1

R410.7K

R710.7K

R89.1K

C101uF

1

VIN3

C91uF

ON

OFF 16EN2

ON

OFF 10EN1

ON

OFF 4EN3

HousekeepingC8

1uF

6

FB3

VOUT3

AVIN

ADP5040

2

LDO2300mA

3

VDD_1P3_xxx

VDD_INTERFACE

VDD_GPO

AD936x

1.7V

3.3V

R129.4K

R211.3K

C21uF

15FB2

VOUT214

LDO1300mA

1.8V

C40.1uF

TRANSCEIVER SECTIONPOWER SECTION

R511.5K

R67.15K

C610nF

VIN

VIN

VIN

ENGND SS NC

SNS

VOUT

VOUT

VOUTVOUTVOUTVIN VIN

PG

C72x

10uF 1.3V

ADP1755LDO

12

Example 2: AD9370(Mykonos) Power Requirements

► 20 power supply balls spanning over seven power domains supplying different circuits in the part► Current drawn from different power supply domains depends on end customer application► Intelligent power management and layout design to optimize performance

Power Domain Voltage Range Preliminary currentVDDA1P3 Analog supply

Sensitive1.3V (+/-2.5%, DC plus AC

tolerance)1410mA

VDDA1P3 Analog supply 1.3V (+/-2.5%, DC plus AC tolerance) 1051mA

VDDD1P3_DIG supply 1.3V (+/-2.5%) 1200mA

1P8 TX 1.8V 400mA

VDD Interface 1.8V~2.5V 50mA

VDDA_3P3 power supply 3.3V 124mA

JESD Supply (VTT) 1.3V 250mA

13

Example 2: Evolution of ADI Agile RF Transceiver Power Solution

Conservative RF Power SolutionADP5050, 7x LDOs

850mA

83mA

50mA

1.65V/2050mA

2.3V/690mA1.2A Buck Regulator

4.5V to 15.5V

ADP5050

2.3V

1200mA

1250mA

1.3V TX Analog

1.3V TX Digital

1.8V TX

1.8V LVDS/CMOS

2TX/2RX

1.3V VDD_JESD86mA

420mA

50mA

1.3V/1950mA

ADP17402A LDO

ADP17402A LDO

4A Buck Regulator

4A Buck Regulator

3.3V VDD_GPO

3.6V/1000mA

200mA LDO

FETS ADP1755

1.2A LDO

700mA

200mA

200mA

1.3V RX Analog

1.3V RX Digital

1.8V LVDS/CMOS

1.3V VDD_JESD

3.3V VDD_GPO

ADP125500mA LDO

CLOCKING400mA

1.2A Buck Regulator

ADP125500mA LDO

ADP7104(0.5A LDO)

2TX/2RX

1.8V TX420mA

ADP121150mA LDO

900mA

110mA

50mA

1.3V/ 1920mA

3.3V/ 250mA

4.5V ~ 15.5V

ADP5054

1300mA

1000mA

1.3V Analog

1.3V Digital

1.8V TX

1.8V INTERFACE

AD9368 (2Tx)

1.8V

CH4 2.5A Buck

(Low-Noise)

1.3V VDD_JESD110mA

420mA

50mA

1.65V/2200mA

ADP1740(2A LDO)

ADP1740(2A LDO)

3.3V VDD_GPO

1.8V/ 420mA

FETS

700mA

100mA

100mA

1.3V Analog

1.3V Digital

1.8V INTERFACE

AD9368 (2Rx)

1.3V VDD_JESD

3.3V VDD_GPO

VREG EN1

EN2

EN4

EN3

CH1 6A Buck(Low-Noise)

CH3 2.5A Buck

(Low-Noise)

1.6V

100k60.4kR1 R2

NCC1

1P3DIG_PWRGD EN

EN

CH26A Buck(Low-Noise)

VREG

Power-up Sequence: 1.3V_Digital ---> 1.3V_Analog ---> 1.8V_Tx /1.8V_INTERFACE/3.3V_VDD_GPO

ENEN

ADP121(0.15A LDO)

Optimized RF Power SolutionADP5054, 3x LDOs Reduced Size

Reduced CostImproves RF Competition

14

Example 3: Power Solution for AD9162 (Barium) 16-bit 12 GSPS RF DAC

ADP5073

5Vin/12vin

AD9162/4

-1.2Va

1.2Va 2.5Va 3.3Vser

ADP7118

400mA

180mA

40mA

1.2A1.2Vd

800mA1.2Vser

ADM7154

ADP1761

ADP2386

ADP7183-180mA

ADP2370

ADP2301

ADP1761ADP2370

ADP5054Integrated TRX

Superhet Radio

AD9361

AD9368

AD9122

AD9154

AD9162

5GHzDC

CW

2.5GHz

RF Synthesis

SignalBW

HB2×

HB3×

JESD

HB2×,4×,8×

NCOINV

SINCHB2×

DATA

LATC

H

SDOSDIO

SCLKCSB SPI

DACCORE

SERDIN0+/- . .

SERDIN7+/-

SYSREF+/-SYNC+/-

CLOCKDISTRIBUTION

DACCLK+/-

TO JESD

TO DATAPATH

TX_ENABLE

OUTPUT+/-

RESETB IRQB

VREF

ISET VREF

NRZ RZ MIX

ADF4355 / ADF5355 / HMC833PLL/VCO

ADM7150

ADM7150

5V

3.3V

12Vin

Example 4: PLL/VCO Applications Diagrams

Power Management Attachment BOM : $4 to $6

$2 to $3

$2 to $3

16

eGaN FETsLDMOS FETs GaAs FETs5.0V

Zin

λ/4

Zout

λ/4

50Ω

Vd =28..50VVd =28..50VVd =10..28V

λ/4

Example 5: Generating Bias Voltage for GaN FETs

VIN =2.85V~15V

PVIN FB

VREF

EN SW

CIN

DL

COUT

ADP5073/4VNEG

(-5V/500mV, up to -35V)

AVIN

PVIN

SW

AGND

SS

SYNC

SLEW

PWRGD

COMPCc Rc

VREGCv

ON

OFF

-8.5V@100mA ADP7182

Neg LDO

-8V@100mA

L/C Filter To Attenuate The Switcher Output Ripple

1P3_Analog

AD9368C6

10nF

1.3VVIN

VIN

VIN

ENGND SS NC

SNS

VOUT

VOUT

VOUTVOUTVOUTVIN VIN

PG

ADP1740-1.3VLDO C6

10uF

C747uF

R40.1ohm

L3140nH

16mohm

C347uF

C247uF

C147uF

L12.2uH

ADP505x

VIN5V to 12V SW1

C410uF

C547uF

R30.1ohm

L2140nH

16mohm

R110K

R210K

FB1

CH12.5A Buck Regulator

1.65V

LC Filter LC Filter

AC response of the filter shows about 35dB

attenuation at 1MHz

Note: Difficult for LDO to filter the switcher fundamental switching ripple and its high-freq harmonic, 2nd stage LC filter is usually recommended in LDO’s input.

Switching Ripple & Harmonic

(100s’ kHz to MHz)

18

ADP5003 – 3A Switcher plus 3A NFET LDO

SS / RT

VFB1

SW1

PGND1

VREG

PVINSYS

C2

C1

C5

VIN:4.2V to 15V

AGND

PVIN2

VOUT2

C9

VFB2P

Int VREG

EN1

C7

SS

VBUF

COMP1

R2C4

L1

OSC

REFOUT

R7

R6

EN2

VFB2N

L2

VSET2

Low NoiseLDO Active

Filter3 A

C6

Load

SYNC_IN/SYNC_OUT

R1

VOUT2:0.6V to 3.3V

VOUT10.6V to 5V

R5

VSET1

VREG_LDO

C8

PVIN1

BUCK REGULATOR

3 A

VIN:4.2V to 15V

C3

R3

R4

Two Operation Modes Adaptive Operation Mode - Single Output Independent Operation Mode - Dual Output

3A Low-Noise NFET LDO (Active Filter) ~6µVrms Output Noise (Indp. of Vout setting)

High PSRR at low voltage headroom Adaptive Headroom Control (50mV~300mV)

32-lead 5mm x 5mm LFCSP Package (under development)

+ Voltage Droop -

>35dB PSRR

Works like “Green LDO”(High Efficiency, Low Output Noise)

10 100 1000 10000 1000000

100

200

300

400

500 Noise Spectral Density, 300mV Headroom

100mA

Frequency (Hz)NSD

(nv/

rt-Hz

)In Development to

be released July 2016

Further information

► Attach ‚Power Packs‘: AD9162/4 RF DAChttps://analog.my.salesforce.com/sfc/#version?selectedDocumentId=06932000002SwZH

► Various RF component datasheets► Power Attach brochure

General ADI Power Management Attach information:

► RF Power Attach hyperlinked presentation coming up in Q3 2016. Stay tuned…

https://analog.my.salesforce.com/sfc/#version?selectedDocumentId=06932000002SwZH



Summary

► Analog Devices RF business is more than 15% of total ADI business. Power Attach to this business makes good sense.

► RF customers are interested in a reliable proven power solution. Often there is limited power expertise at RF customers.

► There are many RF power attach examples available. Many new datasheets offer a suitable power solution.

► New power developments are targetted at RF power attach.

► ADI RF ultra low noise LDOs are best in class.

The End

rf power management attach

Engineering