review for exam 2
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Review for Exam 2. Chapters 4 and 5 Close book and close notes Bring pencil No computers or cell phones allowed. Implementations: Half-Adder. X. S. Y. C. =. Å. S. X. Y. =. ×. C. X. Y. X. Y. C. S. 0. 0. 0. 0. 0. 1. 0. 1. 1. 0. 0. 1. 1. 1. 1. 0. - PowerPoint PPT PresentationTRANSCRIPT
Review for Exam 2
Chapters 4 and 5 Close book and close notes Bring pencil No computers or cell phones allowed
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.(Hyperlinks are active in View Show mode)
Chapter 4 – Arithmetic Functions
Logic and Computer Design Fundamentals
Implementations: Half-Adder
The most common half adder implementation is:
YXCYXS
×=Å=
XY
C
S
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Implementation: Full Adder
Full Adder Schematic for bit i
with
G = generate (=AB) and
P = propagate (=AB)
Ci+1 = Gi + Pi · Ci
or: Co= (G = Generate) OR (P =Propagate AND Ci = Carry In)
Ai Bi
Ci
Ci+1
Gi
Pi
Si
Co = AB + (AB)Ci
or Ci+1 = AiBi + (AiBi )Ci
Si =(Ai Bi)Ci
4-bit Ripple-Carry Binary Adder
A four-bit Ripple Carry Adder made from four 1-bit Full Adders:
Slow adder: many delays from input to output
FA
AiBi
Ci
Si
Ci+1
Delay of a Full Adder
Assume that AND, OR gates have 1 gate delay and the XOR has 2 gate delays
Delay of the Sum and Carry bit:
Ai Bi
Ci
Ci+1
Gi
P
i
Si
CiBiAiSiÅÅ=
2 delays
Ci)BiAi(BiAiCi+1Å+=
2+2=4 delays
C0)B0 A0(B0A0C1Å+=@2
2+2=4 delays
@3
C0B0A0S0ÅÅ=
Delay of the Carry
C1)B1 A1(B1A1C2Å+=@2
@?
@4
@?
Ai Bi
Ci
Ci+1
Gi
Pi
Si
C2)B2A2(B2A2C3Å+=
@7
@2 @6
@8C4: delay 8+2 = 10
For n stage: delay of Cn: 2n+2 delays! and Sn: 2n+4 (=@Cn + 2)The bottleneck is the delay of the carry.
Delay in a Ripple-carry adder
@0
@0
@4
@4@6
@6
@8
@8@10@10
Example: 32-bit Ripple-carry has a unit gate delay of 1ns. • What is the total delay of the adder? • What is the max frequency at which it can be clocked?
One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit.
Example: 4-bit adder (n=4)
Carry Lookahead Adder
Uses a different circuit to calculate the carry out (calculates it ahead), to speed up the overall addition
Requires more complex circuits.
Trade-off: speed vs. area (complexity, cost)
4-bit Implementation
@4@6@6@6
PFA generates G and P
C1 = G0 + P0 C0
C2= G1 + P1G0 + P1P0 C0
@4
@4
@4
Carry
looka
head lo
gic
C3= G2 + P2G1 + P2P1G0 + P2P1P0 C0
4-3 b. Complements
Two type of complements:• Diminished Radix Complement of N
Defined as (rn - 1) – N, with n = number of digits or bits
1’s complement for radix 2• Radix Complement
Defined as rn - N 2’s complement in binary
As we will see shortly, subtraction is done by adding the complement of the subtrahend
If the result is negative, takes its 2’s complement
Binary 1's Complement
For r = 2, N = 0111 00112, n = 8 (8 digits):
(rn – 1) = 256 -1 = 25510 or 111111112
The 1's complement of 011100112 is then: 11111111
– 01110011 10001100
Since the 2n – 1 factor consists of all 1's and since 1 – 0 = 1 and 1 – 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).
rn – 1- N
1’s compl
Binary 2's Complement
For r = 2, N = 0111 00112, n = 8 (8 digits), we have:
(rn ) = 25610 or 1000000002
The 2's complement of 01110011 is then: 100000000 – 01110011 10001101
Note the result is the 1's complement plus 1:
0111001110001100+ 110001101
Invert bit-wise
2’s complement
rn - N
2’s compl
Alternate 2’s Complement Method
Given: an n-bit binary number, beginning at the least significant bit and proceeding upward:• Copy all least significant 0’s• Copy the first 1• Complement all bits thereafter.
2’s Complement Example:10010100
• Copy underlined bits: 100
• and complement bits to the left:01101100
3-3c. Subtraction with 2’s Complement
For n-digit, unsigned numbers M and N, find M N in base 2: Algorithm
Add the 2's complement of the subtrahend N to the minuend M:
M + (2n N) = M N + 2n
Unsigned 2’s Complement Subtraction Example 1
Find 010101002 – 010000112
01010100 01010100 –01000011 + 10111101
00010001
2’s comp
1Discard carry
84-67 17
The carry of 1 indicates that no correction of the result is required
Unsigned 2’s Complement Subtraction Example 2
Find 010000112 – 010101002
01000011 01000011 – 01010100 + 10101100
11101111 00010001
The carry of 0 indicates that a correction of the result is required.
Result = – (00010001)
0
2’s comp 67-84-17 2’s comp
Signed Binary Numbers
So far we focused on the addition and subtraction of unsigned numbers.
For SIGNED numbers:• How to represent a sign (+ or –)?
One need one more bit of information. Two ways:
• Sign + magnitude• Signed-Complements
Thus: • Positive number are unchanged• Negative numbers: use one of the above methods
Exercise
Give the sign+magnitude, 1’s complement and 2’s complement of (using minimal required bits):
Sign+Mag One’s compl. Two’s compl.
+2 010 010 010
- 2 110 101 110
+3 011 011 011
- 3 111 100 101
+0 000 000 000
- 0 100 111 000
2’s Complement Arithmetic
Addition: Simple rule• Represent negative number by its 2’s
complement. Then, add the numbers including the sign bits, discarding a carry out of the sign bits (2's complement):
• Indeed, e.x. M+(-N) M + (2n-N) If M ≥ N: (M-N) + 2n ignore carry out: M-N is the
answer in two’s complement) If M ≤ N: (M-N) + 2n = 2n – (N-M) which is 2’s
complement of the (negative) number (M-N): -(N-M).
Subtraction: M-N M + (2n-N) Form the complement of the number you are
subtracting and follow the rules for addition.
Overflow examples (continued)
18+15 33
0 1 1 1 1 0 0 1 0 0 1 0 +0 0 1 1 1 1 1 0 0 0 0 1
wrong answerdue to overflow
-31!
carries
18- 15 3
1 1 0 0 0 0 0 1 0 0 1 0 +1 1 0 0 0 1 0 0 0 0 1 1
3correct answerno overflow
Overflow occurs when the carry-in into the sign bit (most left bit) is different from the carry-out of the sign bit.
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.(Hyperlinks are active in View Show mode)
Chapter 5 – Sequential Circuits
Logic and Computer Design Fundamentals
5-1 Sequential circuit block diagram
Combina-tionalLogic
InputsOutputs
Storage Elements
State
(or present state)
NextState
CLOCK Synchronous machine
Combinatorial Logic gives:• Next state function
Next State = f(Inputs, State)
• Output function
Types of Sequential Circuits Illustra
Moore machine:• Outputs = h(State)
Mealy machine• Outputs = g(Inputs, State)
Combina-tionalLogic Storage
Elements
Inputs
State
(or present state)
NextState
OutputsComb. logic
CLOCK
Mealy
Basic (NOR) S – R Latch
Function Table:
This element is also the basic building block in SRAM memories
S (set)
R (reset)Q
Q
S R Q Q0 0 0 1 1 0 1 1
hold, no change0 1 Reset1 0 Set
0 0 not allowed, unstable (Q=Q)
Timing waveforms of NOR S-R latch
1
2
S
R
Q
Q
S
R
0
0
not allowed
Q
Q
1
0
tpd
set
reset
unstableNo change
Clocked (NOR) S-R Latch
1
2
Q
Q
S
R
Clk
• Clk=0: input has no effect: latch is always in “hold” mode
• Clk=1: latch is a regular S-R latch
Function table of the (NAND) S - R latch
S R Q Q1 10 11 00 0
S = 0, R = 0 is forbidden as input pattern
Function table:
hold, no change1 0 Set0 1 Reset1 1 not allowed, unstable
(Q=Q=1)
QS (set)
R (reset) Q
Latch with NAND
Q1
1 Q
When both S=R=1: the NAND gates act as inverters and the circuit implements two inverters: “hold mode”
Q
Q
A =A
1 AA
S
R
C
Q
Q
S
R
Clocked latch:
0 x x1 0 01 0 11 1 01 1 1
Q(t) no changeQ(t) no changeQ(t+1) = 0, ResetQ(t+1) = 1, Set Q=Q’=1 Undefined
C S R Next state Q(t+1)
D Latch (Delay latch)
S-R Latch can be usedfor at D Latch:
C
D Q
Q
D Q(t+1)0 01 1
Function table D latch:
S R Q+ Q+
0 0 hold, 0 1 0 11 0 1 01 1 0 0
SR latch:
DQ
C
QQ(t+1)
Latch issues
Latches can cause serious timing problems (races) in sequential circuits• Due to the fact that a latch is
“transparent” when the clock C = 1 The timing problems can be
prevented by using “Flip-Flops”
The Latch Timing Problem (continued)
Similar timing problems in the sequential circuits:
Combina-tionalLogic D Latch
(storage)
InputsOutputs
StateNext State
X0
• The state should change only once every new clock cycle:• C=1:
• Now the current state becomes X1 and a new state is generated by the combinational logic circuit: X2.
• However, if C=1, the new “next state” X2 will create a new current state X2!, etc…
X1X0 X2 X2
C=0
X1X1 X1X2 X2X3
1
How to solve the timing problem: use Flip-Flops
A solution to the latch timing problem is to break the closed path from In to Out within the storage element
C
D Q
Q
In Out
C: 0 1C
D Q
Q
In Out
C: 0 1
D-Latch D-Flip-Flop
In
C
Out
In
C
Out
Symbol: Master-Slave Flip-Flop
C
S
R
Q
Q
Q
Q
C
R
Q
Q
C
S
R
S Y
Y’
C
Notice; the output changes when the clock C goes low.
Symbol:S
C
R
Q
Q
Sometimes one adds:To indicate that the input responds when C=1, but the output changes when C goes to 0
Flip-Flop Problem: 1’ catching
C
S
R
Y
QSlave out
Master out
Masteractive
Slaveactive
1’ catching
wrong outputshould have been 0
C
S
R
Q
Q
Q
Q
C
R
Q
Q
C
S
R
S Y
Y’
Glitch
Flip-Flop Solution: Edge-triggered
An edge-triggered flip-flop changes values at the clock edge (transition): • responds to its input at a well-defined moment
(at the clock-transition) • ignores the pulse while it is at a constant level
Positive edge-triggeredNegative edge-triggered
Clock
In
The value of the input at the clock transition (negative or positive) determines the output
ignored
Edge-Triggered D Flip-Flop
The 1s-catching behavior is not present with D replacing S and R inputs
The change of the D flip-flop output is associated with the negative edge at the end of the pulse:
It is called a negative-edge triggered flip-flop
C
S
R
Q
QC
Q
QC
D QD
Q
No 1’s catching in the edge-triggered D Flip-Flops
CS
R
Q
QC
Q
QC
D QD
Q
C
D
Y
QSlave out
Master out
Masteractive
Slaveactive no 1’ catching
correct output
Y
Timing diagram of a (Nor) S-R Master-Slave Flip-Flop
C
Slave out
Masteractive
YMaster out
Q
S
C
R
Q
Q
S
R
SlaveactiveMaster
active
Y’
C
S
R
Q
Q
Q
Q
C
R
Q
Q
S Y
Y’
S
R
C=
undefined
undefined
undefined
Direct inputs: active-low or active-high
D flip-flop with active-low direct inputs :
Active high direct inputs:
D
C
S
R
Q
Q
D
C
S
R
Q
Q
S R C D Q Q’0 1 x x 1 01 0 x x 0 11 1 0 0 11 1 1 1 0
S R C D Q Q’0 1 x x 0 11 0 x x 1 00 0 0 0 10 0 1 1 0
Direct inputs
5-4 Sequential Circuit Analysis
Consider the following circuit:
C
D Q
Q’
C
D Q
Q'
y
xA
A
B
CLK
What does it do? How do the
outputs change when an input arrives?
input
state
s
output
Step 1: Input and output equations
Boolean equations for the inputs to the flip flops:• DA = A(t)x(t)+B(t)x(t)
• DB = A(t)x(t)
Output y• y(t) = x(t)(B(t) + A(t))
C
D Q
Q’
C
D Q
Q'
y
xA
A
B
CLK
Next State
Output
DA
DB
Pre
sent sta
te
State Table
For the example: A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) =A (t)x(t)
y(t) =x (t)(B(t) + A(t))
Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
23
row
s
(2m
+n)
row
s
m: no. of FFn: no. of inputs
Inputs of the tableOutputs of the table
0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0
State diagram convention
Moore Machine:
Stateout
in
Moore type output depends only on state
to next state
01
1
1
Mealy Machine:
Mealy type output depends on state and input
State
In/out
01
x=1/y=0
AB
y
xExample:
01
x/y’
State Diagram for the example
Graphical representation of the state table:
A B0 0
0 1 1 1
1 0
x=0/y=1 x=1/y=0
x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0
x=0/y=0
x=1/y=0
Equivalent State Example
Are there other equivalent states? Examining the new diagram,
states S1 and S2 are equivalent since• their outputs for input
0 is 1 and input 1 is 0,and
• their next state for input0 is both S0 and for input1 is both S2,
Replacing S1 and S2 by asingle state gives statediagram:
S2
1/0
0/0
S0 S1
1/0
0/1
1/0
0/1
0/0
S0 S1
1/0
0/1
1/0
Exercise: Derive the state diagram of the following Circuit
Logic Diagram:
Clock
Reset
D
QC
Q
R
D
QC
Q
R
D
QC
Q
R
A
B
C
Z
Moore or Mealy?
What is the reset state?
••
5V
5-5 Sequential Circuit Design
Idea,New
productSpecificatio
n
DA
DB
Comb.Crct.
OUT
IN?
• Word description State Diagram
• State Table
• Select type of Flip-flop
• Input equations to FF, output eq.
• Verification
State encoding
Design procedure
Specification
Component Forms of Specification• Written description• Mathematical description• Hardware description language• Tabular description• Equation description• Diagram describing operation (not just
structure)
5-6 Other Flip-Flop Types
J-K and T flip-flops• Behavior• Implementation
Basic descriptors for understanding and using different flip-flop types• Characteristic tables• Characteristic equations• Excitation tables
J-K Flip-flop
Behavior of JK flip-flop:• Same as S-R flip-flop with
J analogous to S and K analogous to R
• Except that J = K = 1 is allowed, and
• For J = K = 1, the flip-flop changes to the opposite state (toggle)
Behavior described by the characteristic table (function table):
J
C
K
Q
J K Q(t+1)0 0 Q(t) no change0 1 0 reset1 0 1 set1 1 Q(t) toggle