rev date pages pre-release schematic a 20 may 2014 all · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 d d c...

31
5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb x16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000 Ethernet x6 User Push Buttons User LEDs x22 User DIP Switches JTAG Header x4 x42 ADC Header x16 QSPI Flash PMOD x2 ADV7513 HDMI TX DAC MAX II OnBoard USB Blaster TM II & USB Interface MiniUSB 2.0 HSMC x16 x6 x31 x19 x3 x2 x37 125 MHz 100 MHz 10 MHz 50 MHz 25 MHz 100-0321401- C1 110-0321401- C1 120-0321401- C1 130-0321401- C1 140-0321401- C1 150-0321401- C1 160-0321401- C1 170-0321401- C1 180-0321401- C1 210-0321401- C1 220-0321401- C1 320-0321401- C1 Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework 1. NOTES: Pre-Release Schematic DO NOT COPY MAX 10 Development Kit Board DESCRIPTION REV DATE PAGES INITIAL REVISION A RELEASE A 20 May 2014 All 29 26 27 PAGE DESCRIPTION 5 6 28 PAGE DESCRIPTION 2 Title, Notes, Block Diagram, Rev. History 1 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Power Tree Clock Tree MAX10 Bank 1 & 2 MAX10 Bank 3 & 4 MAX10 Bank 5 & 6 MAX10 Bank 7 & 8 MAX10 Configuration MAX10 Clocks PLL ADC Filter DAC DDR3 SDRAM QSPI FLASH HSMC Port GPIO, PMOD HDMI 10/100/1000 Ethernet A 10/100/1000 Ethernet B USB to UART On-Board USB Blaster II-1 On-Board USB Blaster II-2 LED, User IO, Connector Power1 Power2 Power3 Power4 Power5 MAX10 Power 30 MAX10 Ground 31 Decoupling B 2 Sep 2014 6 Swap pin AA21 with AA22 7 Swap pin D5 with C3, and E8 with C6 23 Change resistor value, R44 to 10K, R106 to 1K, R99 to 2K, R100 to 1K, R104 to 1K 24 SW3 pin number change 24 Sep 2014 Add functional diagram 24 Change resistor value, R169 to 10K 1 26 27 Add DNI capacitor, C70 and C166 Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203 Copyright (c) 2015, Altera Corporation. All Rights Reserved. 26 Jan 2015 All Update notes for release version C 17 Mar 2015 6 Swap pin F20 with D19, F21 with C20, F18 with A21, and E19 with B20 10 Add resistors R303, R304, R305, R306, R80, R81, C355 Update the net name from BOOT_SEL to CONFIG_SEL Add resistors R307 13 9 & 23 22 & 23 Update the net name from MAX10_BYPASSn to VTAP_BYPASSn Title Size Document Number Rev Date: Sheet of 150-0321401-C1 C1 MAX10 FPGA Development Kit (6XX-44292R) B 1 31 Wednesday, March 18, 2015 Title Size Document Number Rev Date: Sheet of 150-0321401-C1 C1 MAX10 FPGA Development Kit (6XX-44292R) B 1 31 Wednesday, March 18, 2015 Title Size Document Number Rev Date: Sheet of 150-0321401-C1 C1 MAX10 FPGA Development Kit (6XX-44292R) B 1 31 Wednesday, March 18, 2015

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Page 1: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR31Gb x16

DDR31Gb x8

x4

x5

x85

USB to UART

RJ4510/100/1000Ethernet

x6

User Push Buttons

User LEDs

x22

User DIP Switches

JTAG Headerx4

x42

ADC Headerx16

QSPI Flash

PMOD x2PMOD x2 ADV7513

HDMI TX

DAC

MAX IIOn‐Board

USB BlasterTM II& USB Interface

Mini‐USB2.0

HSMC

x16

x6 x31

x19 x3

x2

x37

125 MHz

100 MHz

10 MHz

50 MHz

25 MHz

100-0321401- C1110-0321401- C1120-0321401- C1130-0321401- C1140-0321401- C1150-0321401- C1160-0321401- C1170-0321401- C1180-0321401- C1210-0321401- C1220-0321401- C1320-0321401- C1

Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework

1.

NOTES:

Pre-Release Schematic DO NOT COPY

MAX 10 Development Kit Board

DESCRIPTIONREV DATE PAGESINITIAL REVISION A RELEASEA 20 May 2014 All

29

2627

PAGE DESCRIPTION

56

28

PAGE DESCRIPTION

2Title, Notes, Block Diagram, Rev. History1

34

78910111213141516171819202122232425

Power TreeClock TreeMAX10 Bank 1 & 2MAX10 Bank 3 & 4MAX10 Bank 5 & 6MAX10 Bank 7 & 8MAX10 ConfigurationMAX10 ClocksPLLADC FilterDACDDR3 SDRAMQSPI FLASHHSMC PortGPIO, PMODHDMI10/100/1000 Ethernet A10/100/1000 Ethernet BUSB to UARTOn-Board USB Blaster II-1On-Board USB Blaster II-2LED, User IO, ConnectorPower1Power2Power3Power4Power5MAX10 Power

30 MAX10 Ground

31 Decoupling

B 2 Sep 2014 6 Swap pin AA21 with AA227 Swap pin D5 with C3, and E8 with C623 Change resistor value, R44 to 10K, R106 to 1K, R99 to 2K, R100 to 1K, R104 to 1K24 SW3 pin number change

24 Sep 2014 Add functional diagram24 Change resistor value, R169 to 10K126 27 Add DNI capacitor, C70 and C166

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.

26 Jan 2015 All Update notes for release versionC 17 Mar 2015 6 Swap pin F20 with D19, F21 with C20, F18 with A21, and E19 with B20

10 Add resistors R303, R304, R305, R306, R80, R81, C355

Update the net name from BOOT_SEL to CONFIG_SELAdd resistors R30713

9 & 2322 & 23 Update the net name from MAX10_BYPASSn to VTAP_BYPASSn

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

1 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

1 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

1 31Wednesday, March 18, 2015

Page 2: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DC INPUT12V 2A

EN2342QI4A

EN6337QI3A

12V @ 1000mA

5.0V @ 155mA

EN6337QI3A

3.3V_HSMC @ 2000mA3.3V_PMOD @ 200mA3.3V_QSPI @ 20mA3.3V_ADV7513@ 30mA3.3V_CY7C68013A @ 85mA3.3V_VCCIO_MAXII @ 12mA3.3V_VCCIO_MAX10 @ 21mA

12V_HSMC @ 1000mA

3.3V @ 2698mA

2.5V @ 1102mA2.5V_88E1111 @ 766mA2.5V_FT232R @ 15mA2.5V_VCCINT_MAXII @ 80mA2.5V_VCCIO_MAX10 @ 241mA

EP5358HUI0.6A

5V_HDMI @ 55mA5V_FT232 @ 100mA

2.5V_VCCA @ 55mA

1.8V_ADV7513 @ 53mA1.8V @ 53mA

1.2V @ 1769mA1.2V_88E1111 @ 607mA

2.5V_VCCADC

1.2V_VCC @ 1128mA

1.5V_DDR3 @ 341mA1.5V_MAX10_VCCIO @ 85mA

1.5V @ 426mA

1.2V_VCCADC

1.2V_VCCD @ 34mA

200 mm

75 mm

75 mm

14 mm

1

2

3

Power sequence

EN6337QI3A

EP5358HUI0.6A

14 mm

2.5V @ 55mA

75 mm

EP5358LUI0.6A

14 mm

Power Tree

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

2 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

2 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

2 31Wednesday, March 18, 2015

Page 3: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Si 570CMOS Clock OutputDefault 10MHz

FA‐12824MHz XTAL 

CypressCY7C68013AUSB Controller

MAX II USB Blaster

ALTERAMAX 10

Bank 1A

Bank 1B

Bank 2

Bank 3 Bank 4

Bank 5

Bank 6

Bank 7Bank 8

8Y‐25MHzXTAL

Si5338 

IN  Default 50 MHz

10/100/1000 Base – TEthernet PHY88E1111 x 2

USB_CLK

CH0

Default 25 MHz CH1

CH2

CH3

100M_DDR3

125M_LVDS

ADC

50M_MAX10

USB_CLK50M_MAXII

25M_ENET

25M_MAX10

Default 125 MHz

Default 100 MHz

Clock Tree

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

3 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

3 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

3 31Wednesday, March 18, 2015

Page 4: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 1 & 2

10/100/1000 Ethernet A

10/100/1000 Ethernet B

ADC INPUT

( VCCIO = 2.5V )

( VCCIO = 2.5V )

( VCCIO = 2.5V )

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

ADC1IN1ADC1IN2ADC2IN1

ENETA_TX_D1

ENETA_TX_EN

ENETB_RX_D0

ENETB_TX_D0ENETB_TX_D1

ENETB_RX_DVENETB_RX_ER

ADC1IN3ADC1IN4

ADC1IN6ADC1IN5

ADC1IN7

ADC2IN7

ADC2IN3ADC2IN4

ADC2IN5ADC2IN6

ADC2IN2

ADC2IN8

ADC1IN8

ENETB_RX_CRS

ENETB_RX_D2

ENETB_RX_COL

ENETB_RX_D1

ENETB_RX_D3

ENETA_TX_D3ENETA_TX_D2

ENETA_TX_D0

ENETA_TX_ER

ENETB_TX_D3ENETB_TX_ER

ENETB_TX_ENENETB_TX_D2

ENETA_RX_COL

ENETA_RX_ER

ENETA_RX_D1ENETA_RX_DV

ENETA_RX_D0ENETA_RX_CRS

ENETA_RX_D3ENETA_RX_D2

ADC1IN[8:1] 11

ADC2IN[8:1] 11

ENETA_TX_D[3:0] 18

ENETA_TX_EN 18ENETA_TX_ER 18

ENETA_RX_D[3:0] 18

ENETA_RX_DV 18ENETA_RX_ER 18ENETA_RX_CRS 18ENETA_RX_COL 18

ENETB_TX_D[3:0] 19

ENETB_TX_EN 19ENETB_TX_ER 19

ENETB_RX_D[3:0] 19

ENETB_RX_DV 19ENETB_RX_ER 19ENETB_RX_CRS 19ENETB_RX_COL 19

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

4 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

4 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

4 31Wednesday, March 18, 2015

MAX 10 LEFT BANKS

BANK-2BANK-1A

BANK-1B

10M50DAF484

U1A

DIFFIO_RX_L1N/ADC1IN1F5

DIFFIO_RX_L1P/ADC1IN2F4

DIFFIO_RX_L2N/ADC2IN1E4

DIFFIO_RX_L2P/ADC2IN8E3

DIFFIO_RX_L3N/ADC1IN3J8

DIFFIO_RX_L3P/ADC1IN4J9

DIFFIO_RX_L4N/ADC2IN3G4

DIFFIO_RX_L4P/ADC2IN4F3

DIFFIO_RX_L5P/ADC1IN6H3

DIFFIO_RX_L5N/ADC1IN5J4

DIFFIO_RX_L6N/ADC2IN5H4

DIFFIO_RX_L6P/ADC2IN6G3

DIFFIO_RX_L7N/ADC1IN7K5

DIFFIO_RX_L7P/ADC1IN8K6

DIFFIO_RX_L8P/ADC2IN2J3

DIFFIO_RX_L8N/ADC2IN7K4

DIFFIO_RX_L15NK8

VREFB1N0C1

DIFFIO_RX_L19NK2

DIFFIO_RX_L19PL2

DIFFIO_RX_L23NG1

DIFFIO_RX_L21PF2

DIFFIO_RX_L23PF1

DIFFIO_RX_L21NE1

DIFFIO_RX_L24NM4

DIFFIO_RX_L24PM3

DIFFIO_RX_L25NK1

DIFFIO_RX_L25PL1

DIFFIO_RX_L16PD2

IO_BANK1D1

DIFFIO_RX_L29NP4

DIFFIO_RX_L29PP5

DIFFIO_RX_L37NN3

DIFFIO_RX_L37PN2

DIFFIO_RX_L39NR4

DIFFIO_RX_L39PR5

DIFFIO_RX_L40NT1

DIFFIO_RX_L40PT2

DIFFIO_RX_L41NN8

DIFFIO_RX_L41PN9

DIFFIO_RX_L42NP1

DIFFIO_RX_L42PN1

DIFFIO_RX_L43NT3

DIFFIO_RX_L43PU2

DIFFIO_RX_L44NU1

DIFFIO_RX_L44PV1

DIFFIO_RX_L45NU4

DIFFIO_RX_L45PU5

DIFFIO_RX_L46NU3

DIFFIO_RX_L46PV3

DIFFIO_RX_L47NP8

DIFFIO_RX_L47PR7

DIFFIO_RX_L48NW1

DIFFIO_RX_L48PW2

DIFFIO_RX_L60NR1

DIFFIO_RX_L60PR2

VREFB2N0M2

IO_BANK2M1

DIFFIO_RX_L16ND3

DIFFIO_RX_L20NL8

DIFFIO_RX_L20PL9

DIFFIO_RX_L22NH1

DIFFIO_RX_L22PJ1

Page 5: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 3 & 4

HSMC Interface

( VCCIO = 2.5V ) ( VCCIO = 2.5V )

UART

Ethernet

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Notes:R249-R265 are 100 ohm termination resistors for LVDS RX.

HSMC_CLK_OUT_N1HSMC_CLK_OUT_P1

HSMC_CLK_OUT_N2HSMC_CLK_OUT_P2

HSMC_CLK_OUT0

HSMC_CLK_IN_N1HSMC_CLK_IN_P1

HSMC_D0HSMC_D1

HSMC_TX_D_N7HSMC_TX_D_P7

HSMC_D3HSMC_D2

HSMC_TX_D_N3HSMC_TX_D_P3

HSMC_TX_D_N2HSMC_TX_D_P2HSMC_TX_D_N4HSMC_TX_D_P4

HSMC_TX_D_N13HSMC_TX_D_P13

HSMC_RX_D_N13HSMC_RX_D_P13

HSMC_TX_D_P14HSMC_TX_D_N14

HSMC_RX_D_N14HSMC_RX_D_P14

HSMC_TX_D_P15HSMC_TX_D_N15

HSMC_RX_D_N15HSMC_RX_D_P15

HSMC_TX_D_N8HSMC_TX_D_P8

HSMC_RX_D_N8HSMC_RX_D_P8

HSMC_TX_D_N9HSMC_TX_D_P9

HSMC_RX_D_P9HSMC_RX_D_N9

HSMC_RX_D_P10HSMC_RX_D_N10

HSMC_TX_D_N10HSMC_TX_D_P10

HSMC_RX_D_P11HSMC_RX_D_N11

HSMC_TX_D_N16HSMC_TX_D_P16

HSMC_RX_D_N16HSMC_RX_D_P16

HSMC_TX_D_N11HSMC_TX_D_P11

HSMC_RX_D_P12HSMC_RX_D_N12

ENET_MDCENET_MDIO

ENETA_RESETnENETA_INTn

ENETB_INTnENETB_RESETn

HSMC_SDAHSMC_SCL

HSMC_PRSNTn

UART_RXUART_TX

HSMC_RX_D_P0HSMC_RX_D_N0

HSMC_RX_D_P1HSMC_RX_D_N1

HSMC_RX_D_N2HSMC_RX_D_P2

HSMC_RX_D_N3HSMC_RX_D_P3

HSMC_RX_D_P4HSMC_RX_D_N4

HSMC_RX_D_P5HSMC_RX_D_N5

HSMC_RX_D_P6HSMC_RX_D_N6

HSMC_RX_D_P7HSMC_RX_D_N7

HSMC_RX_D_P8HSMC_RX_D_N8

HSMC_RX_D_P9HSMC_RX_D_N9

HSMC_RX_D_P10HSMC_RX_D_N10

HSMC_RX_D_P11HSMC_RX_D_N11

HSMC_RX_D_P12HSMC_RX_D_N12

HSMC_RX_D_P13HSMC_RX_D_N13

HSMC_RX_D_P14HSMC_RX_D_N14

HSMC_RX_D_P15HSMC_RX_D_N15

HSMC_RX_D_P16HSMC_RX_D_N16

HSMC_RX_D_N3HSMC_RX_D_P3HSMC_RX_D_N4HSMC_RX_D_P4

HSMC_TX_D_N1HSMC_TX_D_P1

HSMC_TX_D_N6HSMC_TX_D_P6

HSMC_TX_D_N0HSMC_TX_D_P0

HSMC_RX_D_N0HSMC_RX_D_P0

HSMC_TX_D_N5HSMC_TX_D_P5

HSMC_RX_D_N1HSMC_RX_D_P1HSMC_RX_D_N2HSMC_RX_D_P2

HSMC_RX_D_N5HSMC_RX_D_P5

HSMC_RX_D_N6HSMC_RX_D_P6HSMC_RX_D_N7HSMC_RX_D_P7

ENETA_LED_LINK100ENETB_LED_LINK100

HSMC_D[3:0] 15

HSMC_RX_D_P[16:0] 15

HSMC_RX_D_N[16:0] 15

HSMC_CLK_IN_P[2:1] 8,15

HSMC_CLK_IN_N[2:1] 8,15

HSMC_PRSNTn 15,22

HSMC_TX_D_P[16:0] 8,15

HSMC_TX_D_N[16:0] 8,15

HSMC_CLK_OUT_P[2:1] 15

HSMC_CLK_OUT_N[2:1] 15

HSMC_CLK_OUT0 15

HSMC_CLK_IN0 8,15

ENETA_RESETn 18

ENETA_INTn 18

ENET_MDIO 18,19

ENETB_RESETn 19

ENETB_INTn 19

HSMC_SDA 15

HSMC_SCL 15

UART_RX 20UART_TX 20

ENETA_LED_LINK100 18ENETB_LED_LINK100 19

ENET_MDC 18,19

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

5 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

5 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

5 31Thursday, March 19, 2015

BANK-3 BANK-4

MAX 10 BOTTOM BANKS

10M50DAF484

U1B

DIFFIO_RX_B10NY7

DIFFIO_RX_B10PY8

DIFFIO_RX_B12NAB2

DIFFIO_RX_B12PAB3

DIFFIO_RX_B14NY3

DIFFIO_RX_B14PY4

DIFFIO_RX_B17NAA5

DIFFIO_RX_B17PAB5

DIFFIO_RX_B19NAB6

DIFFIO_RX_B19PAB7

DIFFIO_RX_B21NAA8

DIFFIO_RX_B21PAB8

DIFFIO_RX_B23NAA9

DIFFIO_RX_B23PAB9

DIFFIO_RX_B2NV4

DIFFIO_RX_B2PV5

DIFFIO_RX_B4NY1

DIFFIO_RX_B4PY2

DIFFIO_RX_B6NAA1

DIFFIO_RX_B6PAA2

DIFFIO_RX_B8NY5

DIFFIO_RX_B8PY6

DIFFIO_TX_RX_B11NW9

DIFFIO_TX_RX_B11PW10

DIFFIO_TX_RX_B13NW7

DIFFIO_TX_RX_B13PW8

DIFFIO_TX_RX_B15NR10

DIFFIO_TX_RX_B15PP10

DIFFIO_TX_RX_B16NAA6

DIFFIO_TX_RX_B16PAA7

DIFFIO_TX_RX_B1NW5

DIFFIO_TX_RX_B1PW6

DIFFIO_TX_RX_B22NY10

DIFFIO_TX_RX_B22PAA10

DIFFIO_TX_RX_B3NU6

DIFFIO_TX_RX_B3PU7

DIFFIO_TX_RX_B5NW4

DIFFIO_TX_RX_B5PW3

DIFFIO_TX_RX_B7NV7

DIFFIO_TX_RX_B7PV8

DIFFIO_TX_RX_B9NR9

DIFFIO_TX_RX_B9PP9

VREFB3N0AA3

IO_BANK3AB4

DIFFIO_RX_B25NW11

DIFFIO_RX_B25PY11

DIFFIO_RX_B27NAB10

DIFFIO_RX_B27PAB11

DIFFIO_RX_B29NAB12

DIFFIO_RX_B29PAB13

DIFFIO_RX_B35NW12

DIFFIO_RX_B35PW13

DIFFIO_RX_B38NAA14

DIFFIO_RX_B38PAB15

DIFFIO_RX_B40NAA15

DIFFIO_RX_B40PY16

DIFFIO_RX_B42NAB16

DIFFIO_RX_B42PAA16

DIFFIO_RX_B44NAB19

DIFFIO_RX_B44PAB20

DIFFIO_RX_B46NAA19

DIFFIO_RX_B46PY18

DIFFIO_RX_B50NAB21

DIFFIO_RX_B50PAA20

DIFFIO_RX_B58NAB17

DIFFIO_RX_B58PAB18

DIFFIO_TX_RX_B24NV11

DIFFIO_TX_RX_B24PV12

DIFFIO_TX_RX_B26NR12

DIFFIO_TX_RX_B26PP12

DIFFIO_TX_RX_B28NAA11

DIFFIO_TX_RX_B28PAA12

DIFFIO_TX_RX_B34NV13

DIFFIO_TX_RX_B34PW14

DIFFIO_TX_RX_B36NR13

DIFFIO_TX_RX_B36PP13

DIFFIO_TX_RX_B37NY13

DIFFIO_TX_RX_B37PY14

DIFFIO_TX_RX_B39NV14

DIFFIO_TX_RX_B39PW15

DIFFIO_TX_RX_B41NU15

DIFFIO_TX_RX_B41PV16

DIFFIO_TX_RX_B43NAA17

DIFFIO_TX_RX_B43PY17

DIFFIO_TX_RX_B45NV15

DIFFIO_TX_RX_B45PW16

DIFFIO_TX_RX_B49NY19

DIFFIO_TX_RX_B49PW18

VREFB4N0AA13

IO_BANK4AB14

R265 DNI

R256 DNI

R264 DNI

R255 DNI

R252 DNI

R263 DNI

R254 DNI

R251 DNI

R262 DNI

R250 DNI

R261 DNI

R253 DNI

R260 DNI

R259 DNI

R258 DNI

R257 DNI

R249 DNI

Page 6: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 5 & 6

DDR3 Interface

( VCCIO = 1.5V ) ( VCCIO = 1.5V )

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

DDR3_DM0DDR3_RESETn

DDR3_A9

DDR3_DQS_P0

DDR3_DQ6

DDR3_DQ12

DDR3_DQ0

DDR3_DQS_N0

DDR3_DQ10

DDR3_DM2

DDR3_DQS_P2DDR3_DQS_N2

VREF_MAX10

DDR3_DQ19

USER_PB0USER_PB1USER_PB2USER_PB3VREF_MAX10

RUPRDN

DDR3_DM1

DDR3_CLK_PDDR3_CLK_N

USER_DIPSW0USER_DIPSW1USER_DIPSW2USER_DIPSW3USER_DIPSW4

USER_LED0USER_LED1USER_LED2

DDR3_DQ1DDR3_DQ3

DDR3_DQ7

DDR3_DQ5

DDR3_DQ14DDR3_DQ8

DDR3_DQ15

DDR3_DQ13

DDR3_DQ9

DDR3_DQ11

DDR3_DQ21

DDR3_DQ22

DDR3_DQ23DDR3_DQ17

DDR3_DQ4DDR3_DQ2

DDR3_CKE

DDR3_DQ20

DDR3_DQ18

DDR3_DQ16

DDR3_A12

DDR3_A13DDR3_A8

DDR3_WEn

DDR3_A6

DDR3_RASn

DDR3_A11

DDR3_A10

DDR3_CASn

DDR3_CSn

DDR3_A5

DDR3_BA1

DDR3_A0

DDR3_ODT

DDR3_A3

DDR3_BA0

DDR3_BA2

USER_LED3USER_LED4

DDR3_A7

DDR3_A1

DDR3_A2

DDR3_A4

1.5V_VCCIO

VREF_MAX10

VREF_MAX10

1.5V_VCCIO

DDR3_DQS_P[2:0] 8,13

DDR3_DQS_N[2:0] 8,13

DDR3_DQ[23:0] 13

DDR3_CKE 13DDR3_CLK_P 13DDR3_CLK_N 13

DDR3_WEn 13DDR3_RASn 13DDR3_CASn 13

DDR3_RESETn 13

DDR3_A[13:0] 13

DDR3_BA[2:0] 13

DDR3_DM[2:0] 13

USER_PB[3:0] 23

USER_DIPSW[4:0] 23

USER_LED[4:0] 23

DDR3_CSn 13

DDR3_ODT 13

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

6 31Friday, March 20, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

6 31Friday, March 20, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

6 31Friday, March 20, 2015

R1871.00k

R2 49.9

C330

DNI

C331

0.1uF

R2101.00k

R1 49.9

C329

0.1uF

BANK-5 BANK-6

MAX 10 RIGHT BANKS

10M50DAF484

U1C

DIFFIO_RX_R19NU19

DIFFIO_RX_R19PV18

DIFFIO_RX_R1N/RDNU17 DIFFIO_RX_R1P/RUPU18

DIFFIO_RX_R20NW22

DIFFIO_RX_R20PY22

DIFFIO_RX_R21NW20

DIFFIO_RX_R21PW19

DIFFIO_RX_R22NY21

DIFFIO_RX_R22PY20

DIFFIO_RX_R23NU20

DIFFIO_RX_R23PV20

DIFFIO_RX_R24NV22

DIFFIO_RX_R24PV21

DIFFIO_RX_R25N/DQ1RR14

DIFFIO_RX_R25P/DQ1RR15

DIFFIO_RX_R26NT22

DIFFIO_RX_R26PT21

DIFFIO_RX_R27N/DM1RT18

DIFFIO_RX_R27P/DQ1RT19

DIFFIO_RX_R28N/DQ1RR20

DIFFIO_RX_R28P/DQ1RT20

DIFFIO_RX_R29NU22

DIFFIO_RX_R29PU21

DIFFIO_RX_R2NAA22

DIFFIO_RX_R2PAA21

DIFFIO_RX_R30N/DQ1RP14

DIFFIO_RX_R30P/DQ1RP15

DIFFIO_RX_R31NN22

DIFFIO_RX_R31PP21

DIFFIO_RX_R32N/DQSN1RP18

DIFFIO_RX_R32P/DQS1RR18

DIFFIO_RX_R33N/DQ1RP20

DIFFIO_RX_R33P/DQ1RP19

DIFFIO_RX_R34NL22

DIFFIO_RX_R34PM21

DIFFIO_RX_R35NM22

DIFFIO_RX_R35PN21

IO_BANK5R22 VREFB5N0P22

DIFFIO_RX_R39NH21

DIFFIO_RX_R39PH22

DIFFIO_RX_R41NJ21

DIFFIO_RX_R41PJ22

DIFFIO_RX_R42NG19

DIFFIO_RX_R42PG20

DIFFIO_RX_R43NF22

DIFFIO_RX_R43PG22

DIFFIO_RX_R44N/DQ2RM14

DIFFIO_RX_R44P/DQ2RM15

DIFFIO_RX_R45NE21

DIFFIO_RX_R45PE22

DIFFIO_RX_R46N/DM2RN19

DIFFIO_RX_R46P/DQ2RN18

DIFFIO_RX_R47P/DQ2RM20

DIFFIO_RX_R47N/DQ2RN20

DIFFIO_RX_R48NF20

DIFFIO_RX_R48PF21

VREFB6N0D21

DIFFIO_RX_R49PD22

DIFFIO_RX_R51N/DQ2RL18

DIFFIO_RX_R51P/DQ2RM18

DIFFIO_RX_R52N/DQ2RL20

DIFFIO_RX_R52P/DQ2RL19

DIFFIO_RX_R53NF18

DIFFIO_RX_R53PE19

DIFFIO_RX_R54NE20

DIFFIO_RX_R54PF19

DIFFIO_RX_R55N/DQSN3RK15

DIFFIO_RX_R55P/DQS3RK14

DIFFIO_RX_R56ND19

DIFFIO_RX_R56PC20

DIFFIO_RX_R57N/DQ3RJ18

DIFFIO_RX_R57P/DQ3RK18

DIFFIO_RX_R58N/DQ3RK20

DIFFIO_RX_R58P/DQ3RK19

DIFFIO_RX_R59NE17

DIFFIO_RX_R59PF17

DIFFIO_RX_R60NB21

DIFFIO_RX_R60PB22

DIFFIO_RX_R61N/DM3RJ15

DIFFIO_RX_R61P/DQ3RJ14

DIFFIO_RX_R62NA21

DIFFIO_RX_R62PB20

DIFFIO_RX_R63N/DQ3RH18

DIFFIO_RX_R63P/DQ3RH19

DIFFIO_RX_R64N/DQ3RH20

DIFFIO_RX_R64P/DQ3RJ20

DIFFIO_RX_R70N/CK#_6E18

DIFFIO_RX_R70P/CK_6D18

DIFFIO_RX_R49NC22

IO_BANK6C21

C182

0.1uF

Page 7: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 7 & 8

HDMI TX

MAX10 USB INTERFACE

QSPI FLASH

DAC

PMOD

( VCCIO = 3.3V ) ( VCCIO = 3.3V )

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

HDMI_TX_D0HDMI_TX_D1

HDMI_TX_D4

HDMI_TX_HS

HDMI_TX_INT

PMODA_IO0PMODA_IO1

QSPI_IO2QSPI_IO3QSPI_CLKQSPI_CSn

USB_SCL

USB_RESETnUSB_OEn

DAC_SYNCDAC_SCLKDAC_DIN

PMODA_IO2PMODA_IO3PMODA_IO4PMODA_IO5PMODA_IO6PMODA_IO7

JTAG_SAFE

USB_DATA4

USB_DATA2

USB_DATA5

USB_DATA7USB_DATA0

USB_DATA3

USB_DATA6

USB_DATA1

USB_FULL

USB_SDA

USB_EMPTY

USB_RDn

USB_ADDR1USB_WRn

USB_ADDR0

HDMI_SCL

HDMI_TX_D15

HDMI_TX_D10

HDMI_TX_D13

HDMI_TX_D11

HDMI_TX_D16

HDMI_TX_D7

HDMI_TX_D14

HDMI_TX_DE

HDMI_SDA

HDMI_TX_VS

HDMI_TX_D23

HDMI_TX_D3

HDMI_TX_D22

HDMI_TX_D5

HDMI_TX_D21

HDMI_TX_D2

HDMI_TX_D20

HDMI_TX_D6

HDMI_TX_D19

HDMI_TX_D8

HDMI_TX_D18

HDMI_TX_D9

HDMI_TX_D17

HDMI_TX_D12

PMODB_IO4PMODB_IO5

PMODB_IO2

PMODB_IO7

PMODB_IO3

PMODB_IO6

PMODB_IO1

QSPI_IO1

PMODB_IO0

QSPI_IO0

HDMI_TX_INT 17

HDMI_TX_DE 17

HDMI_TX_VS 17

HDMI_TX_HS 17

HDMI_TX_D[23:0] 17

PMODA_IO[7:0] 16

USB_DATA[7:0] 22

USB_SDA 22

USB_ADDR[1:0] 22

USB_SCL 22

USB_RESETn 22USB_OEn 22USB_RDn 22USB_WRn 22

USB_EMPTY 22USB_FULL 22

QSPI_IO[3:0] 14

QSPI_CLK 14

QSPI_CSn 14

DAC_SYNC 12

DAC_SCLK 12

DAC_DIN 12

HDMI_SDA 17

HDMI_SCL 17

JTAG_SAFE 22

PMODB_IO[7:0] 16

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

7 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

7 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

7 31Wednesday, March 18, 2015

BANK-7 BANK-8

MAX 10 TOP BANKS

10M50DAF484

U1D

DIFFIO_RX_T10NA17

DIFFIO_RX_T10PA18

DIFFIO_RX_T15NC15

DIFFIO_RX_T15PC16

DIFFIO_RX_T16NA16

DIFFIO_RX_T16PB16

DIFFIO_RX_T17NJ13

DIFFIO_RX_T17PH14

DIFFIO_RX_T18NC13

DIFFIO_RX_T18PC14

DIFFIO_RX_T19NB14

DIFFIO_RX_T19PA14

DIFFIO_RX_T1NE15

DIFFIO_RX_T1PE16

DIFFIO_RX_T20NE13

DIFFIO_RX_T20PD14

DIFFIO_RX_T21PE12

DIFFIO_RX_T21ND13

DIFFIO_RX_T22NJ12

DIFFIO_RX_T22PH13

DIFFIO_RX_T23NA12

DIFFIO_RX_T23PA13

DIFFIO_RX_T24ND12

DIFFIO_RX_T24PC12

DIFFIO_RX_T25NA10

DIFFIO_RX_T25PA11

DIFFIO_RX_T26NC10

DIFFIO_RX_T26PC11

DIFFIO_RX_T27NB11

DIFFIO_RX_T27PB12

DIFFIO_RX_T28NJ11

DIFFIO_RX_T28PH12

DIFFIO_RX_T31NB8

DIFFIO_RX_T31PA9

DIFFIO_RX_T2NC17

DIFFIO_RX_T2PD17

DIFFIO_RX_T30NC9

DIFFIO_RX_T30PB10

DIFFIO_RX_T29PA7

DIFFIO_RX_T29NA8

DIFFIO_RX_T5NF15

DIFFIO_RX_T5PF16

DIFFIO_RX_T6NB19

DIFFIO_RX_T6PC19

DIFFIO_RX_T7NB17

DIFFIO_RX_T7PC18

DIFFIO_RX_T8NA19

DIFFIO_RX_T8PA20

DIFFIO_RX_T9NE14

DIFFIO_RX_T9PD15

IO_BANK7A15 VREFB7N0B15

DIFFIO_RX_T39NC7

DIFFIO_RX_T39PC8

DIFFIO_RX_T41NA6

DIFFIO_RX_T41PB7

DIFFIO_RX_T42PD8

DIFFIO_RX_T43NA4

DIFFIO_RX_T43PA5

DIFFIO_RX_T44NE9

DIFFIO_RX_T45PA2

DIFFIO_RX_T45NA3

DIFFIO_RX_T46PB3

DIFFIO_RX_T46NB4

DIFFIO_RX_T49ND5

DIFFIO_RX_T49PC5

DIFFIO_RX_T51NB1

DIFFIO_RX_T51PB2

DIFFIO_RX_T53PC3

VREFB8N0D7

IO_BANK8C6

DIFFIO_RX_T47PB5

DIFFIO_RX_T47NC4

DIFFIO_RX_T48PE8

DIFFIO_RX_T53NC2

Page 8: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Clock

HDMI TX

From PLL

HSMC

DDR3

Ethernet

( VCCIO = 2.5V )

( VCCIO = 2.5V )

( VCCIO = 2.5V )

( VCCIO = 1.5V )

( VCCIO = 3.3V )

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

HSMC_CLK_IN_N2HSMC_CLK_IN_P2

ENETA_GTX_CLKENETB_GTX_CLK

CLK_DDR3_100_NCLK_DDR3_100_P

CLK_LVDS_125_NCLK_LVDS_125_P

HSMC_TX_D_N12HSMC_TX_D_P12

DDR3_DQS_P1DDR3_DQS_N1

CLK_LVDS_125_N

CLK_LVDS_125_P

CLK_DDR3_100_N

CLK_DDR3_100_P

ENETA_RX_CLKENETB_RX_CLK

CLK_50_MAX10

CLK_10_ADC

HSMC_CLK_IN_P2

HSMC_CLK_IN_N2HSMC_CLK_IN_N1

HSMC_CLK_IN_P1

HDMI_TX_CLK

ENETA_TX_CLKENETB_TX_CLK

IP_SECURITY

HSMC_CLK_IN0

USB_CLK

CLK_25_MAX10

HSMC_CLK_IN_P[2:1] 5,15

HSMC_CLK_IN_N[2:1] 5,15

HDMI_TX_CLK 17

HSMC_CLK_IN0 15

CLK_10_ADC 10

CLK_50_MAX10 10

CLK_LVDS_125_P 10

CLK_LVDS_125_N 10

CLK_DDR3_100_P 10

CLK_DDR3_100_N 10

ENETA_RX_CLK 18ENETB_RX_CLK 19ENETA_TX_CLK 18ENETB_TX_CLK 19

ENETA_GTX_CLK 18ENETB_GTX_CLK 19

DDR3_DQS_N1 13DDR3_DQS_P1 13

HSMC_TX_D_N12 15HSMC_TX_D_P12 15

IP_SECURITY 16

USB_CLK 21

CLK_25_MAX10 10

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

8 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

8 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

8 31Thursday, March 19, 2015

R33100

R52100

BANK-2

MAX 10 CLOCK

BANK-3

BANK-4

BANK-6

BANK-8

10M50DAF484

U1E

DIFFIO_RX_L28N/CLK0NN4

DIFFIO_RX_L28P/CLK0PN5

DIFFIO_RX_L36N/CLK1NM8

DIFFIO_RX_L36P/CLK1PM9

DIFFIO_TX_RX_B18N/CLK6NV9

DIFFIO_TX_RX_B18P/CLK6PV10

DIFFIO_TX_RX_B20N/CLK7NR11

DIFFIO_TX_RX_B20P/CLK7PP11

DIFFIO_RX_R38N/CLK2NN15

DIFFIO_RX_R38P/CLK2PN14

DIFFIO_RX_R40N/CLK3NK21

DIFFIO_RX_R40P/CLK3PK22

DIFFIO_RX_T38N/CLK4NE10

DIFFIO_RX_T38P/CLK4PE11

DIFFIO_RX_T40P/CLK5PJ10

DIFFIO_RX_T40N/CLK5NH11

DIFFIO_RX_L38N/DPCLK0P3

DIFFIO_RX_L38P/DPCLK1R3

DIFFIO_RX_L59N/PLL_L_CLKOUTNT5

DIFFIO_RX_L59P/PLL_L_CLKOUTPT6

DIFFIO_TX_RX_B57N/PLL_B_CLKOUTNW17

DIFFIO_TX_RX_B57P/PLL_B_CLKOUTPV17

DIFFIO_RX_R50N/DPCLK2/DQSn2RL15

DIFFIO_RX_R50P/DPCLK3/DQS2RL14

DIFFIO_RX_R69N/PLL_R_CLKOUTNG17

DIFFIO_RX_R69P/PLL_R_CLKOUTPH17

DIFFIO_RX_T52N/PLL_T_CLKOUTNE6

DIFFIO_RX_T52P/PLL_T_CLKOUTPD6

R94DNI

R95DNI

Page 9: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Configuration

JTAG

Configuration

( VCCIO = 2.5V ) ( VCCIO = 3.3V )

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

MAX10_JTAG_TCK

MAX10_JTAG_TDIMAX10_JTAG_TDO

MAX10_JTAG_TMS

MAX10_JTAG_ENCONFIG_SELPULSE_NCONFIG

MAX10_CONF_DONE

CPU_RESETn

MAX10_NSTATUS

3.3V

CONFIG_SEL 23PULSE_NCONFIG 23

MAX10_JTAG_TDO 22

MAX10_JTAG_EN 22MAX10_JTAG_TMS 22MAX10_JTAG_TCK 22MAX10_JTAG_TDI 22

MAX10_CONF_DONE 21CPU_RESETn 23MAX10_NSTATUS 21

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

9 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

9 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

9 31Wednesday, March 18, 2015

MAX 10 Configuration

BANK-1B BANK-8

10M50DAF484

U1F

DIFFIO_RX_L15P/JTAGENK9

DIFFIO_RX_L17P/TCKG2

DIFFIO_RX_L17N/TMSH2

DIFFIO_RX_L18N/TDIL4

DIFFIO_RX_L18P/TDOM5

DIFFIO_RX_T42N/DEV_CLRND9

DIFFIO_RX_T44P/DEV_OED10

NCONFIGH9

CONFIG_SELH10

DIFFIO_RX_T48N/CRC_ERRORF7

DIFFIO_RX_T50P/NSTATUSG9

DIFFIO_RX_T50N/CONF_DONEF8 R6 10K

R8 10K

Page 10: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Programmable Clock for ADC

PLL

Notes:Use Clock Control GUIDefault 10MHz

I2C Address 55 HEX

LVDS

Notes:Si5338 Programmable Oscillator Use Clock Control GUI(Defaults 50MHz, 25MHz, 125MHz, 100MHz)

I2C Address 70 HEX

Programmable Clock

Clock control

Clock out

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

CLK_LVDS_125_N

I2C_MAXII_SCL

SI570_EN

XTAL_25M_Si5338A_P

SI5338A_INTR

XTAL_25M_Si5338A_N

CLK_LVDS_125_CNCLK_LVDS_125_CP

2.5V_SI5338

CLK_DDR3_100_CNCLK_DDR3_100_CP

I2C_MAXII_SDA CLK_10_ADC

CLK_50_MAX10CLK_50_MAXII

CLK_25_MAX10CLK_25_ENETCLK_25_ENET_R

CLK_25_MAX10_R

CLK_50_MAXII_RCLK_50_MAX10_R

CLK_LVDS_125_P

I2C_MAXII_SDA

I2C_MAXII_SCL CLK_DDR3_100_NCLK_DDR3_100_P

2.5V

2.5V

2.5V

1.5V

1.5V

CLK_10_ADC 8

CLK_50_MAX10 8

CLK_50_MAXII 21

CLK_25_ENET 18,19

CLK_25_MAX10 8

CLK_LVDS_125_P 8

CLK_LVDS_125_N 8

CLK_DDR3_100_P 8

CLK_DDR3_100_N 8

I2C_MAXII_SDA 22,28

I2C_MAXII_SCL 22,28

SI570_EN 22

SI5338A_INTR 22

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

10 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

10 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

10 31Wednesday, March 18, 2015

C3 DNI

R3062.0K

C8

0.1uF

R3042.0K

R79 22.0

X1

Si570

OE2

NC1

GND3

CLK+4

CLK-5

VCC6

SDA7

SCL8

R167 22.0

Y125.00MHz

13

24

R810

C12 0.1uF

R73 22.0

C14 0.1uF

R78 22.0

C5

0.1uF

L1

BLM15AG221SN1300mA

C4

0.1uF

C13 0.1uF

R7 4.7k

C7

0.1uFC10 DNI

R77 22.0

R3052.0K

C6

0.1uF

C9

0.1uF

C1

10uF

R3032.0K

R74 22.0

C355

0.1uF

R172 22.0

R10 4.7k

R80DNI

U2

Si5338A-CUSTOM

CLKIN_P1

CLKIN_N2

CLKIN3

I2C_LSB4

FDBK_P5

FDBK_N6

VDD17

VDD224

VDDO311

VDDO215

VDDO116

VDDO020

INTR8

CLK3B9

CLK3A10SCL

12

CLK2B13

CLK2A14

CLK1B17

CLK1A18

SDA19

CLK0B21

CLK0A22

RSVD_GND23

EPAD25

C11 0.1uF

C2

0.1uF

Page 11: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADC Filter

Notes: Put the 1pF capacitors close to each MAX10 analog pin.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

ADC1IN1ADC1_CH0

ADC1_CH1 ADC1IN2

ADC1IN3ADC1_CH2

ADC1IN4ADC1_CH3

ADC1IN5ADC1_CH4

ADC1IN6ADC1_CH5

ADC1IN7ADC1_CH6

ADC1IN8ADC1_CH7

ADC2_CH0 ADC2IN1

ADC2IN2ADC2_CH1

ADC2_CH2 ADC2IN3

ADC2_CH3 ADC2IN4

ADC2_CH4 ADC2IN5

ADC2_CH5 ADC2IN6

ADC2_CH6 ADC2IN7

ADC2_CH7 ADC2IN8

REFGND

ADC1_CH[7:0] 16

ADC2_CH[7:0] 16

ADC1IN[8:1] 4

ADC2IN[8:1] 4

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

11 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

11 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

11 31Wednesday, March 18, 2015

R19 10

C21

1pF

R22 10

R24 10

R18 10

R16 10

R27 10

C23

1pF

R26 10

C19

1pF

R20 10

C16

1pF

R30 10

C25

1pF

R29 10

C28

1pF

R17 10

C22

1pF

TP1

C18

1pF

C27

1pF

R21 10

R15 10

C24

1pF

R23 10

C26

1pF

C17

1pF

C30

1pF

R25 10

C15

1pF

C20

1pF

C29

1pF

R28 10

Page 12: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAC

Notes: 1. Put 0.1uF capactor close to VREF pin.2. Everything related to this DAC should be connected to analog ground.3. For better DC accuracy, VFB should be connected to VOUT at loadpoints.4. Thermal pad should be connected to GND.

Put this pull-up to digital area.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

REF_2.5V

3.3V_DAC

DAC_DIN

DAC_SCLK

DAC_SYNC

VFB DACOUT_SMA

3.3V_DACREF_2.5V

3.3V3.3V_DAC3.3V

DAC_SYNC 7

DAC_SCLK 7

DAC_DIN 7

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

12 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

12 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

12 31Wednesday, March 18, 2015

L10

BLM15AG221SN1300mA

C34

0.1uF

R36 0

C31

0.1uF

U33

DAC8551

SYNC5

SCLK6

DIN7

VREF2

VDD1

VFB3

VOUT4

GND8

R35 0

C33

0.47uF

C32

10uFR31DNI

R37 0

R34 0

U4

REF3125

VIN1

VOUT2

GND3

J11

2 3 4 5

Page 13: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR3 SDRAM

FPGA InterfaceDDR3 SDRAM A (64Mx16) DDR3 SDRAM B (128Mx8)

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

DDR3_DM0DDR3_DM1

DDR3_CLK_P

DDR3_CSnDDR3_WEnDDR3_RASnDDR3_CASn

DDR3_RESETnDDR3_ODT

DDR3_BA2

DDR3_CKE

DDR3_BA1

DDR3_CLK_N

DDR3_BA0

DDR3_A13

DDR3_A5

DDR3_A1

DDR3_A6

DDR3_A11

DDR3_A0

DDR3_A7

DDR3_A12

DDR3_A2

DDR3_A8

DDR3_A3

DDR3_A9

DDR3_A4

DDR3_A10

DDR3_DQS_P0

DDR3_DQ5

DDR3_DQ11

DDR3_DQ6

DDR3_DQ12

DDR3_DQ0DDR3_DQ1

DDR3_DQS_N0

DDR3_DQ7

DDR3_DQ13

DDR3_DQS_P1

DDR3_DQ2

DDR3_DQS_N1

DDR3_DQ8

DDR3_DQ14

DDR3_DQ3

DDR3_DQ9

DDR3_DQ15

DDR3_DQ4

DDR3_DQ10

DDR3_ZQ1

DDR3_CLK_P DDR3_CLK_N

DDR3_A5

DDR3_A1

DDR3_A6

DDR3_A11

DDR3_A0

DDR3_A7

DDR3_A12

DDR3_A2

DDR3_A8

DDR3_A3

DDR3_A9

DDR3_A4

DDR3_A10

DDR3_DM2

DDR3_BA2

DDR3_BA0DDR3_BA1

DDR3_DQS_P2DDR3_DQS_N2

DDR3_ZQ2

DDR3_A13

DDR3_CLK_PDDR3_CKE

DDR3_CLK_N

DDR3_RESETnDDR3_ODT

DDR3_CSnDDR3_WEnDDR3_RASnDDR3_CASn

DDR3_DQ20DDR3_DQ21DDR3_DQ22

DDR3_DQ17

DDR3_DQ23

DDR3_DQ16

DDR3_DQ18DDR3_DQ19

DDR3_RESETnDDR3_CKE

DDR3_A13

VREF_DDR3

1.5V

1.5V

VREF_DDR3

1.5V

VREF_DDR3

1.5V

DDR3_DQS_P[2:0] 6,8

DDR3_DQS_N[2:0] 6,8

DDR3_DQ[23:0] 6

DDR3_BA[2:0] 6

DDR3_DM[2:0] 6

DDR3_A[13:0] 6

DDR3_CKE 6DDR3_CLK_P 6DDR3_CLK_N 6

DDR3_CSn 6DDR3_WEn 6DDR3_RASn 6DDR3_CASn 6

DDR3_RESETn 6DDR3_ODT 6

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

13 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

13 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

13 31Wednesday, March 18, 2015

R233 2.0K

C49

0.1uF

R401.00k

R39

240

C324

DNI

V2

R38

240C327

0.1uF

R244 2.0K

DDR3 DeviceU6

IS43TR81280A -125JBLI

A0K3

A1L7

A10/APH7

A11M7

A12/BC#K7

A13N3

A2L3

A3K2

A4L8

A5L2

A6M8

A7M2

A8N8

A9M3

BA0J2

BA1K8

BA2J3

CAS#G3

CS#H2

CK#G7 CKF7 CKEG9

DM/TDQSB7

DQ0B3

DQ1C7

DQ2C2

DQ3C8

DQS#D3 DQSC3

NC5H9

NC1A3

NC2F1

NC3F9

NC4H1

NC6J7

NC7N7

DQ4E3

DQ5E8

DQ6D2

DQ7E7

NU/TDQS#A7

ODTG1

RAS#F3

RESET#N2

VDDA2 VDDA9 VDDD7 VDDG2 VDDG8 VDDK1 VDDK9 VDDM1 VDDM9

VDDQB9

VDDQC1

VDDQE2 VDDQE9

VREFCAJ8

VREFDQE1

VSSA1

VSSA8

VSSB1

VSSD8

VSSF2

VSSF8

VSSJ1

VSSJ9

VSSL1

VSSL9

VSSN1

VSSN9

VSSQB2

VSSQB8

VSSQC9

VSSQD1

VSSQD9

WE#H3

ZQH8

C326

0.1uF

R421.00k

C64

0.1uF

V1

C325

0.1uF

DDR3 DeviceU5

IS43TR16640A -125JBLI

A5P2 A4P8 A3N2 A2P3 A1P7 A0N3

NC4L9

A10/APL7

A11R7

A12/BC#N7

RESET#T2

VSSQB1

VSSQB9

VSSQD1

A9R3 A8T8 A7R2 A6R8

NC5M7

NC1J1

NC3L1

ZQL8

CK#K7

WE#L3

CKEK9

ODTK1

NC2J9

RAS#J3

CKJ7

CS#L2

BA0M2

BA1N8

BA2M3

CAS#K3

DMUD3

NC6T7

DMLE7

VDDB2

VDDD9

VDDG7

VDDK2

VSSA9

VSSB3

VSSE1

VSSG8

DQL0E3

DQSLF3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

DQSUC7DQSL#G3

DQSU#B7

VSSQD8

VSSQE2

VSSQE8

VSSQF9

VDDQH9

VDDK8

VDDN1

VDDN9

VDDR1

VDDR9

VREFDQH1

VREFCAM8

VSSQG1

VSSQG9

VDDQA1

VDDQA8

VDDQC1

VDDQC9

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VSSJ2

VSSJ8

VSSM1

VSSM9

VSSP1

VSSP9

VSST1

VSST9

NC(A13)T3

R41

100

R307 2.0K

Page 14: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

QSPI FLASH

QSPI FLASH

Notes:Place capacitors near FLASH device.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

3.3V

3.3V

QSPI_IO07QSPI_IO17QSPI_IO27QSPI_IO37

QSPI_CLK7

QSPI_CSn7

QSPI_RESETn 21

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

14 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

14 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

14 31Wednesday, March 18, 2015

C66

0.1uF

U7

N25Q512A83GSF40F

PART_NUMBER = N25Q512A83GSF40FManufacturer = Micron

DQ015

DQ18

DQ2/VPP/W#9

DQ3/HOLD#1

C16

S#7

RESET3

DNU24

DNU35

DNU46

DNU511

DNU612

DNU713

DNU814

VSS10

VCC2

C65

4.7uF

TP2

R98 DNI

R432.0K

Page 15: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HSMC PortFPGA Interface

Note:Place capacitors near HSM connector.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

HSMC_TX_D_P0HSMC_TX_D_N0

HSMC_TX_D_P1HSMC_TX_D_N1

HSMC_TX_D_P2HSMC_TX_D_N2

HSMC_TX_D_P3HSMC_TX_D_N3

HSMC_TX_D_P4HSMC_TX_D_N4

HSMC_TX_D_P5HSMC_TX_D_N5

HSMC_TX_D_P6HSMC_TX_D_N6

HSMC_TX_D_P7HSMC_TX_D_N7

HSMC_CLK_OUT_P1HSMC_CLK_OUT_N1

HSMC_TX_D_P8HSMC_TX_D_N8

HSMC_TX_D_P9HSMC_TX_D_N9

HSMC_TX_D_P10HSMC_TX_D_N10

HSMC_TX_D_P11HSMC_TX_D_N11

HSMC_TX_D_P12HSMC_TX_D_N12

HSMC_TX_D_P13HSMC_TX_D_N13

HSMC_TX_D_P14HSMC_TX_D_N14

HSMC_TX_D_P15HSMC_TX_D_N15

HSMC_TX_D_P16HSMC_TX_D_N16

HSMC_CLK_OUT_P2HSMC_CLK_OUT_N2

HSMC_D0HSMC_D2

HSMC_RX_D_P0HSMC_RX_D_N0

HSMC_RX_D_P1HSMC_RX_D_N1

HSMC_RX_D_P2HSMC_RX_D_N2

HSMC_RX_D_P3HSMC_RX_D_N3

HSMC_RX_D_P4HSMC_RX_D_N4

HSMC_RX_D_P5HSMC_RX_D_N5

HSMC_RX_D_P6HSMC_RX_D_N6

HSMC_RX_D_P7HSMC_RX_D_N7

HSMC_CLK_IN_P1HSMC_CLK_IN_N1

HSMC_RX_D_P8HSMC_RX_D_N8

HSMC_RX_D_P9HSMC_RX_D_N9

HSMC_RX_D_P10HSMC_RX_D_N10

HSMC_RX_D_P11HSMC_RX_D_N11

HSMC_RX_D_P12HSMC_RX_D_N12

HSMC_RX_D_P13HSMC_RX_D_N13

HSMC_RX_D_P14HSMC_RX_D_N14

HSMC_RX_D_P15HSMC_RX_D_N15

HSMC_RX_D_P16HSMC_RX_D_N16

HSMC_CLK_IN_P2HSMC_CLK_IN_N2HSMC_PRSNTn

HSMC_D1HSMC_D3

HSMC_PRSNTn

3.3V 12V

12V 3.3V

2.5V

HSMC_D[3:0] 5

HSMC_TX_D_P[16:0] 5,8

HSMC_TX_D_N[16:0] 5,8

HSMC_RX_D_P[16:0] 5

HSMC_RX_D_N[16:0] 5

HSMC_CLK_IN_P[2:1] 5,8

HSMC_CLK_IN_N[2:1] 5,8

HSMC_CLK_OUT_P[2:1] 5

HSMC_CLK_OUT_N[2:1] 5

HSMC_SDA5HSMC_JTAG_TCK22HSMC_JTAG_TDO22HSMC_CLK_OUT05

HSMC_SCL 5HSMC_JTAG_TMS 22HSMC_JTAG_TDI 22HSMC_CLK_IN0 8

HSMC_PRSNTn 5,22

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

15 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

15 31Thursday, March 19, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

15 31Thursday, March 19, 2015

R4549.9

C68

10uF

D2GREEN_LED

C67

10uF

BANK 1

BANK 2

BANK 3

J2

HSMC

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

3.3V45

4747

4949

3.3V51

5353

5555

3.3V57

5959

6161

3.3V63

6565

6767

3.3V69

7171

7373

3.3V75

7777

7979

3.3V81

8383

8585

3.3V87

8989

9191

3.3V93

9595

9797

3.3V99

101101

103103

3.3V105

107107

109109

3.3V111

113113

115115

3.3V117

119119

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

12V46

4848

5050

12V52

5454

5656

12V58

6060

6262

12V64

6666

6868

12V70

7272

7474

12V76

7878

8080

12V82

8484

8686

12V88

9090

9292

12V94

9696

9898

12V100

102102

104104

12V106

108108

110110

12V112

114114

116116

12V118

120120

GN

D_1

_116

1

GN

D_1

_216

2

GN

D_1

_316

3

GN

D_1

_416

4

GN

D_2

_116

5

GN

D_2

_216

6

GN

D_2

_316

7

GN

D_3

_116

9G

ND

_2_4

168

GN

D_3

_217

0

GN

D_3

_317

1

GN

D_3

_417

2

121121

3.3V123

125125

127127

3.3V129

131131

133133

3.3V135

137137

139139

3.3V141

143143

145145

3.3V147

149149

151151

3.3V153

155155

157157

3.3V159

122122

12V124

126126

128128

12V130

132132

134134

12V136

138138

140140

12V142

144144

146146

12V148

150150

152152

12V154

156156

158158

PSNTn160

Page 16: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO, PMOD

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

3.3V 3.3V

3.3V 3.3V

ADC1_CH6

ADC1_CH0ADC1_CH1ADC1_CH2ADC1_CH3

ADC1_CH4ADC1_CH5ADC1_CH6ADC1_CH7

IP_SECURITY

ADC2_CH0ADC2_CH1ADC2_CH2ADC2_CH3

ADC2_CH4ADC2_CH5ADC2_CH6ADC2_CH7

PMODA_IO0PMODA_IO1PMODA_IO2PMODA_IO3

PMODA_IO4PMODA_IO5PMODA_IO6PMODA_IO7

PMODA_D0PMODA_D1PMODA_D2PMODA_D3

PMODB_IO0PMODB_IO1PMODB_IO2PMODB_IO3

PMODB_IO4PMODB_IO5PMODB_IO6PMODB_IO7

PMODB_D4PMODB_D5PMODB_D6PMODB_D7

PMODA_D4PMODA_D5PMODA_D6PMODA_D7

PMODB_D0PMODB_D1PMODB_D2PMODB_D3

3.3V

2.5V_VCCADC

3.3V 3.3V

3.3V 3.3V

ADC1_CH[7:0] 11

PMODA_IO[7:0] 7

PMODB_IO[7:0] 7

IP_SECURITY 8

ADC2_CH[7:0] 11

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

16 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

16 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

16 31Wednesday, March 18, 2015

R282 200

R220 200

J5

2x6 PMOD Connector

11

77

22

88

33

99

44

1010

55

1111

66

1212

R290 200

R218 200

R288 200

R216 200

U37

824013

IO11

IO23

IO34

IO46

VDD5

GND2

XJ1

881545-2

R286 200R284 200

R319DNI

R223 200

R219 200

J7

CON2

12

R289 200

R217 200

R287 200

R211 200

POT1 5001 3

2

U39

824013

IO11

IO23

IO34

IO46

VDD5

GND2

R285 200

R283 200

U40

824013

IO11

IO23

IO34

IO46

VDD5

GND2

U34

DNI

GND1

IO2

NC33

NC44

NC55

NC66

U38

824013

IO11

IO23

IO34

IO46

VDD5

GND2

J20

2x10 Header

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

J4

2x6 PMOD Connector

11

77

22

88

33

99

44

1010

55

1111

66

1212

C69 4.7uF

Page 17: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI

Notes:Place a 0.1uF capacitor close to each DVDD pin.

Notes:Place a 0.1uF capacitor close to each AVDD pin.

Notes:Place this 0.1uF capacitor close to the DVDD_3V pin.

Notes:Place a 0.1uF capacitor close to each PVDD and BGVDD pin.

HDMI TX

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

TMDS_DATA_P2TMDS_DATA_N2

TMDS_DATA_P1

TMDS_CLK_P

TMDS_DATA_N1

TMDS_CLK_N

HDMI_HPD

TMDS_DATA_P0TMDS_DATA_N0

DDCSCLDDCSDA

HDMI_TX_D0HDMI_TX_D1HDMI_TX_D2HDMI_TX_D3HDMI_TX_D4HDMI_TX_D5HDMI_TX_D6HDMI_TX_D7

HDMI_TX_D8HDMI_TX_D9HDMI_TX_D10HDMI_TX_D11HDMI_TX_D12HDMI_TX_D13HDMI_TX_D14HDMI_TX_D15

HDMI_TX_D16HDMI_TX_D17HDMI_TX_D18HDMI_TX_D19HDMI_TX_D20HDMI_TX_D21HDMI_TX_D22HDMI_TX_D23

HDMI_TX_CLKHDMI_TX_DEHDMI_TX_HSHDMI_TX_VSHDMI_R_EXT

TMDS_CLK_PTMDS_CLK_N

TMDS_DATA_N0TMDS_DATA_P0

HDMI_TX_INT

HDMI_SDA

TMDS_DATA_P1

TMDS_DATA_P2TMDS_DATA_N1

TMDS_DATA_N2

HDMI_SCLDDCSDADDCSCL

CEC_CLKCEC_IO

3.3V_DVDD

1.8V_DVDD

1.8V_PVDD

1.8V_AVDD

1.8V_AVDD

1.8V_DVDD

1.8V_AVDD

1.8V_PVDD

3.3V_DVDD

HDMI_SCL

HDMI_SDA

HDMI_TX_INT

3.3V_DVDD

DDCSCL

DDCSDA

HDMI_HPD

HDMI_HPD

5V

5V

1.8V

1.8V

1.8V

3.3V

5V 5VHDMI_TX_D[23:0] 7

HDMI_TX_CLK 8

HDMI_TX_HS 7

HDMI_TX_VS 7

HDMI_TX_DE 7

HDMI_SCL 7

HDMI_TX_INT 7

HDMI_SDA 7

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

17 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

17 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

17 31Wednesday, March 18, 2015

R55 DNIR54 2.0K

L2 10uH1 2

C81

0.1uF

C72

0.1uF

L5 10uH1 2

R159

0

R58 2.0K

L4 10uH1 2

C84

0.1uF

VDD GND IO6 IO5

IO3 IO4IO2IO1

D42

82401646

7

4

81 2 3

56

C83

10uF

C75

0.1uF

C71

10uF

C73

0.1uF

C77

0.1uF

R53 2.0K

C79

10uF

R48 10.0K

ADV7513BSWZ

U8

DVDD1

VSYNC2

SPDIF3

MCLK4

I2S05

I2S16

I2S27

I2S38

SCLK9

LRCLK10

DVDD11

PVDD12

BGVDD13

R_EXT14

AVDD15HPD

16

DDCSCL33DDCSDA34SCL35SDA36

D2337 D2238 D2139 D2040 D1941 D1842 D1743 D1644

D1545 D1446 D1347 D1248 D1149 D1050

DVDD51

D952

CLK53

D854

D755 D656 D557 D458 D359 D260 D161 D062

DE63

HSYNC64

TXC-17TXC+18

AVDD19

TX0-20TX0+21

PD22

TX1-23TX1+24

AVDD25

TX2-26TX2+27

INT28

DVDD_3V29

CEC30

DVDD31

CEC_CLK32

EPAD_GND65

C82

0.1uF

C80

0.1uF

L3 10uH1 2

R155

0

R57 2.0KC76

10uF

R51 887 1%

HDMI 19-Pin Connector

J8685119134923

TMDS_DATA_N23 TMDS_DATA_P21

TMDS_DATA_N16 TMDS_DATA_P14

TMDS_DATA_N09 TMDS_DATA_P07

5V_VCC18

SCL15

TMDS_CLK_P10

TMDS_DATA_SHLD22

RESERVED_NC14

MTG

2G

2

TMDS_DATA_SHLD15

TMDS_DATA_SHLD08

SDA16

MTG

1G

1

TMDS_DATA_SHLD_CLK11 TMDS_CLK_N12

CEC13

DDC_CEC_GND17

HOT_PLUG_DETECT19

MTG

3G

3

MTG

4G

4

C74

0.1uF

C78

0.1uF

R47 2.0K

R49 DNI

VDD GND IO6 IO5

IO3 IO4IO2IO1

D41

82401646

7

4

81 2 3

56

R46 2.0K

Page 18: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

10/100/1000 Ethernet A

Notes:MDI signals termination

RGMII Mode (default)

Notes: Place capacitors near Ethernet PHY A pins

RGMII Mode

MII Mode

Ethernet PHY A

RJ45

FPGA Interface

Notes: Overlap R75 and R76 pads

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

ENETA_CONF4

ENET_MDC

ENETA_LED_TX

ENETA_INTn

ENETA_MDI_P1

ENETA_MDI_P2ENETA_MDI_N2

ENETA_MDI_3

ENETA_RESETn

ENETA_MDI_P3

ENETA_MDI_1

ENETA_MDI_0

ENETA_MDI_2

ENETA_LED_LINK1000

ENETA_MDI_N3

ENETA_MDI_N0

ENETA_RSET

ENET_MDIO

ENETA_MDI_P0

ENETA_TRST_N

ENETA_MDI_P1ENETA_MDI_N1ENETA_MDI_P2ENETA_MDI_N2ENETA_MDI_P3ENETA_MDI_N3

ENETA_MDI_N0ENETA_MDI_P0

ENETA_LED_RX

ENETA_HSDAC_PENETA_HSDAC_N

ENETA_GTX_CLKENETA_TX_CLKENETA_TX_ENENETA_TX_ER

ENETA_TX_D0ENETA_TX_D1ENETA_TX_D2ENETA_TX_D3

ENETA_RX_D0ENETA_RX_D1ENETA_RX_D2ENETA_RX_D3

ENETA_RX_CLKENETA_RX_DVENETA_RX_ER

ENETA_RX_CRSENETA_RX_COL

ENETA_LED_DUPLEX

ENETA_LED_TX

ENETA_LED_DUPLEXENETA_CONF4

CLK_25_ENET

ENETA_MDI_N12.5V

2.5V

ENETA_LED_RX

ENETA_LED_LINK1000

ENETA_LED_TX

ENETA_LED_LINK100

ENETA_LED_LINK100

1.2V2.5V

2.5V

2.5V

2.5V

1.2V

2.5V

2.5V

ENETA_RESETn 5

ENETA_INTn 5

ENET_MDC 5,19

ENET_MDIO 5,19ENETA_TX_D[3:0] 4

ENETA_GTX_CLK 8

ENETA_TX_EN 4ENETA_TX_ER 4

ENETA_TX_CLK 8

ENETA_RX_D[3:0] 4

ENETA_RX_CLK 8ENETA_RX_DV 4ENETA_RX_ER 4ENETA_RX_CRS 4ENETA_RX_COL 4

CLK_25_ENET 10,19

ENETA_LED_LINK100 5

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

18 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

18 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

18 31Wednesday, March 18, 2015

R301 DNI

R63 49.9C85 0.01uF

R60 4.7k

C92

0.1uF

C101

0.1uF

R65 49.9

R62 4.7k

R206 49.9

C87 0.01uF

GMII/MII/TBI INTERFACE

TEST

SGMII INTERFACE

JTAGMDI INTERFACE

MGMT

U9A

Ethernet PHY, 88E1111

COMA27

RESET_N28

CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065

125CLK22

XTAL155

XTAL254

VSSC53

RSET30

SEL_FREQ56

MDI3_P42

MDI3_N43

MDI2_P39

MDI2_N41

MDI1_P33

MDI1_N34

MDI0_P29

MDI0_N31

MDIO24

MDC25

INT_N23

HSDAC_P37

HSDAC_N38

GTX_CLK8

TX_CLK4

TX_EN9

RXCLK2

RX_DV94

CRS84

COL83

S_CLK_P79

S_CLK_N80

S_IN_P82

S_IN_N81

S_OUT_P77

S_OUT_N75

LED_TX68

LED_RX69

LED_DUPLEX70

LED_LINK100073

LED_LINK10074

LED_LINK1076

RXD095

RXD192

RXD293

RXD391

RXD490

RXD589

RXD687

RXD786

RX_ER3

TXD011

TXD112

TXD214

TXD316

TXD417

TXD518

TXD619

TXD720

TX_ER7

TMS46 TDO50 TDI44 TCK49 TRST_N47

R66 49.9

V27

C90

0.1uF

R76 DNI

R67 49.9

R64 49.9

R61 4.7k

C95

0.1uF

V28

R724.7k

R69 49.9

C93

0.1uF

C99

0.1uF

C100

0.1uF

C97

0.1uF

R68 49.9

R205DNI

Yellow

Green

RJ1A

7499151120

TD0_PA2

TD0_NA3

TD1_PA4

TD1_NA7

TD2_PA5

TD2_NA6

TD3_PA8

TD3_NA9

GN

D_T

AB

A15

GN

D_T

AB

A16

GNDA10

VCCA1

LED_G+A11

LED_G-A12

LED_Y+A14

LED_Y-A13

R75 0

C86 0.01uF

C91

0.1uF

R207 49.9

U9B

Ethernet PHY, 88E1111

NC113

VSS97

DVDD1

DVDD6

DVDD10

DVDD15

DVDD57

DVDD62

DVDD67

DVDD71

DVDD85

AVDD32

AVDD36

AVDD35

AVDD40

AVDD45

AVDD78

VD

DO

X26

VD

DO

X48

VD

DO

5

VD

DO

21

VD

DO

88

VD

DO

96

VD

DO

H72

VD

DO

H66

VD

DO

H52

NC251

C88 0.01uF

C89

0.1uF

C98

0.1uF

C96

0.1uF

R70 49.9

R59 4.7k

R71

4.99K1%

C94

0.1uF

Page 19: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

10/100/1000 Ethernet B

RGMII Mode (default)

Notes:MDI signals termination

RGMII Mode

MII Mode

Notes: Place capacitors near Ethernet PHY B pins

FPGA Interface

Notes: Overlap R96 and R97 pads

Ethernet PHY B

RJ45

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

ENETB_GTX_CLK

ENETB_RX_D0ENETB_RX_D1ENETB_RX_D2ENETB_RX_D3

ENETB_RX_CLKENETB_RX_DVENETB_RX_ER

ENETB_RX_CRSENETB_RX_COL

ENETB_LED_TX

ENETB_CONF4

ENET_MDC

ENETB_LED_TX

ENETB_INTn

ENETB_MDI_P1

ENETB_MDI_P2ENETB_MDI_N2

ENETB_MDI_3

ENETB_RESETn

ENETB_LED_DUPLEX

ENETB_MDI_P3

ENETB_MDI_1

ENETB_MDI_0

ENETB_MDI_2

ENETB_LED_LINK1000

ENETB_MDI_N3

ENETB_MDI_N0

ENETB_RSET

ENET_MDIO

ENETB_MDI_P0

ENETB_TRST_N

ENETB_LED_TX

ENETB_LED_DUPLEX

ENETB_MDI_P1ENETB_MDI_N1ENETB_MDI_P2ENETB_MDI_N2ENETB_MDI_P3ENETB_MDI_N3

ENETB_MDI_N0ENETB_MDI_P0

ENETB_LED_RX

ENETB_CONF4

ENETB_HSDAC_PENETB_HSDAC_N

ENETB_TX_CLKENETB_TX_ENENETB_TX_ER

ENETB_TX_D0ENETB_TX_D1ENETB_TX_D2ENETB_TX_D3

CLK_25_ENET

ENETB_MDI_N12.5V

2.5V

ENETB_LED_RX

ENETB_LED_LINK1000

ENETB_LED_TX

ENETB_LED_LINK100

ENETB_LED_LINK100

2.5V

1.2V2.5V

2.5V

2.5V

2.5V

1.2V

2.5V

ENETB_RESETn 5

ENETB_INTn 5ENETB_TX_D[3:0] 4

ENETB_GTX_CLK 8

ENETB_TX_EN 4ENETB_TX_ER 4

ENETB_TX_CLK 8

ENETB_RX_D[3:0] 4

ENETB_RX_CLK 8ENETB_RX_DV 4ENETB_RX_ER 4ENETB_RX_CRS 4ENETB_RX_COL 4

CLK_25_ENET 10,18

ENET_MDC 5,18

ENET_MDIO 5,18

ENETB_LED_LINK100 5

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

19 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

19 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

19 31Wednesday, March 18, 2015

C110

0.1uF

R89 49.9

C108

0.1uF

R87 49.9

R934.7k

C116

0.1uF

C106

0.1uF

R86 49.9

C105 0.01uF

R302 DNI

C103 0.01uF

R96 0

V30

C102 0.01uF

R91 49.9

R92

4.99K1%

R84 49.9

C111

0.1uF

C118

0.1uF

R83 4.7k

C109

0.1uF

GMII/MII/TBI INTERFACE

TEST

SGMII INTERFACE

JTAGMDI INTERFACE

MGMT

U10A

Ethernet PHY, 88E1111

COMA27

RESET_N28

CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065

125CLK22

XTAL155

XTAL254

VSSC53

RSET30

SEL_FREQ56

MDI3_P42

MDI3_N43

MDI2_P39

MDI2_N41

MDI1_P33

MDI1_N34

MDI0_P29

MDI0_N31

MDIO24

MDC25

INT_N23

HSDAC_P37

HSDAC_N38

GTX_CLK8

TX_CLK4

TX_EN9

RXCLK2

RX_DV94

CRS84

COL83

S_CLK_P79

S_CLK_N80

S_IN_P82

S_IN_N81

S_OUT_P77

S_OUT_N75

LED_TX68

LED_RX69

LED_DUPLEX70

LED_LINK100073

LED_LINK10074

LED_LINK1076

RXD095

RXD192

RXD293

RXD391

RXD490

RXD589

RXD687

RXD786

RX_ER3

TXD011

TXD112

TXD214

TXD316

TXD417

TXD518

TXD619

TXD720

TX_ER7

TMS46 TDO50 TDI44 TCK49 TRST_N47

C104 0.01uF

U10B

Ethernet PHY, 88E1111

NC113

VSS97

DVDD1

DVDD6

DVDD10

DVDD15

DVDD57

DVDD62

DVDD67

DVDD71

DVDD85

AVDD32

AVDD36

AVDD35

AVDD40

AVDD45

AVDD78

VD

DO

X26

VD

DO

X48

VD

DO

5

VD

DO

21

VD

DO

88

VD

DO

96

VD

DO

H72

VD

DO

H66

VD

DO

H52

NC251

C117

0.1uF

R209 49.9

C107

0.1uF

R88 49.9

R82 4.7k

Yellow

Green

RJ1B

7499151120

TD0_PB2

TD0_NB3

TD1_PB4

TD1_NB7

TD2_PB5

TD2_NB6

TD3_PB8

TD3_NB9

GN

D_T

AB

B15

GN

D_T

AB

B16

GNDB10

VCCB1

LED_G+B11

LED_G-B12

LED_Y+B14

LED_Y-B13

C115

0.1uF

R97 DNI

R90 49.9

R204DNI

R208 49.9

C113

0.1uF

R85 49.9

C114

0.1uF

C112

0.1uF

V29

Page 20: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB to UARTFPGA Interface

2.5V default 3.3V optional

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

UART_RXUART_TX

FT232_DP

UART_TXLEDUART_RXLED

UART_PWEN

VCCIO_UART

FT232_DM

UART_VCC

UART_5V

VCCIO_UART

UART_RESETn2.5V

UART_WAKEUPUART_5V

2.5V 3.3V_UART 5V

UART_TX 5

UART_RESETn 21

UART_RX 5

UART_WAKEUP 21

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

20 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

20 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

20 31Wednesday, March 18, 2015

C123

0.1uF

D13 GREEN_LED

C1254.7nFD14 GREEN_LED

U12

TPD2EUSB30D-

2D+1

GND3

U11

FT232R

VCCIO1

RXD2

RI#3

GN

D1

4

NC35DSR#

6

DCD#7

CTS#8

CBUS49

CBUS210

USBDP14

NC513NC412

CBUS311

GN

D2

17

USBDM15

3V3OUT16

RESET18

VCC19

CBUS022

NC223

AG

ND

24

CBUS121

GN

D3

20

NC125

OSCO28

NC629

TXD30

DTR#31

RTS#32

OSCI27

TEST26

EP

AD

_GN

D33

C119

0.1uF

R105 4.7K

R103 0

R107 DNI

R110 270

R222 10.0K

VBUSD-

D+ID

J11USB MINI-B

12345

6 7 8 9

C212

0.1uF

R1081M

R221

20.0K

C124

4.7uF

R101 0 R102 DNI

R109 270

C120

4.7uF

C121

0.1uF

C122

4.7uF

R111 10K

Page 21: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

On-Board USB Blaster II-1 MAX10 USB INTERFACE

PLACE NEAR CY7C68013A

IFCLK = 48MHz

From PLL

MISC

MAXII LED

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

FX2_PA0

USB_MAX_TDOUSB_MAX_TMS

USB_MAX_TCK

USB_MAX_TDI

FX2_WAKEUPVBUS_5V

FX2_D_NFX2_D_P

VBUS_5V

FX2_PD4FX2_PD3

FX2_PD0FX2_PD1FX2_PD2

FX2_PD5FX2_PD6FX2_PD7

FX2_PB5FX2_PB6FX2_PB7

24M_XTALIN24M_XTALOUT

FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4

FX2_PA5FX2_PA6FX2_PA7

FX2_PA1FX2_PA2FX2_PA3FX2_PA4

USB_CLK

FX2_RESETn

FX2_SDA MAX_SDA

FX2_FLAGCFX2_FLAGB

FX2_WAKEUP

FX2_SLWRnFX2_SLRDn

FX2_FLAGA

FX2_SCLFX2_SDA

FX2_RESETn

FX2_PD2FX2_PD0USB_MAX_TCK

USB_MAX_TDIFX2_PD3USB_MAX_TDOFX2_PD1USB_MAX_TMS

FX2_PA2

USB_CLK

FX2_PA1FX2_PB1

FX2_PA4

FX2_PB2

FX2_PA6FX2_PB5

FX2_SLWRn

FX2_PD5

FX2_PA5

FX2_SCL

FX2_PD6

FX2_PD4

FX2_PB7

FX2_PB4

FX2_FLAGC

FX2_PA3

FX2_FLAGB

FX2_SLRDn

FX2_PD7

FX2_PB3

FX2_PB0

FX2_PB6

FX2_FLAGA

FX2_RESETn

FX2_PA7

FX2_PA0

CLK_50_MAXII

QSPI_RESETn

UART_RESETn

MAX_SDA

MAX10_CONF_DONE

MAXII_CONF_DONE

1.2V_POK

3.3V_POK2.5V_POK

3.3V_LED2.5V_LED1.2V_LED

MAX10_NSTATUSUART_WAKEUP

LED_GREENLED_RED

LED_BLUE

3.3V3.3V

3.3V3.3V

3.3V

3.3V

USB_CLK 8

CLK_50_MAXII 10

QSPI_RESETn 14UART_RESETn 20

MAX10_CONF_DONE 9MAXII_CONF_DONE 23

3.3V_POK 252.5V_POK 251.2V_POK 27

3.3V_LED 232.5V_LED 231.2V_LED 23

MAX10_NSTATUS 9UART_WAKEUP 20

LED_RED 23LED_GREEN 23LED_BLUE 23

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

21 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

21 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

21 31Wednesday, March 18, 2015

R122 10.0K

C128

12pF

C131

0.1uF

R112 0

U14

MAX811

GND1

RESET2

VCC4

MR3

R1141M

C129

12pFR121 0

C136

0.1uF

J13

DNI

11

33

55

77

22

44

66

88

99

1010

R119 0

C132

0.1uF

R125 1.00K

U16

CY7C68013A_QFN

RDY01

RDY12

XTALIN5

AVCC3

DMINUS9

AGND6

VCC11

GND12

PD752

CLKOUT54

XTALOUT4

AVCC7

DPLUS8

AGND10

IFCLK13

RESERVED14

PD550PD449

PD651

SCL15

SDA16

PB018

GND26

GND28

GND41

PB119

PB321PB220

VCC17

VCC27

PB624PB523PB422

PD348PD247

PA740

PA437

PA134

PB725

PD146

WAKEUP44

PA639

GND53

VCC43

PA336

CTL130CTL029

PD045

RESET42

PA538

GND56

VCC55

PA235

PA033

CTL231

VCC32

EXPOSED_PAD57

R115100K

C126 0.1uFVBUSD-D+ID

J12USB MINI-B

12345

6789

R118 0

C137

0.1uF

R116 2.0K

R120 0

C133

0.1uF

U15

TPD2EUSB30D-

2D+1

GND3

R113 DNI

C1274.7nF

R124 1.00K

Y2

24.00MHz

1 3

24

MAX IIBANK1

U13A

EPM1270_M256FBGA

IOB1_21G4

IOB1_22H1

IOB1_23H2

IOB1/GCLK0K1

IOB1/GCLK1L1

IOB1_1B1

IOB1_2C1

IOB1_3C2

IOB1_4C3

IOB1_5C4

IOB1_6D1

IOB1_7D2

IOB1_8D3

IOB1_9D4

IOB1_10E1

IOB1_11E2

IOB1_12E3

IOB1_13E4

IOB1_14F1

IOB1_15F2

IOB1_16F3

IOB1_17F4

IOB1_18G1

IOB1_19G2

IOB1_20G3

IOB1_24H4

IOB1_25J1

IOB1_26J2

IOB1_27K2

IOB1_28L2

IOB1_29M1

IOB1_30M2

IOB1_31N1

IOB1_32N2

IOB1_33N4

IOB1_34P1

IOB1_35P2

IOB1_36P3

IOB1_37P4

IOB1_38R1

IOB1_39R2

IOB1_40R3

IOB1_41R4

IOB1_42T1

IOB1_43T2

IOB1_44T4

IOB1_45U1

IOB1_46U3

IOB1_47V1

TMST3TDOV2TDIU2TCKW2

IOB1_48V3

IOB1_49W1

C138

0.1uF

C134

0.1uF

C130

0.1uF

MAX IIBANK4

U13D

EPM1270_M256FBGA

IOB4/DEV_CLRnY13

IOB4/DEV_OEW12

IOB4_1U13

IOB4_2U14

IOB4_3U15

IOB4_4U16

IOB4_5U4

IOB4_6U5

IOB4_7U6

IOB4_8U7

IOB4_9U8

IOB4_10V14

IOB4_11V15

IOB4_12V16

IOB4_13V17

IOB4_14V18

IOB4_15V4

IOB4_16V5

IOB4_17V6

IOB4_18V7

IOB4_20W11

IOB4_21W13

IOB4_22W14

IOB4_23W15

IOB4_24W16

IOB4_25W17

IOB4_26W18

IOB4_27W3

IOB4_28W4

IOB4_29W5

IOB4_30W6

IOB4_32W8

IOB4_33W9

IOB4_34Y1

IOB4_35Y10

IOB4_36Y11

IOB4_37Y12

IOB4_38Y14

IOB4_39Y15

IOB4_40Y16

IOB4_41Y17

IOB4_42Y18

IOB4_43Y19

IOB4_44Y2

IOB4_45Y3

IOB4_46Y4

IOB4_47Y5

IOB4_48Y6

IOB4_49Y7

IOB4_50Y8

IOB4_51Y9

IOB4_31W7

IOB4_19W10R123

20.0K

R117 2.0K

C135

0.1uF

Page 22: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 USB INTERFACE

JTAG INTERFACE

On-Board USB Blaster II-2

Notes:Place capacitors near MAX II device.

USB Blaster Programming Header(uses JTAG mode only)

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

JTAG_HEADER_TCK_RJTAG_HEADER_TDO_R

JTAG_HEADER_TCK

USB_DISABLEn

JTAG_HEADER_TMS

JTAG_HEADER_TDI

USB_FULL

USB_ADDR1

USB_ADDR0

HSMC_JTAG_TDOHSMC_JTAG_TDI

HSMC_JTAG_TMSHSMC_JTAG_TCK

USB_RDn

USB_WRnUSB_OEn

USB_RESETn

USB_DATA0USB_DATA2

USB_DATA1

USB_DATA7

USB_DATA4

USB_DATA5

USB_SDA

USB_SCL

USB_EMPTY

USB_SCLUSB_SDAUSB_FULLUSB_EMPTY

USB_DISABLEn

VTAP_BYPASSnHSMC_BYPASSn

USB_DATA3

MAX10_JTAG_TDI

JTAG_HEADER_TDO

MAX10_JTAG_TMSMAX10_JTAG_TDO

MAX10_JTAG_TCK

SI5338A_INTR

SI570_EN

MAX10_JTAG_EN

HSMC_PRSNTn

HSMC_JTAG_MASTERn

HSMC_JTAG_MASTERnI2C_MAXII_SCLI2C_MAXII_SDA

JTAG_LOCK_R

JTAG_LOCKJTAG_SAFEJTAG_HEADER_TCK

USB_DATA6

JTAG_HEADER_TCKJTAG_HEADER_TDOJTAG_HEADER_TMSJTAG_LOCKJTAG_HEADER_TDI

JTAG_HEADER_TMS_R

JTAG_HEADER_TDI_R

3.3V 3.3V

3.3V

3.3V

3.3V 2.5V2.5V

2.5V

2.5V

3.3V

3.3V

3.3V 3.3V 3.3V

2.5V

2.5V

USB_DATA[7:0] 7

USB_FULL 7USB_EMPTY 7

USB_SDA 7

USB_RESETn 7USB_OEn 7USB_RDn 7USB_WRn 7

USB_ADDR[1:0] 7

USB_SCL 7

MAX10_JTAG_TMS 9

MAX10_JTAG_TDI 9

MAX10_JTAG_TCK 9

MAX10_JTAG_TDO 9

HSMC_JTAG_TDI 15

HSMC_JTAG_TMS 15HSMC_JTAG_TDO 15

HSMC_JTAG_TCK 15

HSMC_PRSNTn 5,15

VTAP_BYPASSn 23HSMC_BYPASSn 23

SI5338A_INTR 10SI570_EN 10

MAX10_JTAG_EN 9

I2C_MAXII_SDA 10,28

I2C_MAXII_SCL 10,28

JTAG_SAFE 7

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

22 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

22 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

22 31Wednesday, March 18, 2015

C141

0.1uF

C145

0.1uF

R135 1.00k

R266 22.0

R243 10.0K

R1401.00k

MAX IIPower

U13E

EPM1270_M256FBGA

GNDINTJ4

GNDINTU12

GNDINTM17

GNDINTD12

GNDIOH3

GNDIOJ3

GNDIOM4

GNDION3

GNDIOU9

GNDIOV8

GNDIOV9

GNDIOV13

GNDIOH18

GNDIOJ17

GNDION18

GNDIOC8

GNDIOD9

GNDIOC12

GNDIOC13

GNDIOM18

VCCINTD11VCCINTL17VCCINTU11VCCINTK4

VCCIO1K3

VCCIO1L3

VCCIO1L4

VCCIO1M3

VCCIO2C9

VCCIO2C10

VCCIO2D10

VCCIO2C11

VCCIO3J18

VCCIO3K17

VCCIO3K18

VCCIO3L18

VCCIO4U10

VCCIO4V10

VCCIO4V11

VCCIO4V12

R136 DNI

J14

2X5_100mil

11

33

55

77

22

44

66

88

99

1010 R276 22.0

C144

0.1uF

R248 22.0

R126 10.0K

R133 1.00k

R56 DNI

C148

0.1uF

MAX IIBANK3

U13C

EPM1270_M256FBGA

IOB3/GCLK3L20

IOB3_24J19

IOB3_1B20

IOB3_2C18

IOB3_3C19

IOB3_4C20

IOB3_5D17

IOB3_6D18

IOB3_7D19

IOB3_8D20

IOB3_9E17

IOB3_10E18

IOB3_11E19

IOB3_12E20

IOB3_13F17

IOB3_14F18

IOB3_15F19

IOB3_16F20

IOB3_17G17

IOB3_18G18

IOB3_19G19

IOB3_20G20

IOB3_21H17

IOB3_23H20

IOB3/GCLK2M20

IOB3_25J20

IOB3_26K19

IOB3_27K20

IOB3_28L19

IOB3_29M19

IOB3_30N17

IOB3_31N19

IOB3_32N20

IOB3_33P17

IOB3_35P19

IOB3_36P20

IOB3_37R17

IOB3_38R18

IOB3_39R19

IOB3_40R20

IOB3_41T17

IOB3_42T18

IOB3_43T19

IOB3_44T20

IOB3_45U17

IOB3_46U18

IOB3_47U19

IOB3_48U20

IOB3_49V19

IOB3_50V20

IOB3_51W19

IOB3_52W20

IOB3_53Y20

IOB3_22H19

IOB3_34P18

C149

0.1uF

R130 10.0K

R127 10.0K

R134 1.00k

R138 1.00k

C143

0.1uF

C147

0.1uF

C139 DNI

C140

0.1uF

R131 1.00k

R1391.00k

R267 22.0

C142

0.1uF

MAX IIBANK2

U13B

EPM1270_M256FBGA

IOB2_1A1

IOB2_2A10

IOB2_3A11

IOB2_4A12

IOB2_5A13

IOB2_6A14

IOB2_7A15

IOB2_8A16

IOB2_9A17

IOB2_10A18

IOB2_11A19

IOB2_12A2

IOB2_13A20

IOB2_14A3

IOB2_15A4

IOB2_16A5

IOB2_17A6

IOB2_18A7

IOB2_20A9

IOB2_21B10

IOB2_22B11

IOB2_23B12

IOB2_24B13

IOB2_25B14

IOB2_26B15

IOB2_27B16

IOB2_28B17

IOB2_29B18

IOB2_30B19

IOB2_31B2

IOB2_32B3

IOB2_33B4

IOB2_34B5

IOB2_36B7

IOB2_37B8

IOB2_38B9

IOB2_39C14

IOB2_40C15

IOB2_41C16

IOB2_42C17

IOB2_43C5

IOB2_44C6

IOB2_45C7

IOB2_46D13

IOB2_47D14

IOB2_48D15

IOB2_49D16

IOB2_50D5

IOB2_51D6

IOB2_52D7

IOB2_53D8

IOB2_19A8

IOB2_35B6

R1371.00k

C146

0.1uF

R247 22.0

R129 10.0K

R128 1.00k

R132 1.00k

Page 23: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LED, User IO, Connector

ON = 0OFF = 1

USER DIPSWITCH

ON = 0OFF = 1

BOARD SETTINGS DIPSWITCH

Push Buttons

LED

Logic 0 = Device JTAG BypassLogic 1 = Device JTAG Enable

POWER LED

LED

Swtiches

Buttons

Vth

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

USER_DIPSW1USER_DIPSW0

USER_DIPSW2USER_DIPSW3

CONFIG_SELVTAP_BYPASSn

USER_DIPSW4

HSMC_BYPASSn

USER_PB1

USER_PB2

USER_PB0

USER_PB3

USER_LED1

USER_LED2

USER_LED3

RESn_LED0USER_LED0

RESn_LED1

RESn_LED2

RESn_LED3

USER_LED4 RESn_LED4

PULSE_NCONFIG

CPU_RESETn

CONF_DONE_LEDMAXII_CONF_DONE

3.3V_LED

2.5V_LED

1.2V_LED

RESn_3.3V_LED

RESn_1.2V_LED

RESn_2.5V_LED

LED_GREEN

LED_BLUE

LED_RED

1.5V

3.3V

1.5V

2.5V

3.3V

12V

3.3V

5V

USER_DIPSW[4:0] 6

USER_LED[4:0] 6

USER_PB[3:0] 6

CONFIG_SEL 9VTAP_BYPASSn 22HSMC_BYPASSn 22

MAXII_CONF_DONE 21

PULSE_NCONFIG 9

CPU_RESETn 9

1.2V_LED 212.5V_LED 213.3V_LED 21

LED_RED 21LED_GREEN 21LED_BLUE 21

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

23 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

23 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

23 31Wednesday, March 18, 2015

R151 49.9

R157 10K

S1

PB Switch

1 32 4

R149 49.9

D23 GREEN_LED R146 10K

S4

PB Switch

1 32 4

D1BLUE LED

R153 49.9

R144 49.9

R1001K

R160 10K

D19 GREEN_LED

S5

PB Switch

1 32 4

R238 150

Q2

NDS7002A

R141 49.9

R150 10K

R154 10K

R992.0K

D22 GREEN_LED

OPEN

SW2

DIPSWITCH4

1234 5

678

D17 GREEN_LED

R145 10K

R142 10K

R148 10K

R1041K

D21 GREEN_LED

R G B

LED1

RGB_LED_HSMF_C118

34

2

1

R156 10K

R4410K

R162 10KS6

PB Switch

1 32 4

D18 GREEN_LED

Q3

NDS7002A

D20 GREEN_LED

R106

1K

R237 150

OPEN

SW1

DIPSWITCH4

1234 5

678

S2

PB Switch

1 32 4

R147 10K

D15 GREEN_LED

Q1

NDS7002A

R161 150

R158 10K

D16 GREEN_LED

R239 150

S3

PB Switch

1 32 4

R143 10K

R152 10K

Page 24: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V / 4A

Power - 12V_DCIN / 5V

12VDC Input

Hot Swap Controller Circuit

Set frequency to 1.48MHz

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

5V_AVIN

5V_S

S

5V_F

QA

DJ

5V_R

CLX

5V_VFB

5V_POK

5V_AVIN

12V_UV

12V

_PG

12V_IMON

12V

_FB

12V_UV12V_OV

12V

_N

12V_P

12V

_GA

TE

12V

12V_DCIN

5V

12V12V_DCIN

5V_POK 25,27

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

24 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

24 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

24 31Tuesday, March 24, 2015

C154

56pF

R294

150K

R174DNI

U17

EN2342

NC11

NC22

NC33

NC44

NC55

NC66

NC77

NC88

NC99

NC1010

NC1111

NC1212

NC1313

NC1414

NC1515

VOUT16VOUT17VOUT18VOUT19VOUT20VOUT21VOUT22VOUT23VOUT24

NC2525

NC2626

NC(SW)2727

NC(SW)2828

PGND29PGND30PGND31PGND32PGND33PGND34

S_OUT48

S_IN47

BG

ND

46

VD

DB

45

BTM

P44

PG

43

AVINO42

PVIN41 PVIN40 PVIN39 PVIN38 PVIN37 PVIN36 PVIN35

NC6868 NC6767 NC6666 NC6565 NC6464

NC(SW)6363

NC(SW)6262

NC(SW)6161

CGND60

NC5959

FQADJ58

RCLX57

SS56

EAIN55

VFB54

AGND53AGND52

AVIN51

ENABLE50

POK49

PGND69

J15

DC Input Jack 2.0 mm

123

R16510.0K

C165

0.047uF

R296

20.0K

C15322uF

C157

DNI

R297 1K

R163 DNI

R164 560

C150 DNI

R179

0

R17613.3K

SW3

POWER SW

32

1

45

6

C159

1uF

C156

47uf

R17010.0K

R291

20.0K

R293

10

C164

0.01uF

U3

LTC4218CGN

NC1

VDD2

UV3

OV4

TIMER5

INTVCC6

GND7

SOURCE8

GATE9PG10/FLT11FB12IMON13ISET14SENSE-15SENSE+16

R177

30K

C151

0.22uF

R299

1K

C158

150uF

C152 22nF

V39

RS

NS

1S

NS

2

C161

22uF

R181140K

R245

20.0K

R298 0.003

R295

20.0K

R178

68.1KR246

226K

R1664.75K

R300

1K

R16910.0K

C160

1uF

R16875K

V40

RS

NS

1S

NS

2

V34

C155

47uf

C163

0.1uF

R292

10.0K

R1714.02K

U18FDMC8878

5

123

4

C162

0.1uF

Page 25: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - 3.3V / 2.5V

Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.

VFB=0.75VIFB=5nA

Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM

Resistor for LLM mode only. Open (DNI) for PWM mode.

SS -> 22nF * 80kOhm = 1.76msec +/-25%

MAX10 2.5V (2.5V / 3A)

Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.

VFB=0.75VIFB=5nA

Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM

Resistor for LLM mode only. Open (DNI) for PWM mode.

SS -> 22nF * 80kOhm = 1.76msec +/-25%

MAX10 3.3V (3.3V / 3A)

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

2.5V_LLM

2.5V_FB

2.5V_POK

2.5V_RLLM

2.5V_SS

5V_POK 2.5V_EN

1.8V_LLM

3.3V_VFB

3.3V_POK

1.8V_RLLM

1.8V_SS

5V_POK 3.3V_EN

3.3V

5V

5V

5V

5V

2.5V

5V

5V

5V

5V

3.3V3.3V

2.5V

2.5V_VCCIO

2.5V_VCCIO

5V_POK 24,27

3.3V_POK 21

2.5V_POK 21

2.5V_VCCIO_SENSE_P 28

2.5V_VCCIO_SENSE_N 28

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

25 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

25 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

25 31Tuesday, March 24, 2015

R186 10.0K

R190 0

C176 22nF

R189 DNI

R193200k

C17347UF

V35

RSNS1

SNS2

C177 22nF

C17247UF

U22

EN6337

NC

(SW

)11

NC

(SW

)22

NC

33

NC

44

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT10

VOUT11

NC

(SW

)12

12PGND

13

PGND14

PGND15

PGND16

PGND17

PGND18

PVIN19

NC

2525

NC

2424

NC

2323

NC

2222

PVIN21 PVIN20

NC

(SW

)38

38N

C(S

W)3

737

NC

(SW

)36

36N

C(S

W)3

535

NC

(SW

)34

34

AVIN33

AGND32

VFB31

SS30

RLLM29

POK28

ENA27

SYNC/LLM26

PGND39

R198 DNI

R201560

R19784.5K

R196 0

R191 0

C17147UF

C170

22uF R281 0.1

V36

RSNS1

SNS2

C16947UF

U23

EN6337

NC

(SW

)11

NC

(SW

)22

NC

33

NC

44

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT10

VOUT11

NC

(SW

)12

12

PGND13

PGND14

PGND15

PGND16

PGND17

PGND18

PVIN19

NC

2525

NC

2424

NC

2323

NC

2222

PVIN21 PVIN20

NC

(SW

)38

38N

C(S

W)3

737

NC

(SW

)36

36N

C(S

W)3

535

NC

(SW

)34

34

AVIN33

AGND32

VFB31

SS30

RLLM29

POK28

ENA27

SYNC/LLM26

PGND39

C17415pF

R194 0

R200560

R185 DNI

R184 10.0K

R19559.0K

R199 DNI

C17515pF

C168

22uF

R192200k

Page 26: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - 2.5V_VCC / 1.2V

MAX10 2.5V (2.5V_VCCA+2.5V_VCCADC / 600mA) MAX10 1.8V (1.8V / 600mA)

Notes:Place the 10uF capacitor close to ferrite bead.Place the 0.1uF capacitor close to MAX 10 pin.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

2.5V_CORE_EN 1.8V_EN2.5V_CORE_EN

3.3V2.5V_CORE_SENSE

3.3V 1.8V

2.5V_CORE

2.5V_CORE

2.5V_VCCA

2.5V_VCCADC

2.5V_CORE

2.5V_CORE

2.5V_CORE_SENSE

1.2V_POK 21,27

2.5V_CORE_SENSE_P 28

2.5V_CORE_SENSE_N 28

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

26 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

26 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

26 31Tuesday, March 24, 2015

U25

EP5358HUI

NC11

PGND2

PGND3

VFB4

VSENSE5

AGND6

VOUT7

VOUT8

VS29 VS1

10 VS011

ENABLE12

AVIN13

PVIN14

NC1515

NC1616

R278 10.0K

R213

0

C255

10uF

TP9

C215

10uF

C256

10uF

R188 0.1

C213

DNI

C217

10uF

C70

DNI

C214

2.2uF

V38

RSNS1

SNS2

R214

0

C218

2.2uF

C178

10uF

C179

0.1uF

U24

EP5358HUI

NC11

PGND2

PGND3

VFB4

VSENSE5

AGND6

VOUT7

VOUT8

VS29 VS1

10 VS011

ENABLE12

AVIN13

PVIN14

NC1515

NC1616

TP8

L6 7427920221 2

R279 10.0K

C181

0.1uF

L7 7427920221 2

V37

RSNS1

SNS2

C231

DNI

C180

10uF

Page 27: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - 1.5V / 1.2V

Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.

VFB=0.75VIFB=5nA

Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM

Resistor for LLM mode only. Open (DNI) for PWM mode.

SS -> 22nF * 80kOhm = 1.76msec +/-25%

MAX10 1.2V (1.2V / 3A)

Notes:Place the 10uF capacitor close to ferrite bead.Place the 0.1uF capacitor close to MAX 10 pin.

MAX10 1.5V (1.5V / 600mA)

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

1.5V_EN

1.2V_LLM

1.2V_FB

1.2V_POK

1.2V_RLLM

1.2V_SS

5V_POK 1.2V_EN

1.5V

3.3V

5V

1.2V_VCC

5V

5V

5V

1.2V

1.2V

1.2V_VCC

3.3V

1.2V_VCC 1.2V_VCC1.2V_VCCD 1.2V_VDDADC

1.5V_VCCIO

1.5V_VCCIO

1.5V

1.2V_VCC_SENSE_P 28

1.2V_VCC_SENSE_N 28

1.2V_POK 21

5V_POK 24,25

1.5V_VCCIO_SENSE_N 28

1.5V_VCCIO_SENSE_P 28

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

27 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

27 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

27 31Tuesday, March 24, 2015

C211

10uF

U27

EN6337

NC

(SW

)11

NC

(SW

)22

NC

33

NC

44

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT10

VOUT11

NC

(SW

)12

12

PGND13

PGND14

PGND15

PGND16

PGND17

PGND18

PVIN19

NC

2525

NC

2424

NC

2323

NC

2222

PVIN21 PVIN20

NC

(SW

)38

38N

C(S

W)3

737

NC

(SW

)36

36N

C(S

W)3

535

NC

(SW

)34

34

AVIN33

AGND32

VFB31

SS30

RLLM29

POK28

ENA27

SYNC/LLM26

PGND39

C197

0.1uF

R212 0.1R230 0

R228 0

L9 7427920221 2

C242

DNI

C202

10uF

L8 7427920221 2

R234560

C199

0.1uF

R226 DNI

C20515pF

V49

RSNS1

SNS2

R231332K

R227 10.0K

V43

RSNS1

SNS2

C166

DNI

C196

10uF

C201

2.2uFR232 DNI

V50

RSNS1

SNS2

R225 .009

R215

0

C20447UF

R224 10.0K

TP5

C20347UF

C200

22uF

U26

EP5358LUI

NC11

PGND2

PGND3

VFB4

VSENSE5

AGND6

VOUT7

VOUT8

VS29 VS1

10 VS011

ENABLE12

AVIN13

PVIN14

NC1515

NC1616

R229200k

V44

RSNS1

SNS2

C206 22nF

C198

10uF

Page 28: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - Power Monitor

ADDR = 98h

ADDR = 9Ah

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

I2C_MAXII_SDAI2C_MAXII_SCL

I2C_MAXII_SDAI2C_MAXII_SCL

3.3V

3.3V

2.5V

I2C_MAXII_SDA 10,22

I2C_MAXII_SCL 10,22

1.5V_VCCIO_SENSE_N 271.5V_VCCIO_SENSE_P 27

1.2V_VCC_SENSE_N 271.2V_VCC_SENSE_P 27

2.5V_VCCIO_SENSE_P 252.5V_VCCIO_SENSE_N 25

2.5V_CORE_SENSE_P 262.5V_CORE_SENSE_N 26

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

28 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

28 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

28 31Wednesday, March 18, 2015

C209

0.1uF

U30

LTC2990

V11

V22

V33

V44

GND5

SDA6 SCL7

ADR08 ADR19

VCC10

R235 4.7k

U29

LTC2990

V11

V22

V33

V44

GND5

SDA6 SCL7

ADR08 ADR19

VCC10

R236 4.7k

C210

0.1uF

Page 29: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Power

Notes:Place the capacitor close to MAX10 pin.

Notes:Place the capacitor close to MAX 10 pin.

Notes:Place the capacitors close to MAX 10 pin.

Notes:Place this filter close to VCCIO1A pins.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Vout = 2.5V - Vin

Vout = 2.5V - Vin

ANAIN1ANAIN2

ADC_VREF

ANAIN1_SMA

ANAIN2_SMA

1.2V_VCC

1.2V_VCCD

2.5V_VCCA

1.2V_VDDADC2.5V_VCCADC

2.5V_VCCIO

2.5V_VCCIO

2.5V_VCCIO

1.5V_VCCIO

1.5V_VCCIO

3.3V

3.3V

ADC_VREFREF_2.5V

ADC_VREF 2.5V_VCCADC

ADC_VREF 2.5V_VCCADC

2.5V_VCCIO

2.5V_VCCIO

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

29 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

29 31Tuesday, March 24, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

29 31Tuesday, March 24, 2015

R274 4.99K1%

C319

1pF

C318

1pF

R240 1

U36

AD8515

VIN+3

VIN-4 OUT

1

V-

2V

+5

R242 DNI

C315

10uF

R270

4.99K1%

R280 10

U35

AD8515

VIN+3

VIN-4 OUT

1

V-

2V

+5

C314

1uF

L12

BLM15AG221SN1300mA

R26910.0K

MAX 10 POWER

10M50DAF484

U1G

VCCN12

VCCN10

VCCM13

VCCM12

VCCM11

VCCL12

VCCL11

VCCL10

VCCK13

VCCK11

VCCD_PLL1T7

VCCD_PLL2G16

VCCD_PLL3G7

VCCD_PLL4U16

VCCA1R8

VCCA2H15

VCCA3H8

VCCA4T15

VCCINTJ7

VCCA_ADCH7

ADC_VREFH6

ANAIN1G5

ANAIN2J5

VCCIO1AL6

VCCIO1AK7

VCCIO1BM6

VCCIO1BL7

VCCIO2R6

VCCIO2P7

VCCIO2N7

VCCIO2N6

VCCIO3U9

VCCIO3U8

VCCIO3T9

VCCIO3T11

VCCIO3T10

VCCIO4U14

VCCIO4U12

VCCIO4U11

VCCIO4T13

VCCIO4T12

VCCIO5T17

VCCIO5R17

VCCIO5R16

VCCIO5P16

VCCIO5N16

VCCIO6N17

VCCIO6M17

VCCIO6L16

VCCIO6K17

VCCIO6K16

VCCIO6J17

VCCIO6H16

VCCIO7G14

VCCIO7G13

VCCIO7G12

VCCIO7F14

VCCIO7F12

VCCIO8G11

VCCIO8G10

VCCIO8F9

VCCIO8F11

J191

2345

R27310.0K

R271 4.99K1%

C184

0.1uF

R241 DNI

C207 30pF

R26810.0K

C208 30pF

C316

0.1uF

C183

0.1uF

R275

4.99K1%

R27210.0K

R277 10

J181

2345

Page 30: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Ground

Notes:1. Use REFGND as ground reference.2. Route analog input signal adjacent to AVSSREF as possible.

Notes:Place this FB close to MAX 10 ADC_VREF.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

REFGND

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

30 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

30 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

30 31Wednesday, March 18, 2015

MAX 10 GROUND

10M50DAF484

U1H

GNDY9

GNDY15

GNDY12

GNDW21

GNDV6

GNDV2

GNDV19

GNDU13

GNDU10

GNDT8

GNDT4

GNDT16

GNDT14

GNDR21

GNDR19

GNDP6

GNDP2

GNDP17

GNDN13

GNDN11

GNDM7

GNDM19

GNDM16

GNDM10

GNDL5

GNDL21

GNDL17

GNDL13

DNUL3

GNDK3

GNDK12

GNDK10

GNDJ6

GNDJ2

GNDJ19

GNDJ16

GNDG8

GNDG6

GNDG21

GNDG18

GNDG15

GNDF13

GNDF10

GNDE7

GNDE2

GNDD4

GNDD20

GNDD16

GNDD11

GNDB9

GNDB6

GNDB18

GNDB13

GNDAB22

GNDAB1

GNDAA4

GNDAA18

GNDA22

GNDA1

NC2F6NC1E5

REFGNDH5

TP7

L11 7427920221 2

Page 31: REV DATE PAGES Pre-Release Schematic A 20 May 2014 All · 2020-01-31 · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 1Gb DACx16 DDR3 1Gb x8 x4 x5 x85 USB to UART 10/100/1000RJ45 Ethernet

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Decoupling

Notes:Place capacitor near MAX 10 pins. Notes:

Place a 0.1uF capacitor close to each MAX 10 VCCA pin.

Notes:Place a 0.1uF capacitor close to each MAX 10 VCCD pin.

Notes:Place decoupling capacitors on power pins of DDR3 and MAX 10. Place 100UF capacitors on center of the power rail between DDR3 and MAX 10.

Notes:Place these capacitors close to MAX 10 VCCIO7 and VCCIO8 pins.

Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

2.5V_VCCIO

1.2V_VCC

3.3V

1.2V_VCCD

2.5V_VCCA

1.5V

1.5V_VCCIO

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

31 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

31 31Wednesday, March 18, 2015

Title

Size Document Number Rev

Date: Sheet of

150-0321401-C1 C1

MAX10 FPGA Development Kit (6XX-44292R)

B

31 31Wednesday, March 18, 2015

C237

0.1uF

C228

0.1uF

C222

1.0UF

C345

1.0UF

C349

1.0UF

C240

0.1uF

C220

1.0UF

C344

1.0UF

C313

0.1uF

C350

1.0UF

C348

1.0UF

C247

0.1uF

C342

0.1uF

C219

1.0UF

C347

1.0UF

C351

1.0UF

C251

0.1uF

C354

1.0UF

C312

1.0UF

C346

1.0UF

C334

10uF

C238

0.1uF

C241

0.1uF

C225

1.0UF

C246

0.1uF

C309

0.1uF

C234

0.1uF

C227

0.1uF

C250

0.1uF

C223

1.0UF

C335

10uF

C232

0.1uF

C311

1.0UF

C221

1.0UF

C340

0.1uF

C341

10uF

C352

1.0UF

C310

0.1uF

C229

0.1uF

C236

0.1uF

C343

1.0UF

C249

0.1uF

C239

0.1uF

C216

4.7uFC226

0.1uF

C328

0.1uF

C230

1.0UF

C235

0.1uF

C248

0.1uF

C224

1.0UF

C308

1.0UF

C233

0.1uFC353

1.0UF