Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Research Portfolio Ali Razavieh

Postdoctoral Scholar Millennium Science Complex

Department of Electrical Engineering Penn State University

Tel: 765-729-8073E-Mail: razavieh.a@gmail.com

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Table of Contents

A new Method to Achieve High Transconductance Linearity

through Electronic Transport Properties of Low-Dimensional

Nanowire MOSFETs

3Metal/Semiconductor Contacts in Schottky Barrier InAs Nanowire

Transistors

4

Low-Temperature Oxidation of Silicon Nanowires for Low-Leakage

Gate Dielectric Applications5

Circuit Design Experience6

III-V Quantum Well TransistorsIII-V Quantum-Well MOSFETs

Ferro Electric Capacitors on Silicon and InGaAs 1

2

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Ferroelectric Capacitors on III-V & Si

-2 -1 0 1 2-50

-25

0

25

50

Electric Field [MV/cm]

Po

lari

zatio

n [

C/c

m2]

III-V Substrate

-2 -1 0 1 2-60

-40

-20

0

20

40

60

Electric Field [MV/cm]

Po

lari

zatio

n [

C/c

m2]

Deposition Pressure = 6mtorrAnnealing Temperature = 620°CPad Area = 50x50 µm2

Deposition Pressure = 5mtorrAnnealing Temperature = 550°CPad Area = 45x45 µm2

Voltage 6V-20VStep: 2Vf = 100Hz

Voltage 6V-20VStep: 2Vf = 100Hz

20 nm n++ In0.53Ga0.47As

Ni

Au100nm PZT

10nm HfO2

Pt

Au

2nm InPSilicon Substrate

100nm PZT

10nm HfO2

Pt Contact

Au Contact

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

III-V Quantum Well Substrates

-10 0 10 20 30 40 50

-0.1

0

0.1

0.2

0.3

0.4

0.5

Cross Section Height [nm]

Co

nd

uct

ion

Ba

nd

[e

V]

∆E1,2 = 98meV

∆E2,3 = 158meV

InP S. I.

Buffer ~ 400nm In0.52Al0.48As

14nm In0.7Ga0.3As Channel

2nm InP

20 nm n++ In0.53Ga0.47As Cap

1nm Doped In0.52Al0.48As

2 nm channel In0.52Al0.48As

2 nm channel In0.52Al0.48As

Band-Structure Simulation of the Quantum Well Substrates is done using nextnano Software

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

III-V Quantum Well Device Structure

2nm channel In0.7Ga0.3As

15nm n++ In0.53Ga0.47As

30nm Ni 30nm Ni

Au 50nm Au 50nm

5nm channel InAs

2nm channel In0.7Ga0.3As

Buffer ~ 400nm In0.52Al0.48As

50nm InP S. I.

15nm n++ In0.53Ga0.47As

2nm InP

2nm In0.52Al0.48As

10nm HfO2

2e12/cm2 Si Delta Doping

100nm Ni

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

0 0.5 1 1.50

5

10

15

Voltage [V]

Cu

rre

nt

[mA

]

VGS = 0.2V-1VStep: 0.2VT = 300K

III-V Quantum-Well Ring-FET

-2 -1 0 1

1e-4

1e-3

1e-2

1e-1

Voltage [V]

Cu

rre

nt

[A]

VDS = 0.2V-1VStep: 0.2VT = 300K

Drain

SourceGate Gate2µm

DrainSource

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Previous Works on Metal/InAs Nanowire Contacts Assume that Contacts are Ohmic Due to Fermi Level Pining in the Conduction

Band

Our Work Focuses on Schottky Barrier Heights

Previous Contact Studies

Temperature Annealing

Chemical Treatment

Formation of Metal/InAs Alloys

Removing the Native Oxides (InOx & AsOx)

A. Razavieh, P. Katal Mohseni, K. Jung, S. Mehrotra, S. Das, S. Suslov, X. Li, G. Klimeck, D. Janes, J. Appenzeller, “Effect of Diameter Variation on Electrical Characteristics of Schottky Barrier InAs Nanowire MOSFETs” ACS Nano, 8(6), pp 6281–6287, May 2014

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Extracted Schottky Barriers for InAs Nanowire Transistors (NWTs) are Independent of the Wire Diameter/Band-Gap

A. R

azavieh, P. K

atal Mohseni, K

. Jung, S. M

ehrotra, S. D

as, S. S

uslov, X.

Li, G

. Klim

eck, D. Janes, J. A

ppenzeller, “Effect of D

iameter V

ariation on E

lectrical Characteristics of S

chottky Barrier InA

s Nanow

ire MO

SF

ETs”

AC

S N

ano, 8(6), pp 6281–6287, M

ay 2014

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Electrical Characteristics of Different InAs NWTs Provides Solid Evidence to Back Up the Schottky Barrier Claims

A. R

azavieh, P. K

atal Mohseni, K

. Jung, S. M

ehrotra, S. D

as, S. S

uslov, X. L

i, G

. K

limeck,

D.

Janes, J. A

ppenzeller, “E

ffect of

Diam

eter V

ariation on

Electrical C

haracteristics of Schottky B

arrier InAs N

anowire M

OS

FE

Ts” AC

S

Nan

o, 8(6), pp 6281–6287, May 2014

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Achieving High Transconductance Linearity through Electronic Transport Properties of Low-Dimensional MOSFETs

Major Sources of Non-Linearityin Transistors

1. Transconductance2. Output Conductance

Traditional Methods to Improve Linearity

Provide High Linearity, but Trade-Off Linearity with Noise

or Supply Voltage

Proposed New MethodBias and Operation in 1-D, Ballistic Transport Regime in the Quantum

Capacitance Limit

Provides High Linearity and Requires Low Supply

Voltage

A. Razavieh, N. Singh, A. Paul, G. Klimeck, D. Janes, and Joerg Appenzeller, “A New Method to Achieve RF Linearity in SOI Nanowire MOSFETs,” IEEE RFIC Symposium, pp. 167-170. Baltimore, MD (June 2011)

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Small SwingLarge Swing

Comparison of Linear and Non-Linear FETs

2 31 2 3 3d m gs m gs m gsI g V g V g V )(

2 2

thgsd VVh

qI

Non-Linear TransistorConventional MOSFETs

Vgs -Vth

Linear Transistor1-D Ballistic MOSFETs in the Quantum Capacitance Limit

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

What is the Best Choice of Device Structure to Achieve High Linearity Through this New Method?

Nanowire Transistors

Excellent Scaling Potential

Body Thickness Channel Length

1-D Transport

Oxide Thickness

Quantum Capacitance Limit (QCL)

Ballistic Transport

22( )d gs th

qI V V

h

2277.46m

qg S

h

constEDOSEvEM

dEffEMETh

qI

D

DSd

1

1

~

Ideal Linearity Provides Constant Transconductance which is Independent of the Choice of Channel Material.

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Ultra-Thin Gate-All-Around Silicon Nanowire Transistors are Examined for Linearity Evolution Through Our Proposed Method

a

6nm

cGate

DrainSource

b

250nm

A. Razavieh, S. Mehrotra, N. Singh, G. Klimeck, D. Janes, and J. Appenzeller, “Utilizing the Unique Properties of Nanowire MOSFETs for RF Applications,” Nano Letters, 13(4), pp. 1549–1554, April 2013

Channel Length : 200nm-400nmBody Thickness : 6nmOxide Thickness : 4nm

m*= 0.19m0

Device is biased to Operate in 1-D Transport Regime.

Gate Voltage is Replaced by Channel Potential to Simulate the Operation in QCL.

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Effect of Channel Length on Linearity for Devices Which are Biased to operate in 1-D transport Regime in the QCL is Studied

The linearity trend for devices operating in 1-D ballistic transport regime in the QCL is shown for a wide range of channel lengths (circles and solid line). The dashed line shows the effect of increasing the mean-free-path for the same channel material.

Conclusion:

1- Absolute Linearity (Infinite IIP3) Requires ideal Ballistic Transport2- Larger λ Improves Linearity3- Rate of Change of λ with Energy (Scattering Mechanism) Effects Linearity More than the Length of λ

Ballistic Transport: Mean-Free-path (λ) > Channel Length (Lch)

GAA Si NWTs : λ = 8nm Quasi- Ballitic Transport Lch = 200nm-400nm T = 77K

A. Razavieh, S. Mehrotra, N. Singh, G. Klimeck, D. Janes, and J. Appenzeller, “Utilizing the Unique Properties of Nanowire MOSFETs for RF Applications,” Nano Letters, 13(4), pp. 1549–1554, April 2013

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Effect of Rate of Change of λ on Transconductance Linearity is Examined for 1-D Devices which Operate in the QCL

IIP3 values for 1-D devices in the QCL considering different scattering mechanisms (left plot). IIP3 plot for an ideal ballistic channel is shown for comparison.

A. Razavieh, D. Janes, and J. Appenzeller, “Transconductance Linearity Analysis of 1-D, Quasi-Ballistic Nanowire FETs in the Quantum Capacitance Limit,” IEEE Transactions on Electron Devices, vol.60, no.6, pp.2071,2076, June 2013

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Some Materials Such as Graphene are Inherently Linear

Drain

SourceGraphene Ribbon

2µm

L = 7µmW = 1µm

44

220 )()( diracgsdiracgsd VVaVVaaI

Current Equation in Graphene is almost an even function around the Dirac Point which suppresses the odd-order harmonics and intermodulation products.

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

600°C Wet Oxidation of Silicon Nanowires for Low-Leakage Gate Dielectric Applications (Not Published)

5nm-6nm of thin oxide is grown and used for low-leakage gate dielectric.

Furnace is divided to different temperature zones somehow that pyrogenic reaction between H2 and O2 happens at the 750°C zone but the sample oxidation happens at the 600°C zone.

5nm-6nm of Amorphous SiO2

5nm-6nm of Amorphous SiO2

Crystalline Silicon

Nanowire

Oxidation Time: 5 Hours

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Nickel Silicide

Source/Drain Nickel Contact 100nm

Source

DrainGateGate

2μm Silicon Nanowire

Fabricated devices show very low-leakage current levels through the top-gate .

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

Circuit Design Experience

Analog Circuits

Design and Implementation of a Low-Noise Amplifier, an Active MOS Multiplication-Based Mixer and a Voltage-Controlled Oscillator Using Cadence.

Design and Implementation of a Folded Cascode Op-Amp with Switch Capacitor Filter Using Cadence.

Digital Circuits

Design, Implementation and Layout of an 8-bit Wallace Tree Multiplier with CRitical Path ISolation for Timing Addaptiveness (CRISTA) Using Cadence and Hspice.

Design and Implementation of an 6-T SRAM Cell for Maximum Read Stability with Static Noise Margin (SNM) Analysis Using Cadence and Hspice.

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

List of Publications and Patents

Publications:

1. A. Razavieh, Xu. Li, P. Katal Mohseni, K. Jung, S. Mehrotra, S. Datta, V. Narayanan, Xi. Li, G. Klimeck, D. Janes, and J. Appenzeller, “Low-Dimensional Nanowire Dynamic Random-Access-Memory Cell” Nano Letters, In Preparation

2. S. DasGupta, A. Rajashekhar, A. Razavieh, N. Agrawal, K. Majumdar, S. Trolier-McKinstry, and S. Datta, “Sub-kT/q Switching in Strong Inversion of Ferroelectric Gated Negative Capacitance FETs” Submitted to Symposia on VLSI and Circuits VLSI, 2015

3. A. Razavieh, P. Katal Mohseni, K. Jung, S. Mehrotra, S. Das, S. Suslov, X. Li, G. Klimeck, D. Janes, J. Appenzeller, “Effect of Diameter Variation on Electrical Characteristics of Schottky Barrier InAs Nanowire MOSFETs” ACS Nano, 8(6), pp 6281–6287, May 2014

4. A. Razavieh, D. Janes, and J. Appenzeller, “Transconductance Linearity Analysis of 1-D, Quasi-Ballistic Nanowire FETs in the Quantum Capacitance Limit,” IEEE Transactions on Electron Devices, vol.60, no.6, pp.2071-2076, June 2013

5. A. Razavieh, S. Mehrotra, N. Singh, G. Klimeck, D. Janes, and J. Appenzeller, “Utilizing the Unique Properties of Nanowire MOSFETs for RF Applications,” Nano Letters, 13(4), pp. 1549–1554, April 2013

6. A. Razavieh, N. Singh, A. Paul, G. Klimeck, D. Janes, and Joerg Appenzeller, “A New Method to Achieve RF Linearity in SOI Nanowire MOSFETs,” IEEE RFIC Symposium, pp. 167-170. Baltimore, MD (June 2011)

7. J. Smith, Y. Zhao, A. Razavieh, C. Yang, J. Appenzeller, “Ge/Si Core/Shell Nanowire Structures for Tunneling Devices,” 218th ECS Transactions, 33(6), pp. 707-714. Las Vegas, NV (2010).

Ph.D. Final Defense | Silicon, Germanium, and III-V-Based Tunneling Devices J.T. Smith

List of Publications and Patents

Patents:

A. Razavieh, X. Li, J. Appenzeller, V. Varnarayan, S. Datta, “Multi-Level One-Dimensional Nanowire Memory”, U.S. Patent, Filing in Progress