Registers and Counters

• Two of the most common uses of Flip-Flops

• Both are collections of Flip-Flops

• The registers perform operations like load, clear, shift

• Counters count up or down, load, clear

Synchronous Circuits

• We deal mostly with synchronous circuits

– several exceptions in this chapter

• One (wise) convention is that there is no combinational logic between the clock and the F-F.

• The clock pulse should reach all F-Fs at the same time. No skew

Parallel Load

• The first and most obvious thing to do with a register

• The D F-F loads data at every cycle. We want to control that

• Very easy: put an AND gate before the clock

!!WRONG!!

• No logic before the clock! It is not purebred synchronous otherwise

• Still useful: asynchronous circuits are used widely.

• We can also add an asynchronous clear. We use the letter R for this to distinguish it from the C of the clock

Will not Look Pretty

• The synchronous version will be complex

• The idea is to load the new data when we want them loaded

• And load the old data back in when we want to keep them

• Needs more gates, but that’s life

Shift Registers

• Shift is a very common operation

– mult/divide by 2, 4, 8 etc

– serial load/store

• Very easy if we only want to shift

Data Transfer

• We can transfer data serially

• With an AND gate and two simple shift registers, we can do it (asynchronously)

• We omit many “small” details though...

– like we need a counter

Serial Adder

• Serial adders have some advantages

– little hardware

– no worries about carry propagation delays

– really high clock speeds

– can have any number of bits

• Used to be more common...

We Need...

• Two serial registers

• one full adder

• one F-F to remember the carry

• clock circuitry

• a bit of intuition

Use the Force

• We know how to design sequential circuits

• We can apply the design techniques to our serial adder and might save a gate or two

Serial Adder State Table

PresentState

NextStateInput

Out-put

Flip-FlopInputs

Q

00001111

xy

0001101100011011

Q

00010111

S

01101001

Serial Adder State Table

PresentState

NextStateInput

Out-put

Flip-FlopInputs

Q

00001111

xy

0001101100011011

Q

00010111

S

01101001

JK

0X0X0X1XX1X0X0X0

Universal Shift Register

• Can shift left, right, load, or do nothing

• We need two control inputs

– 00 do nothing

– 01 shift right

– 10 shift left

– 11 parallel load

• Use a MUX (it can get messy with gates)

Counters

• We are interested mainly in binary counters

• We start with asynchronous counters

– they are called ripple counters

• They have many uses in digital and non-digital systems

Ripple Counters

• In asynchronous circuits we are allowed to play with the clock

• We use trailing edge F-F (we could use leading edge too)

• T F-F are ideal for counters

• But D F-F can also be used

Basic Operation

• When counting up a F-F flips when the preceding F-F goes from high to low

• A T F-F should have its input connected to 1

• A D F-F should have its input connected to the complement of its output.

Ripple Down Counters

• Have nothing to do with settling the score after a pillow fight!

• Really easy to do with ripple counters: Either

– use positive edge F-F

– connect the clock of a stage to the complement of the previous stage

BCD Ripple Counter

• Should count from zero to nine

• At nine should cycle back to zero

• We can dream up a solution and verify it

– it is after all an ad-hoc solution

Cascading BCD Ripple Counters

• We can connect several such counters to create multibit counters

• The MSB of every stage is connected to the clock input of the next

Synchronous Counters

• That’s what we know how to do well!

• We can use the standard design procedures

• Or observe that a bit toggles if all its predecessors are 1

– the opposite for down-counters

Down Counters

• We can easily convert the up-counter to down-counter

• We only need to use the complement of the output of a F-F instead of its straight output

How about Both

• The Up-Down inputs connect either the output or the complement of the output to the next stage.

• We should make sure that if both up and down are true the circuit does something meaningful

Let’s Get Ambitious

• Design a counter with

– count up

– parallel load

– no-op

– asynchronous clear

This Thing at the Top

• This looks redundant

• But it really is a buffer to protect the circuit driving the LOAD input

– If we had 16 bits, then the circuit driving LOAD might not be able drive LOAD quickly. The buffer isolates and protects it.

Synchronous BCD Counter

• Less of a black art than designing a BCD ripple counter

• We just have to load zero in the F-F when the count reaches 9

• Or we set the asynchronous clear when the count reaches 10

Counter with Unused States

• Unused states are the source of don’t cares

• One concern is recovery from an error (e.g. due to power fluctuation)

• We design the circuit the usual way

• Then analyze it to see what happens after we go to an unused state

State Table

PresentState

NextState Flip-Flop Inputs

A B C

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A B C

0 0 10 1 01 0 0x x x1 0 11 1 00 0 0x x x

State Table

PresentState

NextState Flip-Flop Inputs

A B C

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A B C

0 0 10 1 01 0 0x x x1 0 11 1 00 0 0x x x

J K J K J K

0 X 0 X 1 X0 X 1 X X 11 X X 1 0 XX X X X X XX 0 0 X 1 XX 0 1 X X 1X 1 X 1 0 XX X X X X X

Ring Counters

• Timing signals can be generated by a regular counter plus a decoder

• Alternatively can be generated by a ring counter

• A single bit is shifted along a circular shift register

Cost of Ring Counters

• Ring counters need more F-F

• They do not need a decoder

• They have a large number of unused states

– and thus create lots of don’t cares in the accompanying combinational logic. But we do not design them in a systematic way.

Advantages-Disadvantages

• More F-F but less combinational logic

• Much less complex wiring

• Reinitialization after an error is hard (we need to be able to specify which F-F are set and which are reset during start-up)

Johnson Counter

• The shift register is a switch tail ring

• Needs half the F-F

• Needs a few two-input gates

Advantages-Disadvantages

• Needs half the number of F-F

• Needs only 2-input gates

• But it still needs gates

• And still needs more than log N F-F

• How about error recovery?

Error Recovery

• There are two ways:

– Detect the illegal state and reset every F-F

– Nudge the counter towards a legal state by assigning

• D_c = (A+C)B

• It will eventually go to a legal state.

HDL for Registers

• Can be done using either structural or behavioral techniques

• Registers can be used (instantiated) then as modules

• We do a few examples

Universal Shift Register

• Design a 4-bit universal shift register

• Make it synchronous

• Do behavioral first

Universal Shift Registermodule shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);   input s1,s0;                     //Select inputs   input lfin, rtin;                //Serial inputs         input CLK,Clr;                   //Clock and Clear   input [3:0] Pin;                 //Parallel input   output [3:0] A;                  //Register output   reg [3:0] A;   always @ (posedge CLK or negedge Clr)     if (~Clr) A = 4'b0000;      else        case ({s1,s0})         2'b00: A = A;              //No change         2'b01: A = {rtin,A[3:1]};  //Shift right         2'b10: A = {A[2:0],lfin};  //Shift left         2'b11: A = Pin;            //Parallel load input        endcaseendmodule

Structural Version

• We have to define the building block

• Then instantiate it several times

Structural Versionmodule SHFTREG (I,select,lfin,rtin,A,CLK,Clr);   input [3:0] I;            //Parallel input   input [1:0] select;       //Mode select   input lfin,rtin,CLK,Clr;  //Serial inputs,clock,clear   output [3:0] A;           //Parallel output //Instantiate the four stages   stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);   stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);   stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);   stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);endmodule 

The Building Block   input [1:0] select;   output Q;   reg Q;   reg D;//4x1 multiplexer   always @ (i0 or i1 or i2 or i3 or select)          case (select)            2'b00: D = i0;            2'b01: D = i1;            2'b10: D = i2;            2'b11: D = i3;         endcase//D flip­flop    always @ (posedge CLK or negedge Clr)         if (~Clr) Q = 1'b0;         else Q = D;endmodule

A Synchronous Counter

• Not much harder given that Verilog has the addition operation built in

• The only tricky thing is the carry-out

Synchronous Countermodule counter (Count,Load,IN,CLK,Clr,A,CO);  input Count,Load,CLK,Clr;  input [3:0] IN;                //Data input  output CO;                     //Output carry  output [3:0] A;                //Data output  reg [3:0] A;  assign CO = Count & ~Load & (A == 4'b1111);  always @ (posedge CLK or negedge Clr)    if (~Clr) A = 4'b0000;    else if (Load)  A = IN;            else if (Count) A = A + 1'b1;      else A = A;                  // no change, default condition endmodule

Ripple Counter

• Yes, even asynchronous circuits can be described in Verilog

• Use structural specification for the counter and behavioral for the F-F that constitutes the building block.

Ripple Countermodule ripplecounter (A0,A1,A2,A3,Count,Reset);   output A0,A1,A2,A3;   input Count,Reset;//Instantiate complementing flip­flop   CF F0 (A0,Count,Reset);   CF F1 (A1,A0,Reset);   CF F2 (A2,A1,Reset);   CF F3 (A3,A2,Reset);endmodule 

Complementing F-Fmodule CF (Q,CLK,Reset);   output Q;   input CLK,Reset;   reg Q;   always @ (negedge CLK or posedge Reset)      if (Reset) Q = 1'b0;      else  Q = #2 (~Q);     // Delay of 2 time units endmodule