reconfigurable computing (en2911x) lecture 01: introduction
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Reconfigurable Computing (EN2911X) Lecture 01: Introduction. Prof. Sherief Reda Division of Engineering, Brown University Spring 2007. Methods for executing algorithms. Reconfigurable computing. Software-programmed processors. Hardware (Application Specific Integrated Circuits). - PowerPoint PPT PresentationTRANSCRIPT
Slide 1
S. Reda EN2911X FALL07
Reconfigurable Computing(EN2911X)Lecture 01: Introduction
Prof. Sherief RedaDivision of Engineering, Brown UniversitySpring
2007
Methods for executing algorithms
S. Reda EN2911X FALL07
Advantages:very high performance and efficientDisadvantages:not
flexible (cant be altered after fabrication) expensive
Advantages:software is very flexible to
changeDisadvantages:performance can suffer if clock is not
fastfixed instruction set by hardware
Advantages:fills the gap between hardware and software much higher
performance than softwarehigher level of flexibility than
hardware
Temporal vs. spatial based computing
S. Reda EN2911X FALL07
Temporal-based execution(software)
Spatial-based execution(reconfigurable computing)
Ability to extract parallelism (or concurrency) from algorithm
descriptions is the key to acceleration using reconfigurable
computing
Reconfigurable devices
S. Reda EN2911X FALL07
Field-Programmable Gate Arrays (FGPAs) are one example of
reconfigurable devicesAn FPGA consists of an array of programmable
logic blocks whose functionality is determined by programmable
configuration bitsThe logic blocks are connected by a set of
routing resources that are also programmable Custom logic circuits
can be mapped to the reconfigurable fabric
Programmable interconnect
Programmable logic blocks
Configuring FPGAs
S. Reda EN2911X FALL07
[Maxfield04]
FPGAs can be dynamically reprogrammed before runtime or during
runtime (virtual hardware) full partial
Uses of reconfigurable devices
Low/med volume IC productionEarly prototyping and logic
emulationAccelerating algorithms in reconfigurable computing
environmentsReconfigurable functional units within a host processor
(custom instructions)Reconfigurable units used as
coprocessorsReconfigurable units that are accessed through external
I/O or a network
S. Reda EN2911X FALL07
[Compton02]
Current problems with conventional computing
S. Reda EN2911X FALL07
Technology scaling doubled the number of devices in an IC
(processors, FPGAs, , etc) every 2-3 years
Scaling also provided devices with reduced delay frequency doubling (with aggressive pipelining) increased power density
Increases in clock frequency slowed down (or stopped); available
devices are used to create multi-processor (multi-core)
processors
Intel VP Patrick Gelsinger (ISSCC 2001)If scaling continues at
present pace, by 2005, high speed processors would have power
density of nuclear reactor, by 2010, a rocket nozzle, and by 2015,
surface of sun.
Why reconfigurable computing is more relevant these days?
Demand for high-performance computation is soaring: large-scale
optimization problems, physics and earth simulation,
bioinformatics, signal processing (e.g. HDTV), , etc)Why
software-programmed processors are no longer attractive?Faster
temporal execution of instructions) is no longer
improvingGeneral-purpose multi-core processors requires coarse
grain thread-level parallelismWhy reconfigurable fabrics are
currently attractive?Increased integration densities allow large
FPGAs that can implement substantial functionsProvide the spatial
computational resources required to implement massively-parallel
computations directly in hardware
S. Reda EN2911X FALL07
S. Reda EN2911X FALL07
Topics that will be covered in this class(entry survey
time)
Topic 01: Programmable logic technology overview
S. Reda EN2911X FALL07
Programming information could be stored in SRAM4-input Look-Up
Table (LUT) is the typical size
0
|
&
y = (a & b) | !c
a
b
c
y
000
0
0
0
a
1
b
1
a
b
c
1
1
c
1
0
1
8:1 Multiplexer
0
0
SRAM cells
Programmed LUT
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
001
010
011
100
y
101
Required function
Truth table
110
111
y
Topic 01: Programmable logic technology overview
S. Reda EN2911X FALL07
Switchbox
4-inputLUT
a
b
c
flip-flop
clock
mux
y
q
e
d
Topic 02: Reconfigurable computing methodologies
S. Reda EN2911X FALL07
synthesis (compilation)
Mapping (placement & routing)
configuration data
compile for target processor
Graphical Flowchart
Graphical State Diagram
When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);
Textual HDL
Block-level schematic
Top-level block-levelschematic
Topic 03: Hardware programming languages (Verilog)
Verilog is a hardware description language used to model digital
systemsSimilar in syntax to CDiffers from conventional programming
languages as the execution of statements is not strictly linear.
Possible to have sequential and concurrent execution statementsThe
language can be synthesized into logic circuits
S. Reda EN2911X FALL07
module mux(a, b, select, y); input a, b, select; output y; initial
begin always @ (a or b or select) if (select) y = a; else y = b;
endendmodule
Topic 04: Rapid prototyping with Altera DE2 board
S. Reda EN2911X FALL07
No need to design our board; we will use Alteras DE2 board and
Quartus II software.Features:Cyclone II FPGA 35K LUTs 10/100
Ethernet RS232 Video out (VGA 10-bit DAC) Video in
(NTSC/PAL/multi-format) USB 2.0 (type A and type B) PS/2 mouse or
keyboard port Line in/out, microphone in (24-bit Audio CODEC)
Expansion headers (76 signal pins) Infrared port Memory 8-MBytes
SDRAM, 512K SRAM, 4-MBytes flash SD memory card slot Displays 16 x
2 LCD display Eight 7-segment displays Switches and LEDs
Topic 05: High-level synthesis languages (SystemC)
S. Reda EN2911X FALL07
SystemC is a system description language for hardware/software
systemsSystemC is a set of library and macros implemented in C++ to
allow specification and simulation of concurrent processesAllow
high-level description of hardware modulesA subset of the language
can be synthesized into logic circuits. We will use Celoxica
Agility compiler as our synthesizer tool
#include "systemc.h" SC_MODULE(adder) { sc_in a, b; sc_out sum;
void do_add() { sum = a + b; }
SC_CTOR(adder) { SC_METHOD(do_add); sensitive