Recent advances in lithography and high level metrology needs for lithography

Recent advances in lithography and high level metrology needs for lithography

Scott Hector*Mask Strategy Program ManagerSEMATECHAustin, TX 78741

* On assignment from Freescale Semiconductor, Inc.Acknowledge: Ben Bunday Andrew Grenville, Stefan Wurm, Kim Dean, Jonathan Cobb, and Sergei Postnikov

Outline

• Future lithography in next five years– Overview of immersion lithography– Overview of EUV lithography

• CD and LWR control for lithography• DFM and metrology needs

Resolution of Optical Lithography

Mask

Wafer

θ

NAkHPMIN

λ1=

Finer resolution can be achieved by:– Shorter wavelength (436 nm…365 nm …248

nm…193 nm…13.5 nm)– Increased numerical aperture

• Immersion with NA>1– Reduced k1

• Improved masks (CD control, Phase Shift masks)

• Improved lenses (aberrations)• Better photoresists• Better process controls • Resolution Enhancement Techniques

(RET)

General requirements for lithography• Critical dimension (CD) control

– Size of many features in a design needs to be accurate and precise– CD control needs to be maintained within each exposure field, over each

wafer and from wafer to wafer• Overlay

– The placement of the image with respect to underlying layers needs to be accurate on each integrated circuit in all locations

• Defect control– The desired pattern must be present in all locations, and no additional

patterns should be present.– No particles should be added to the wafer during the lithography

process.• Low cost

– The cost of tools and masks needs to be as low as possible while still meeting the CD control, overlay and defect control requirements

– The lithography step should be performed as quickly as possible– Masks should be used to expose as many wafers as possible– Equipment needs to be reliable and ready to expose wafers when

needed

Metrology plays a critical role in all of these requirements

2004 Lithography exposure tool potential solutions

Notes: EPL is a potential solution at the 65, 45 and 32-nm nodes for one geographical region, and PEL is a potential solution at the 32-nm node for one geographical region. RET will be used with all optical lithography solutions, including with immersion; therefore, it is not explicitly noted.

Technology Node2007 2013 20192004 20162010

hp90 hp65 hp32 hp16hp22hp45

Research Required

Development Underway

Qualification/Pre-Production

Continuous Improvement

DRAM Half-pitch(dense lines)

Tech

nolo

gy O

ptio

ns a

t Tec

hnol

ogy

Nod

es(D

RA

M H

alf-P

itch,

nm

)90 193 nm

65193nm + LFD193nm immersionPEL

32EUV193nm immersion + LFD157nm immersion + LFD, ML2Imprint

22EUVInnovative 157nm or 193 nm immersionML2Imprint, innovative technology

16 Innovative technologyML2, EUV + RET, imprint

45193nm immersion + LFDEUVML2, 157nm immersion, PEL

RET = Resolution enhancement technologyLFD = Lithography friendly design rulesML2 = Maskless lithography

Lithography Potential Lithography Potential Solutions in 2004 UpdateSolutions in 2004 Update

Unofficial version of Figure 34; Not for publication

Resolution Improvement by Immersion

LIQUIDAIR

RESISTLIQUID

RESISTAIR

RESIST

RESISTWETMIN

n

nnn

HP

θλ

θλβ

λ

sin41

sin41

sin41

,

=

=

=

θλ

θλ

αλ

sin41

sin41

sin41

,

AIR

RESIST

RESISTAIR

RESIST

RESISTDRYMIN

nn

HP

=

=

=

Silicon Wafer

Photoresist

Lens

θ Liquid θ

Photoresist

Silicon Wafer

Lens

Enabling NA > 1.3Numerical aperture

1.4 1.5 1.6 1.7

High Index FluidWaterImmersion

Fluid

High Index Lens Material

Final Lens Element

Resist

Plano CaF2or SiO2

Curved Final Element

Existing Platforms

High Index Resist

Earlier increase in index of fluid and/or resist yields process latitude improvement

193i Technology (45nm Half Pitch)Hyper NA

Optics

Fused Silica

Final Optic Durability /

Contamination

Enabling NA>1.45

Fluid StandardsImmersion Defectivity

Fluid Handling

High Index Fluid

ResolutionLWR

SensitivityProcess

Capability

Leaching

Immersion

Fluid

EXPOSURETOOL

MASK

LOWk1

RESIST

AbsorberMask CD MetrologyPattern Transfer

Placement Metrology

Cleaning

Repair

Defect Review

Pellicle

Blank

Patterning

Mask

Defect

Control

Thermal Control

193i

Productivity

Overlay

Laser Platform

Layout / DFM

CaF2

Substrate

Potential Showstopper / Requires InventionCritical Issue / Development RequiredSolution Known

Addressed in part by ISMTAddressed by others

Overlay

CDSEM

METROLOGY

Pattern Generator

Defect InspectionDouble Expose

Extreme Ultraviolet Lithography(EUV)

Laser80

012.0 13.0 14.0

λ (nm)

Ref

. (%

)

40

All optics surfaces coated with multilayer reflectors (40 - 80 layer pairs, each layer approx λ/4 thick, Control ~0.1 Å)

Wafer

CondenserOptics4X Reduction

Optics

EUV imaging with ultrathin resist (UTR)

Laser ProducedPlasma

ReflectiveReticle

Ring Field IlluminationScanning mask and wafer stages Flat, square mask with multilayers

Reflective Optical Surfaces are Aspheric with Surface

Figures & Roughness < 3 Å

λ = 13.5 nm

35nm70nm

Absorber

Buffer

Multilayer

Low thermal expansion substrateTEM courtesy of AMD

Absorber

Buffer

Multilayer

Low thermal expansion substrateTEM courtesy of AMD

EUV Mask Technology Patterned Absorbers

~ 50-100 nm thick(e.g. Al, Cr, TaN, W)

Buffer Layer~ 30-50 nm thick

(e.g. SiO2)Capping Layer

Ru (2nm) or Si (11nm)Reflective Multilayers

~ 300 nm thick(Mo - Si = 13.5nm)

40 - 50 Pairs

Low thermal expansion material (LTEM) substrate

φ1

6o

Full Field 6” EUV Mask with 100-nm node CMOSMultilayers: Mo - Si

Absorber Stack: Cr/SiON120 mm x 104 mm field size

(Courtesy of P. Mangat & S. Hector, Motorola)

• Key challenges for EUV mask multilayers

– High uniformity of thickness– No printable defects– Temperature stability

EUV Infrastructure

Patterning

Protec

tion

Cleaning

Repair

LifetimePotential Showstopper/Requires InventionCritical Issue/Development RequiredSolution Known

Gap addressed by ISMTAddressed by others

TOOL

Vacuum

stage

Source

OpticsBlank

Inspection

RESIST

METROLOGY

EUV MASK

Thermal ManagementFundamental

Constraints – SourcePower & Lifetime

Commercial High Power

Source

ML CoatingsFigure / Finish

Alignment Stability

ChuckingThermal Management

Inspection/Reflect

AlgorithmsAIMSTool/Process

Sub-100nm particleanalysis & clean

RepairInspectionML Coating

FinishFlatness

Molecular Contam.Defects

Form FactorActive

Protection

FIBE-beam

ESD Control

Defects

OverlayCD SEM

Resist TestingOutgassing

LERSensitivityResolution

Process Capability

Image Placement

CD MetrologyResistPattern

Generator

Immersion and EUV tool timing

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q42003 2008

Exitech

ASML

Canon

Nikon

2004 2005 2006 2007

0.85NA >0.9NA >1NA

1.05NA (RIT) 1.3NA (ISMT) >1.4NA

0.75NA

0.75NA >1NA

0.85NA 0.92NA >1NA

>> 1NA

193 immersion

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q42008 2009

EXPOSURE TOOL

ROADMAPS

2004 2005 2006 2007

ASML < 10 wphExitech MET ASML 30 wph ASML 80 wph

Nikon High NA set 3 Nikon Beta Nikon HVM

Canon < 10wph Canon 60wph

EUV

2004 ITRS lithography requirements are challenging

Year of Production 2004 2007 2010 2013 2016Technology Node hp90 hp65 hp45 hp32 hp22DRAM ½ Pitch (nm) 90 65 45 32 22MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 107 76 54 38 27MPU Gate in resist Length (nm) 53 35 25 18 13MPU Gate Length after etch (nm) 37 25 18 13 9Gate CD control (3 sigma) (nm) 3.3 2.2 1.6 1.2 0.8Overlay 32 23 18 13 8.8Mask CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary mask 3.8 2.2 2 1.3 0.5Line Width Roughness (nm, 3 sigma) <8% of CD 4.2 2.8 2 1.4 1

• Gate CD control is intended to represent total CD variation

– Is it possible to meet the desired gate CD control values?

Manufacturable solutions exist, and are being optimizedManufacturable solutions are known

Interim solutions are knownManufacturable solutions are NOT known

Major CD error sources• Intrafield

– Dose uniformity– Focus uniformity– Aberration variation within the field– Mask CD uniformity– Imperfect optical proximity correction (OPC)– Flare variation for EUV

• Interfield– PEB temperature variations– Dose variation– Mean focus variation

Metrology critical to identifying and reducing systematic errors

Calculated CD variation at 45nm half pitch

MEEFDense 1.94Iso 0.36

0

1

2

3

4

5

6

80nm

90nm

isol

atedPitch (nm)

Tota

l CD

var

iatio

n (3

sigm

a in

nm

)

AltPSM, 193nmimmersion

6% EPSM w/ SRAF,193nm immersion

EUV BIM, 3% 3sigmaflare variation

EUV BIM, 1.5%3sigma flare variation

EUV BIM, no flarevariation

No flare variation

Dense 1.63Iso 1.33

ITRS 2004:1.2 nm 3σ

Dense 1.06Iso 1.12

• Both 193nm immersion and EUV (k1=0.83) will probably not meet ITRS requirements

• Under near ideal optical lithography conditions, 193nm immersionat near maximum NA with water (k1=0.31) with AltPSM may provide better CD control if EUV flare variation is not fully compensated

Importance of Line Edge and Width RoughnessImportance of Line Edge and Width Roughness

Fourier PSD, averaged

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E-03 1.E-02 1.E-01 1.E+00f

PSD

[nm

3]PSD a

PSD b

PSD CD

Example: poly-silicon line

Edge assignment from SEM algorithmLine

-20

0

20

40

60

80

100

120

140

160

0 200 400 600 800 1000scan

edge a corr

edge b adj

CD

Spatial frequency (nm-1)

LER

LWR

• Line Edge Roughness (LER) (High frequency roughness)

– Can affect dopant concentration profiles

– Probably affects interconnect resistance

• Line Width Roughness (LWR) (Mid-frequency roughness)

– Leakage of transistors affected– Affects device speed of

individual transistors– Leads to IC timing issues

Ben Bunday, SEMATECH

Areas of potential device impact

Fringing Field Disorder

n+ n+

Gate

Rough Gate Edge

Junction edge fluctuations

Gate-SD Overlap disorder

Halo fluctuations

Poly ρs

• Front end patterning– LWR after etch is what

matters, not LWR in resist– LWR affects leakage

current more strongly than drive current

Ioff

( nA

/ um

on

log

scal

e )

Ion ( uA / um )

L=50nm

L=40nm

L=32nm

Nominal device w/o LER

7nm 3σ LER

Eric Verret, Aaron Thean and Jonathan Cobb; Freescale Semiconductor

Trends to manage CD control and yield• Present approaches are not enough

– More stringent design rule restrictions– Single orientation, pitch restrictions– Larger CD on resist– Relaxed minimum half pitch– Use of resolution enhancement technology (RET)– Field by field and within field dose corrections

• Further actions--DFM– Automation of software analysis of weak spots in design and feedback to

physical layout of cells• RET applied to library cell layouts

– Coordinates of weak points provided to mask and wafer CD metrology tools• Focus and exposure are optimized for printing hot spot regions with maximum

process latitude rather than for CD of CD bars. – Identification of critical timing paths to locally specify CD control– Test programs optimized to detect electrical effects at weak points – Local corrections of mask to account for variations of scanner—mask

specification to particular scanners – Software for reduction of slivers in design data is also being developed to

reduce mask CD error and writing time.

Based on IBM, Intel, ASML and Toshiba presentations at SPIE and PMJ

BIM PSM

Present mode of operation for circuit design and fabrication

Organizational, corporate cultural and geographical

barriersDesignersWafer fab

Circuit architecture

Masks

Layout Test data Packaged IC

Device models Design rules

Incorporating design intent in new ways

• Vary intensity of RET based on location in circuit with respect to critical timing paths

• Increase metrology and decrease allowed tolerances where most needed

• Vary intensity of RET based on location in circuit with respect to critical timing paths

• Increase metrology and decrease allowed tolerances where most needed

Mark shapes in layout that affect critical circuit timing (shown in red)

Mark shapes in layout that affect critical circuit timing (shown in red)

Without DFM (RET applied

uniformly)

With DFM (RET applied

where needed)

Layout from

designer

Layout with RET

Incorporating design intent in new ways

• Optimize floor plan based on critical timing paths

• Place and route optimized based on critical timing

Potential problems areas marked where critical timing paths exist in regions with large variations

Known contours of CD, topography or overlay error with mfg. process

Change layout to move critical timing paths to areas without

smallest errors

New mode of operation with design for manufacturing (DFM) practices

Designers Wafer fab

Circuit architecture

Masks optimized based on design intent

Layout with critical paths

BIM, ACI CD 78PSM, ACI CD 8BIM, ACI CD 74 Packaged IC

Device models Design rules

Statistical timing

optimization0

10203040

Freq

uenc

y

Process variation distributions

Test data

Known contours of CD, topography or overlay error with mfg. process

Conclusions• 193nm immersion and EUV lithography are promising

candidate technologies for 45-nm and 32-nm half-pitch patterning

– Significant challenges remain in developing either technology toprovide a timely, economical manufacturing solution

• Maintaining ±10% CD control doesn’t appear to be possible

– Metrology precision improvements critical to reducing systematicerrors

• Measuring and controlling LWR and LER becoming increasingly important

• Increasing integration of design, lithographic resolution enhancement techniques and extensive metrology will be needed to maintain expected circuit performance

– DFM drives need for improved precision and throughput