radiation hardness improvement of fd-soi mosfets for x-ray … · 2016. 7. 14. · fd-soi is...

Radiation hardness improvement of FD-SOI MOSFETs for X-ray detector application

Ikuo Kurachi1, Kazuo Kobayashi2, Marie Mochizuki3, Masao Okihara3, Hiroki Kasai4, Takaki Hatsui2, Kazuo Hara5, Toshinobu Miyoshi1, and Yasuo Arai1

1 High Energy Accelerator Research Organization (KEK)2RIKEN SPring-8 Center

3Lapis Semiconductor Co., Ltd.4Lapis Semiconductor Miyagi Co., Ltd.

5Faculty of Pure and Applied Science, University of Tsukuba

Jul. 14, 2016 / China-Japan Mini Workshop @ IHEP, Beijing 01/20

Outline

02/20

1. Introduction2. Experimental Procedure3. PMOSFET Radiation Hardness Improvement by LDD Dose Change4. NMOSFET Radiation Hardness Improvement by LDD Dose Change5. Further Improvement by Applying Substrate Bias6. Summary

Introduction

03/20

FD-SOI is suitable structure for monolithic charged particle image sensor.However, radiation tolerance of FD-SOI MOSFET is generally lower than that of bulk-CMOS in total ionizing dose effect (TID).

How low? Any improvement ?

0.2 mm FD-SOI X-ray Sensor Process is based on FD-SOI process for ultralow power operation not for radiation hardness.

We have chance to find some room to improve radiation tolerance by analyzing mechanisms of radiation damage of FD-SOI MOSFET in detail.

Target radiation tolerance: >1 MGy

LHC pixel : ~ 500 kGy, 1015neq/cm2@ATLAS (x10 for HL-LHC)Belle-II : ~ 10 kGy/y, 2x1012neq/cm2 /yILC (e.g., ILD @ r=15 mm) : ~ 1 kGy/y, ~1011neq/cm2 /yX-ray imaging: : kGy/y 〜MGy/y

Experimental Procedure

Nch LDD ConditionULP-LDD : X1RH-LDD : X2.5

X-ray irradiationMolybdenum Target with acceleration voltage of 40 kV0.5 mm Aluminum filter to suppress X-ray below 10KeVDose rate ： 0.018 or 3 Gy(Si)/sAll terminals of MOSFETs are grounded during irradiation

MOSFETRADTEGBF W=10 mm L=0.2/0.3/0.5/1.0/10 mm core Normal Vt （I-V）BT W=5 mm L=0.2/1.0 mm core Normal Vt (Charge Pumping)

Ids_lin : Vds=0.1V, Vgs=1.8V, Ids_sat : Vds=1.8V, Vgs=1.8VVto : extrapolated from Id-Vg @ Vds=0.1V around gm_max pointsCharge Pumping : f=1MHz, tr=tf=1nS, duty 50%, delta Vg=1.5V, Nit=Icp/qSf

Pch LDD ConditionULP-LDD : X1RH-LDD : X6

Lapis Semi. 0.2 mm FD-SOI X-ray Sensor Process

04/20

In detail, refer to T. Kudo et al., IEEE Trans. Nucl. Sci. 61 (3), pp. 1444-1450, 2014.

PMOS Drain Current Degradation due to RIGLEM

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.001 0.01 0.1 1 10

DI d

_li

n/I

d_

lin

0

X-ray Dose (kGy(Si))

L=0.2mm

L=10mm

Id_lin : Ids @ Vgs=-1.8V, Vds=-0.1V

W=10mm

0

0.01

0.02

0.03

0.04

0.05

0.001 0.01 0.1 1 10DdL

(m

m)


Pre-rad. dL : -0.0421mm

𝑅𝑚 = 𝜌𝑐ℎ𝐿𝑒𝑓𝑓

𝑊𝑒𝑓𝑓+ 𝑅𝑠 + 𝑅𝑑

𝐿𝑒𝑓𝑓 = 𝐿 + 𝛿𝐿

∆𝛿𝐿 = 𝛿𝐿 𝑥 − 𝛿𝐿 0

In detail, please refer toI. Kurachi et al., “Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs,” IEEE Trans. Electron Devices, Vol. 62, No. 8, pp. 2371-2376, 2015.

Terada’s method

Linear drain current degradation of shorter gate length MOSFET is faster than that of longer gate length MOSFET.

Drain current degradation is mainly caused by Radiation Induced Gate LEngth Modulation (RIGLEM) not Vt shift nor mobility reduction.

05/20

Dose Rate : 0.018 Gy(Si)/s

Possible Cause of RIGLEM

Gate

BOX

P+ P+P- P-

LDD（Lightly Doped Drain)

When LDD dope is low or N-/P- is offset, possibility to form parasitic transistor at gate edge.

Drain current degradation due to RIGLEM has gate length dependence. Thus, the cause must be located at gate edges.

SOI MOSFET is designed for ultralow power operation. To reduce off-leakage by GIDL, the LDD dope is low. LDD may be slightly offset from gate.

Formation of parasitic transistors at gate edges and positive charge generation in sidewall spacer are the most possible causes!!

If so, higher LDD dose must be a solution to eliminate RIGLEM.

06/20

Elimination of Gate Offset by Higher LDD Dose (Pch)

0.1

1

10

100

0.1 1 10

I d_li

n/W

(m

A/m

m)

Gate Length (mm)

ULP-PLDD

RH-PLDD

I. Kurachi et al., “Tradeoff Between Low-Power Operation and Radiation Hardness of Fully Depleted SOI pMOSFET by Changing LDD Conditions,” IEEE Trans. Electron Devices, Vol. 63, No. 6, pp. 2293-2298, 2016.

High dose LDD : RH-LDD is 6 time high dose of ULP-LDD Improvement of linearity between gate length and drain current by RH-LDD is confirmed. Higher boron concentration underneath gate for RH-LDD is also confirmed using TCAD. “offset” structure can be eliminated by using RH-LDD.

07/20

Boron concentration distribution

Radiation Tolerance Improvement by RH-LDD

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

1 10 100 1000

DI d

_li

n/I

d_li

n0


ULP-PLDD

RH-PLDD

L=0.2 mm

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.1 1 10

DI d

_li

n/I

d_li

n0

L (mm)

ULP-PLDD

RH-LDD

X-ray Dose : 112 kGy(Si)


Drain current degradation improvement : 80 to 20% after 112kGy irradiation by ULP-LDD to RH-LDD. Almost no gate length dependence of drain current degradation when RH-LDD is used. Radiation hardness improvement by RH-LDD is confirmed. Radiation degradation is mainly caused by Vt shift of parasitic MOSFET at gate edges due to

generated positive charge in sidewall spacer.

08/20

Dose Rate : 3 Gy(Si)/s

Improvement for Gate Length Modulation

0.0

0.5

1.0

1.5

1 10 100 1000

DdL

(m

m)


ULP-PLDD

RH-PLDD


For RH-LDD, no or less gate length modulation is observed. High LDD dose improves offset gate structure and eliminates RIGLEM. Consequently, improve

radiation hardness and reduce gate length dependence of drain current degradation.

09/20


Elimination of Gate Offset by Higher LDD Dose (Nch)

1

10

100

1000

0.1 1 10

I d_sa

t/W

(m

A/m

m)

Gate Length (mm)

Meas. LD-LDD (X1)

Meas. HD-LDD (X2.5)

Sim. (X1)

Sim. (X2)

Sim. (X3)

High dose LDD : RH-LDD is 2.5 time high dose of ULP-LDD Improvement of linearity between gate length and drain current by RH-LDD is confirmed. X2 LDD dose is enough to eliminate gate offset from TCAD results. “offset” structure can be eliminated by using RH-LDD.

10/20

NMOS Radiation Tolerance Improvement by RH-LDD

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

1 10 100 1000

DI d

_li

n/I

d_

lin

0


ULP-LDD

RH-LDD

L = 10 mm

L = 0.2 mm

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.1 1 10

DI d

_li

n/I

d_li

n0

Gate Length (mm)

ULP-LDD (Nch)

RH-LDD (Nch)

RH-LDD (Pch)

112 kGy(Si)

In L=10 mm case, no difference between ULP-LDD and RH-LDD. In L=0.2 mm case, drain current degradation rate is slightly improved by RH-LDD. Gate length dependence of drain current degradation is also slightly improved by RH-LDD. Why NMOS case is so different from PMOS case??????

11/20


Compensation by Substrate Bias

0.75

0.80

0.85

0.90

0.95

1.00

-20 -10 0 10

Vto

(V

)

Vsub (V)

0 kGy(Si)

1.1

5.622

56112X-ray Dose

RH-LDD

L=0.2 mm

-0.4

-0.3

-0.2

-0.1

0

0.1

1 10 100 1000

DI d

_li

n/I

d_

lin

0


ULP-LDD

RH-LDD

L=10 mm

L=0.2 mm

W/ Vsub correction

Substrate bias (Vsub) which aligns Vto to fresh one can be found from Vsub-Vto relation. With compensation by correct Vsub, almost no drain current degradation in L=10 mm case. This

means major cause of drain current change of L=10 mm is generated positive charge in BOX. In case of L=0.2 mm, still 15% degradation with Vsub correction even if RH-LDD is used.

12/20


NMOS Drain Current Degradation Mechanism

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

1 10 100 1000

DI d

_li

n/I

d_li

n0


ULP-LDD

RH-LDD

L = 10 mm

L = 0.2 mm

L=10 mmDrain current change is mainly caused by generated

positive charge in BOX because the change can be suppress by applying Vsub.

L=0.2 mmAssuming

ULP-LDD : gate offset structure, RH-LDD : no gate offset structure

Up to 20 kGyULP-LDD : due to generated positive charge in BOX

and Sidewall Spacer.RH-LDD : due to generated positive charge in BOX.

More than 20 kGyDrain current reduction means mobility reduction

by generated interface states.There is gate length dependence of drain current

reduction rate. Generated interface states at gateedges are suspected to be higher than those at center of gate.

Positive charge in sidewall spacer

Mobility degradation by Nit

13/20

Evidence of Higher Interface State Region at Gate Edge

0

20

40

60

80

0 20 40 60 80 100 120

Nit

( 1

01

0cm

-2)


L= 0.2

L= 1.0 mm

mm

Body-tie MOSFET

W= 5 mm

Nit=3.05×1012 DX-ray + 3.23×1010

When there are higher interface state regions at gate edge by X-ray irradiation, generated interface states must be higher for shorter gate length MOSFETs.

Even though initial Nit is the almost same, generated interface states of L=0.2 mm are almost twice of L=1.0 mm.

It is confirmed that there are higher interface state regions at gate edge.

14/20


NMOS REGLEM Degradation Model

𝐼𝑑𝑠 =𝑊𝑒𝑓𝑓

𝐿𝑒𝑓𝑓1𝜇1𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑡𝑜1 𝑉𝑑𝑠1


𝐿𝑒𝑓𝑓2𝜇2𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑑𝑠1 − 𝑉𝑡𝑜2 𝑉𝑑𝑠2


𝐿𝑒𝑓𝑓3𝜇3𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑑𝑠1 − 𝑉𝑑𝑠2 −𝑉𝑡𝑜3 𝑉𝑑𝑠3


𝐿𝑒𝑓𝑓2𝜇2𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑑𝑠1 − 𝑉𝑑𝑠2 − 𝑉𝑑𝑠3 − 𝑉𝑡𝑜2 𝑉𝑑𝑠4


𝐿𝑒𝑓𝑓1𝜇1𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑑𝑠1 − 𝑉𝑑𝑠2 − 𝑉𝑑𝑠3 − 𝑉𝑑𝑠4 − 𝑉𝑡𝑜1 𝑉𝑑𝑠5

𝑉𝑑𝑠 = 𝑉𝑑𝑠1 + 𝑉𝑑𝑠2 + 𝑉𝑑𝑠3 + 𝑉𝑑𝑠4 + 𝑉𝑑𝑠5 (1)

Assuming 𝜇1 = 𝜇3 and 𝑉𝑡𝑜2 = 𝑉𝑡𝑜3, ∆𝛿𝐿 = 𝐿𝑒𝑓𝑓 𝑥 − 𝐿𝑒𝑓𝑓 0

becomes

∆𝛿𝐿 = −2𝐿𝑒𝑓𝑓1∆𝑉𝑡𝑜1 + 2𝜇3 − 𝜇2𝜇2

𝐿𝑒𝑓𝑓2

∆𝑉𝑡𝑜1 =𝑞𝑇𝑜𝑥_𝑠𝑤𝑁𝑜𝑡_𝑠𝑤

휀

𝜇 =𝜇0

1 + 𝛼𝑁𝑖𝑡𝜇3 − 𝜇2𝜇2

=𝛼 𝑁𝑖𝑡2 − 𝑁𝑖𝑡31 + 𝛼𝑁𝑖𝑡3

=𝛼(𝑎 − 1)𝑁𝑖𝑡31 + 𝛼𝑁𝑖𝑡3

𝑁𝑖𝑡2 = 𝑎𝑁𝑖𝑡3

0.001 0.1 10 1000

Notin

BO

X (

cm-2

)


0.018 Gy(Si)/s

3 Gy(Si)/s

1010

1011

1012

1013

Dose Rate

Not=exp(0.253 ln(DX-ray) + 25.11

190

200

210

220

0 10 20 30 40

Mo

bil

ity

(cm

2/V

s)

Nit (×1010 cm-2)

Meas.

Model

Body-tie MOSFET

W=5 mm, L=1.0 mm

If DdL is minimized, dependence of drain current degradation on gate length can be improved and major cause of drain current change must be due to generated positive charge in BOX.

15/20

Comparison between Measured and Calculated DdL

-0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.1 1 10 100 1000

DdL

(m

m)


ULP-LDD (Meas.)

ULP-LDD (Model)

RH-LDD (Meas.)

RH-LDD (Model)

a (cm3) Tox_sw (nm) Leff1 (mm) Leff2 (mm) a

ULP-LDD 2.69 X 10-13 65 0.002 0.085 4.3

RH-LDD 2.69 X 10-13 ----- ----- 0.050 4.3

Fitting curves based on model can be obtained for both ULP-LDD and RH-LDD which indicates accuracy of model.

Interface state generation at gate edge is one of major factors for radiation damages in NMOS. It is suggested that suppression of interface state generation such as F dope or NO annealing is key improvements for NMOS radiation hardness.

16/20


Further Improvement of Radiation Hardness

When gate length dependence of drain current change is eliminated or reduced, major cause of change is generated positive charge in BOX for SOI-NOSFET.

Fortunately, we have back bias layer (middle SOI) in double SOI structure. We can apply compensation back bias (Vsub) to reduce effect of positive charge in BOX.

Handle Wafer

Middle SOI

SOI MOSFET

+ + + +BOX

Apply bias to compensate positive charge in BOX

Can we have accepted bias (Vsub) to reduce drain current change for both NMOS and PMOS, or for wide range of gate length?

17/20

Drain Current Change on Vsub

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2

DI d

_li

n/I

d_

lin

0

Vsub (V)

Nch PchAVE.

MAX

MIN

X-ray Dose : 1.1 kGy(Si)

L=0.2/0.3/0.5/1.0/10 mm

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2

DI d

_li

n/I

d_li

n0

Vsub (V)

Nch PchAVE.

MAX

MIN

X-ray Dose : 5.6 kGy(Si)

L=0.2/0.3/0.5/1.0/10 mm

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2

DI d

_li

n/I

d_li

n0

Vsub (V)

NchPch

AVE.

MAX

MIN


L=0.2/0.3/0.5/1.0/10 mm

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2

DI d

_li

n/I

d_li

n0

Vsub (V)

NchPchAVE.

MAX

MIN


L=0.2/0.3/0.5/1.0/10 mm

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2

DI d

_li

n/I

d_li

n0

Vsub (V)

Nch

PchAVE.

MAX

MIN


L=0.2/0.3/0.5/1.0/10 mm

NLDD:RH-LDDPLDD:RH-LDD

1.1 kGy(Si)

5.6 kGy(Si)

22 kGy(Si)

56 kGy(Si)

112 kGy(Si)

18/20


Drain Current Change Compensation by Applying Vsub

-12

-10

-8

-6

-4

-2

0

1 10 100 1000

Vsu

bfo

r a

ve.

deg

rad

ati

on

=0

(V

)


Nch

Pch

-16

-14

-12

-10

-8

-6

-4

-2

0

1 10 100 1000

Acc

epta

ble

Vsu

b w

ith

in 1

0%

deg

. (V

)


Required Vsub to recover drain currents are different between NMOS and PMOS. Even though, Vsub to make drain current change within 10% for NMOS and PMOS with L=0.2-10

mm up to 100 kGy exists. Compensation of BOX charge by applying Vsub may be the best way to improve radiation hardness

to MGy range even for FD-SOI MOSFET.

19/20


Summary

20/20

1. Current LDD structure (ULP-LDD) is weak in radiation tolerance because of RIGLEM.

2. Higher dose LDD structure (RH-LDD) improves radiation hardness.PMOS : Improve 80% to 20% degradation after 100 kGy(Si) irradiationNMOS : Slightly improve for shorter gate length MOSFETs

3. Major degradation mechanism by X-ray radiation except for generated positive chargein BOX is interface state generation at gate edge. Therefore, improvement by changingLDD concentration is not so obvious.

4. Generated positive charge in BOX can be compensated by applying substrate bias.

5. Substrate bias which can be suppress the drain current change within 10% for NMOS and PMOS, and L=0.2 to 10 mm, up to 100 kGy(Si) irradiation is confirmed to exist.

6. Further radiation hardness improvement must be done by automatic substrate bias control to compensate BOX charge.

radiation hardness improvement of fd-soi mosfets for x-ray … · 2016. 7. 14. · fd-soi is...

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