soitec ultra-thin soi substrates enabling fd-soi technology · fd soi – performance, power &...
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Soitec ultra-thin SOI substrates enabling FD-SOI technology
July, 2015
Agenda
• FD-SOI: Background & Value Proposition
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Today Ultra-mobile & Connected Consumer
Intensified Challenges
At Any Time With Anyone Anywhere
(any place, any service,
any network)
With Anything
Outstanding Performance Longer battery life Optimized cost
$$$$
July 8, 2015 3 C1- Restricted
FD SOI – Performance, Power & Cost Efficiency
4
28nm FD-SOI provides « 20nm performance at 28nm cost », Quote from FD-SOI foundry offering slides shown on Samsung booth, DAC2014
Source: ST
Thermal camera on smartphone
Dual A9 both running at 1.85GHz
Bulk FD-SOI
Apps Proc. Gets Hot | Apps Proc. Stays Cool (High Pwr Cons.)
Co
st
pe
r M
illi
on
Ga
tes (
$)
0.026
0.064
90nm 65nm 40nm 28nm 20nm 16/14nm
Bulk Silicon FD SOI
Wrong trend (Higher integration
= higher cost)
Source: IBS
28
FD
14
FD
3 GHz demo
on ARM-based
Smartphone on 28nm FDSOI
Source: ST
$$$$
+5h web browsing
Bu
lk S
ilic
on
Good trend for FDSOI Moore’s Law
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Conventional silicon technology not suitable anymore
5
Scaling: ”Moore’s law”
Next Technology Gen.:
Application Processor
Next-Gen App. Processor
More functions
n Million transistors 2n Million transistors in same chip size
Moore’s Law :
• For similar chip cost:
– More functionalities (more transistors per chip)
– Less power per transistor
– Faster processing
Planar bulk CMOS reaching its limits at 20nm,
Can’t go further:
– Technical challenges (leakage, variability and short channel effects)
– Cost-efficiency challenges
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Two Scaling Paths for Alternate Device Architecture: Planar FD-SOI or Multi-Gate Transistor
Planar Bulk S D G
Not beyond
20nm
6
Transistor Cross-section
Behavior controlled by doping
Fully Depleted Technologies
FinFET
G D
S
Base Silicon
Buried Oxide
Perspective View
3-D transistor architecture
Revolution
New paradigm : Behavior controlled by silicon geometry
Transistor Cross-section
Planar FD-SOI
Planar transistor architecture
Evolution
G S D
Undopped fully depleted channel
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FD-SOI story: visionary innovations and partnerships
7
FD-SOI processed wafer with multiple raw dice per wafer
FD-SOI transistor
S DG
Smart Cut TM technology
FD-SOI substrates
Silicon die with millions of transistors
2005
Research Institute
2008
Advanced R&D
2010
Industrial Partner
2005
Substrate Supply
2014
Open foundries
2015
Products on the market
…
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Planar FD roadmap: Scalable down to 10nm
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Source: L. Mallier (Leti) at Leti Innovation Days, June 25 2013
Application Benefits 9
Consumer
• Optimized SoC integration (Mixed-signal & RF)
• Energy efficient SoC in all thermal conditions
• Optimized leakage in idle mode
Internet of Things
• Ultra-low voltage operation
• Highly Scalable operation
• Efficient RF and analog integration
Infrastructure Networking
• Energy efficient multicore
• Effective DVFS
• Excellent performance on memories
Automotive
• Well-managed leakage in high temperature
environment
• High reliability thanks to highly-efficient
memories
FD-SOI is excellent for mobile …and many other applications
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Source: ST, SOI Forum, San Francisco Feb 2015
July 8, 2015
Agenda
1. FD-SOI: Background & Value Proposition
2. The FD-SOI ecosystem & markets
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A full FD-SOI ecosystem is now in place
11
May 2014 - Samsung to provide 28nm FD-SOI as open foundry, Press release here May 2014 - Cadence ready to provide 28nm FD-SOI physical IP blocks, Press release here June 2014 - Synopsys to collaborate with Samsung, ST to accelerate 28nm FD-SOI adoption, Press release here June 2015 - GlobalFoundries FD-SOI technology webinar here
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Tools & EDA
Foundries
…
Fabless & Products Substrates
& licensees
Research Technology & IP blocks IP & Design Services
Samsung at SOI Forum in San Francisco, Feb 2015
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PowerPerformanceArea Benchmark (cell level)
* Relative Comparisons
Performance@same leakage
1.64
1.271
1.41
45Bulk 28PSiON 28HKMG 28FD-SOI
1
45Bulk 28PSiON 28HKMG 28FD-SOI
0.640.45
0.70
Power@same speed
10.67
0.61 0.61
45Bulk 28PSiON 28HKMG 28FD-SOI
Chip Area
28FDSOI Low Vdd superiority
0
2
4
6
8
1.0Vop 0.90Vop 0.80Vop 0.63Vop
28FDSOI
28HKMG
28PSiONP
erf
orm
ance
(a.u
.)
Ideal for battery operated ultra low power applications (IoT/wearable)
July 8, 2015
Source: Samsung, SOI Forum, San Francisco Feb2015
GlobalFoundries FD-SOI webinar June 2015
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Source: GF FD-SOI Technology Webinar , June 2015, available here
Examples of wearable application: FD-SOI enables added functionality at ULP for IoT applications
July 8, 2015 14
Sony Next Gen on FD-SOI
1mW
Standard GPS on the
market
x20
20mW
x20 Power Consumption Improvement
On-Chip enabled functionality (RF, logic and SRAM) operating at 0.6V, instead of 1.1V
Source: EETimes, “Sony Joins FDSOI Club”, 30 Jan 2015
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FD-SOI benefits for automotive applications
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Source: ST , SOI Forum, San Francisco, Feb2015
SOI wafer supply ensured
16
300mm SOI starting wafer production sites,
Wordlwide:
Bernin-2, France
Pasir Ris, Singapore
800 Kwfrs/yr capacity,
fully installed, for PD- and FD-SOI. Full conversion to FD in progress.
1 Mwfrs/yr capacity when fully installed
Qualified for FD-SOI. Ready to ramp according to demand in well under a year.
Close to 2 Mwfrs/yr capacity readily available when needed.
Smart Cut licensee
Smart Cut licensee
Soitec ~70% today
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Smart CutTM Alliance – A model for growth
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Agenda
1. FD-SOI: Background & Value Proposition
2. The FD-SOI ecosystem & Markets
3. Soitec’s ultra-thin SOI wafers
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Soitec Fully-Depleted Product Roadmap
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28 nm “28FD”
20/14 nm “14FD”
10 nm “10FD”
7 nm and beyond
FD-3D for FinFET technology
FD-2D
for FDSOI technology
SOI
sSOI
GeOI
III-V.OI
R&D
Fin14 Fin10
Target node
Top Si unif +/- 5A +/- 4A tbd
Box thickness 25nm 20nm 15nm
Top Si stress unstrained unstrained 1.3Gpa tens.
Top Si thickness 12nm 10.5nm tbd
UTBOX25 UTBOX15s UTBOX20
July 8, 2015
Available upon request
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FD-2D Timelines
During Tech. Dev Phase, early samples are available for selected customers
28FD
14FD
10FD
Production
Risk Prod. Production
FD-2D
for FDSOI technology
Sampling Production Tech Dev
2013 2014 2015 2016 2017
July 8, 2015
Simpler process with FD-SOI : Transistor channel pre-defined by substrate
21
Critical dimension: channel thickness
• FD-2D wafers provide excellent control of transistor geometry
To make the best of FD technology
Ultra-Thin Top Silicon Layer
Ultra-Thin Buried Oxide
Base Silicon
S D G
FD-SOI transistor Soitec FD-2D wafer
Enables: Critical dimension: Top Si thickness
• No complex channel doping required • Critical body geometry pre-defined by top silicon • Simplified CMOS process
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Top silicon uniformity: the exceptional made industrial
22
Silicon thickness uniformity is guaranteed to within just a few atomic layers:
Top Si uniformity = +/-5 Å at all points on all wafers, equivalent to +/- 5 mm over 3,000 km (corresponds to ~ +/-0.2 inches over the distance between San Francisco and Chicago)
Soitec FD-2D wafer
Target
+5Å
-5Å
San Francisco - Chicago ~ 2,988 km (1,857 mi)
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Agenda
1. FD-SOI: Background & Value Proposition
2. The FD-SOI ecosystem & Markets
3. Soitec’s ultra-thin SOI wafers
4. Cost Aspects
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IBS’s view on FD-SOI market potential
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Industry Analyst IBS demonstrates FD-SOI competitive advantage
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Relative performance/power
Relative wafer cost
28nm FD-SOI
28nm bulk
20nm bulk
Lower cost Higher cost
worse
better
28nm FD-SOI vs. alternatives
Relative performance/power
Relative wafer cost
20nm FD-SOI
20nm bulk
16nm FinFET
Lower cost Higher cost
worse
better
20nm FD-SOI (14FD) vs. alternatives
• Several studies (IC Knowledge, ST) reach similar conclusions : FD-SOI is extremely cost-competitive vs. any alternative
“ FD-SOI offers best power / performance / cost trade-off for high volume portable applications ” - H Jones, IBS
Use IBS costs
Agenda
1. FD-SOI: Background & Value Proposition
2. The FD-SOI ecosystem & Markets
3. Soitec’s ultra-thin SOI wafers
4. Cost Aspects
5. Take-Aways
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Take-Aways
• 28nm FD-SOI:
outstanding power/performance for the cost of standard 28nm low-power CMOS
• ‘14FD’ / 20nm FD-SOI:
a compelling, cost-effective alternative to FinFET
• Tight wafer specifications are fully met by Soitec in a production environment
• Open foundry offering for FD-SOI at Samsung and GF
• Full ecosystem is in place for high-volume markets
from wafer supply through IP & design environment to foundry manufacturing
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Summary - FD-SOI: confirmed adoption
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A rapidly growing ecosystem and products announcements
Strong competitive advantages
A considerable potential
New products under qualification using FD-SOI
Best Performance/Power/Cost DAC 2014
FD-SOI for COST & POWER SENSITIVE MARKETS: automotive, IoT,
mobile and networking
28nm FD-SOI potential
4.3M 28nm wafers /year
FD-SOI > 25%
28nm bulk
2013 ~2017
“The 28nm technology will represent approximately 4.3 million wafers in 2017 and
FD-SOI could capture at least 25% of the market.” H. Jones, IBS
“There is an opportunity to turn SOI from niche into mainstream.”
Kevin Low, Samsung senior director foundry marketing
“For cost-sensitive markets with more analog integration, FD-SOI is the right solution.”
Jamie Schaeffer, GF product line manager
0.026
0.064
90nm 65nm 40nm 28nm 20nm 16/14nm
Bulk Silicon FD SOI
Negative trend (Higher density = higher costs)
28
FD
14
FD
Bu
lk S
ilic
on
FD-SOI enables following Moore’s law
Cost per Million Gates ($)
Source: IBS Source: SOI Consortium
T h a n k Y o u
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