pwm solenoid/valve driver (rev. b) - texas instruments

DRV102

PWM SOLENOID/VALVE DRIVER

FEATURES HIGH OUTPUT DRIVE: 2.7A WIDE SUPPLY RANGE: +8V to +60V COMPLETE FUNCTION

PWM OutputInternal 24kHz OscillatorDigital Control InputAdjustable Delay and Duty CycleOver/Under Current Indicator

FULLY PROTECTEDThermal Shutdown with IndicatorInternal Current Limit

POWER PACKAGES: 7-Lead TO-220 and7-Lead Surface-Mount DDPAK

APPLICATIONS ELECTROMECHANICAL DRIVERS:

Solenoids PositionersActuators High Power Relays/ContactorsValves Clutches/Brakes

SOLENOID OVERHEAT PROTECTORS FLUID AND GAS FLOW CONTROLLERS PART HANDLERS ELECTRICAL HEATERS/COOLERS MOTOR SPEED CONTROLLERS INDUSTRIAL CONTROL FACTORY AUTOMATION MEDICAL ANALYSIS PHOTOGRAPHIC PROCESSING

DESCRIPTIONThe DRV102 is a high-side power switch employing apulse-width modulated (PWM) output. Its rugged de-sign is optimized for driving electromechanical devicessuch as valves, solenoids, relays, actuators, andpositioners. The DRV102 is also ideal for drivingthermal devices such as heaters and lamps. PWMoperation conserves power and reduces heat rise inthe device, resulting in higher reliability. In addition,adjustable PWM allows fine control of the powerdelivered to the load. Time from dc output to PWMoutput is externally adjustable.

DRV102

DRV102

DelayAdjust

Input

(TTL-Compatible)On

Off

Thermal ShutdownOver/Under Current

Flag

Duty CycleAdjust

Load

DRV102

24kHzOscillator

PWM

2 3

1

7

5(+8V to +60V)

(Gnd electricallyconnected to tab)

Out

6

Gnd(1) 4

VS

Delay

The DRV102 can be set to provide a strong initialclosure, automatically switching to a soft hold mode forpower savings. Duty cycle can be controlled by aresistor, analog voltage, or digital-to-analog converterfor versatility. A flag output indicates thermal shutdownand over/under current limit. A wide supply rangeallows use with a variety of actuators.

The DRV102 is available in a 7-lead staggered TO-220package and a 7-lead surface-mount DDPAK plasticpower package. It operates from –55°C to +125°C.

SBVS009B – JANUARY 1998 – REVISED MAY 2009

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PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Copyright © 1998-2009, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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DRV1022SBVS009Bwww.ti.com

SPECIFICATIONSAt TC = +25°C, VS = +24V, load = series diode MUR415 and 100Ω, and 4.99kΩ Flag pull-up to +5V, unless otherwise noted.

DRV102T, F

PARAMETER CONDITIONS MIN TYP MAX UNITS

OUTPUTOutput Saturation Voltage, Source IO = 1A +1.7 +2.2 V

IO = 0.1A +1.3 +1.7 VCurrent Limit 2 2.7 3.4 AUnder-Scale Current 16 mALeakage Current Output Transistor Off, VS = +60V, VO = 0V ±0.01 ±2 mA

DIGITAL CONTROL INPUT(1)

VCTR Low (output disabled) 0 +1.2 VVCTR High (output enabled) +2.2 VS VICTR Low (output disabled) VCTR = 0V –80(2) µAICTR High (output enabled) VCTR = +5V 20(2) µAPropagation Delay: On-to-Off 0.9 µs

Off-to-On 1.8 µs

DELAY TO PWM(3) dc to PWM ModeDelay Equation(4) Delay to PWM ≈ CD • 106 (CD in F) sDelay Time CD = 0.1µF 80 97 110 msMinimum Delay Time(5) CD = 0 15 µs

DUTY CYCLE ADJUSTDuty Cycle Range 10 to 90 %Duty Cycle Accuracy 49% Duty Cycle, RPWM = 25.5kΩ ±1 ±7 %

vs Supply Voltage 49% Duty Cycle, VS = 8V to 60V ±1 ±5 %Nonlinearity(6) 20% to 80% Duty Cycle ±2 % FSR

DYNAMIC RESPONSEOutput Voltage Rise Time VO = 10% to 90% of VS 0.25 2.5 µsOutput Voltage Fall Time VO = 90% to 10% of VS 0.25 2.5 µsOscillator Frequency 19 24 29 kHz

FLAGNormal Operation 20kΩ Pull-Up to +5V, IO < 1.5A +4 +4.9 VFault(7) Sinking 1mA +0.2 +0.4 VSink Current VFLAG = 0.4V 2 mAUnder-Current Flag: Set 5.2 µs

Reset 11 µsOver-Current Flag: Set 5.2 µs

Reset 11.5 µs

THERMAL SHUTDOWNJunction Temperature

Shutdown +165 °CReset from Shutdown +150 °C

POWER SUPPLYSpecified Operating Voltage +24 VOperating Voltage Range +8 +60 VQuiescent Current IO = 0 6.5 9 mA

TEMPERATURE RANGESpecified Range –55 +125 °CStorage Range –55 +125 °CThermal Resistance, θJC

7-Lead DDPAK, 7-Lead TO-220 3 °C/WThermal Resistance, θJA

7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 °C/W

NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-widthmodulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay.(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature,over-current, or under-current conditions.

DRV102 3SBVS009B www.ti.com

CONNECTION DIAGRAMS

Top Front View TO-220, DDPAK Supply Voltage, VS .............................................................................. 60VInput Voltage .......................................................................... –0.2V to VS

PWM Adjust Input ................................................ –0.2V to VS (24V max)Delay Adjust Input ................................................ –0.2V to VS (24V max)Operating Temperature Range ...................................... –55°C to +125°CStorage Temperature Range .........................................–55°C to +125°CJunction Temperature .................................................................... +150°CLead Temperature (soldering, 10s)(2) ........................................... +300°C

NOTES: (1) Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may de-grade device reliability. (2) Vapor-phase or IR reflow techniques are recom-mended for soldering the DRV102F surface-mount package. Wave solderingis not recommended due to excessive thermal shock and “shadowing” ofnearby devices.

ABSOLUTE MAXIMUM RATINGS(1)

ELECTROSTATICDISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instrumentsrecommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling andinstallation procedures can cause damage.

ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changescould cause the device not to meet its published specifications.

7-LeadStagger-Formed

TO-220

NOTE: Tabs are electrically connected to ground (pin 4).

1 2 3 4 5 6 7

7-LeadDDPAK

Surface-Mount

PWM

PWM

Gnd Out

VS

Delay

In

1 2 3 4 5 6

Flag

Gnd Out

VS

Delay

In Flag

7

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.


PIN # NAME DESCRIPTION

Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven abovethe typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level risesto 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be driven to the power supply (VS)without damage.

Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating resultsin a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to lessthan 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator.When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),so the first pulse may be extended by any portion of the programmed duty cycle.

Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source(PWM) from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,

or output of a D/A converter. The active voltage range is from 0.55V to 3.7V to facilitate the use of single-supply controlelectronics. At 0.56V (or RPWM = 4.4kΩ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWMfrequency is a constant 24kHz.

Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV102 to function. Itcarries the 6.5mA quiescent current.

Pin 5 VS This is the power supply pin. Operating range is +8V to +60V.

Pin 6 Out The output is the emitter of a power npn with the collector connected to VS. Low power dissipation in the DRV102 is obtainedby low saturation voltage and fast switching transitions. Rise time is less than 250ns, fall time depends on load impedance.A flyback diode is (D1) needed with inductive loads to conduct the load current during the off cycle. The external diode shouldbe selected for low forward voltage. The internal clamp diode provides protection but should not be used to conduct loadcurrents. An additional diode (D2), located in series with Out pin, is required for inductive loads.

Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under-current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermalshutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its outputrequires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.

PIN DESCRIPTIONS

LOGIC BLOCK DIAGRAM

CD RPWM

Input

On

Off

Over/Under CurrentDRV102

Flag

ThermalShutdown

PWM

2 3

(2)

1

7

Delay

Load

NOTES: (1) Schottky Power Rectifier for lowpower dissipation. (2) Schottky or appropriatelyrated silicon diode.

(+8V to +60V)

Gnd 4

Out

6

D2

D1(1)

VS

5


TYPICAL PERFORMANCE CURVESAt TC = +25°C and VS = +24V, unless otherwise noted.

OUTPUT SATURATION VOLTAGE vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Sat

urat

ion

Vol

tage

(V

)

2.25

2

1.75

1.5

1.25

1

0.75

IO = 2A

IO = 1.5A

IO = 1A

IO = 0.1A

QUIESCENT CURRENT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Qui

esce

nt C

urre

nt (

mA

)

8

7.5

7

6.5

6

5.5

VS = +60V

VS = +8V

VS = +24V

DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VPWM (V)

Dut

y C

ycle

(%

)

Dut

y C

ycle

Err

or (

%)

90

80

70

60

50

40

30

20

10

8

6

4

2

0

–2

–4

–6

–8

Duty Cycle

Error

IO = 0.1A

IO = 1A

IO = 0.1A to 1A

DUTY CYCLE vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Dut

y C

ycle

(%

)

54

53

52

51

50

49

48

VS = +8V

RPWM = 25.5kΩ

VS = +24V

VS = +60V

CURRENT LIMIT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Cur

rent

Lim

it (m

A)

3.25

3

2.75

2.5

2.25

2

VS = +60V, Load = 5Ω



UNDER-SCALE CURRENT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Und

er-S

cale

Cur

rent

(m

A)

20

18

16

14

12

10

VS = +8V to +60V


TYPICAL PERFORMANCE CURVES (CONT)At TC = +25°C and VS = +24V, unless otherwise noted.

VO

UT

FLAG OPERATIONOVER-CURRENT LIMIT

(VS = +60V, CD = 220pF, RPWM = 25.5kΩ, Load = 350mH || 47Ω)

FLAG OPERATIONUNDER-CURRENT

(VS = +60V, CD = 120pF, RPWM = 25.5kΩ, No Load)

1A

0.5A

0

VO

UT

DC TO PWM MODEDRIVING INDUCTIVE LOAD

(VS = +60V, CD = 120pF, RPWM = 30.1kΩ, Load = 350mH)TYPICAL SOLENOID CURRENT WAVEFORM

(VS = +60V, CD = 0.1µF, RPWM = 30.1kΩ, Load = 350mH)

50µs/div

Inductive load ramp current

50µs/div

60V

40V

20V

0

I SU

PP

LY

PWM ModeConstant Output

Flag only on during constant outputor “ ON” portion of PWM mode

4V

2V

0

60V

40V

20V

0

VIN

VF

LAG

50µs/div

4V

25ms/div

PWM Mode

60V

40V

20V

0

4V

2V

0

VF

LAG

Onset of current limit whereVOUT begins to drop

Flag only set duringconstant output mode

or “ ON” portion ofPWM mode

Solenoid Closure

SolenoidMotionPeriod

VIN

Sol

enoi

d C

urre

nt

0

1A

0.5A

0

10µs/div

CURRENT LIMIT REPSONSE(Load = 1Ω, 2kΩ pull-up to +5V on Flag pin) OSCILLATOR FREQUENCY vs TEMPERATURE

–75 –55 –35 –15 5 25 45 65 85 105 125

Temperature (°C)

Osc

illat

or F

requ

ency

(kH

z)

24.2

24.0

23.8

23.6

23.4

VS = +8V

VS = +60V

3A

2A

1A

0

VF

LAG 5V

2.5V

0

I OU

T


TYPICAL PERFORMANCE CURVES (CONT)At TC = +25°C and VS = +24V, unless otherwise noted.

OUTPUT LEAKAGE CURRENT vs TEMPERATURE

–75 –55 –35 –15 5 25 45 65 85 105 125

Temperature (°C)

Leak

age

Cur

rent

(µA

)

–200

–175

–150

–125

–100

–75

Output Transistor OffVO = 0V

VS = +60V

VS = +8V

VS = +24V

NOMINAL DELAY TIME TO PWM vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Del

ay (

ms)

103

101

99

97

95

93

91

CD = 0.1µFVS = +8V

VS = +24V

VS = +60V

CURRENT LIMITPRODUCTION DISTRIBUTION

Per

cent

of U

nits

(%

)

Current Limit (A)

40

35

30

25

20

15

10

5

0

Typical distributionof packaged units.

DRV102F andDRV102T included.

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4

DELAY TIME TO PWMPRODUCTION DISTRIBUTION

Per

cent

of U

nits

(%

)

Delay Time to PWM (ms)

60

50

40

30

20

10

0



CD = 0.1µF

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110

DUTY CYCLE ACCURACYPRODUCTION DISTRIBUTION

Per

cent

of U

nits

(%

)

Duty Cycle Accuracy (%)

30

25

20

15

10

5

0



Nominal Duty Cycle = 49%RPWM = 25.5kΩ

–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7


BASIC OPERATIONThe DRV102 is a high-side, bipolar power switch employ-ing a pulse-width modulated (PWM) output for drivingelectromechanical and thermal devices. Its design is opti-mized for two types of applications: a two-state driver(open/close) for loads such as solenoids and actuators, anda linear driver for valves, positioners, heaters, and lamps. Itswide supply range, adjustable delay to PWM mode, andadjustable duty cycle make it suitable for a wide range ofapplications. Figure 1 shows the basic circuit connections tooperate the DRV102. A 0.1µF bypass capacitor is shownconnected to the power supply pin.

The Input (pin 1) is compatible with standard TTL levels.Input voltages between +2.2V and +5.5V turn the deviceoutput on, while pulling the pin low (0V to +1.2V), shuts theDRV102 output off. Input current is typically 80µA.

Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allowexternal adjustment of the PWM output signal. The DelayAdjust pin can be left floating for minimum delay to PWMmode (typically 15µs) or a capacitor can be used to set thedelay time. Duty cycle of the PWM output can be controlledby a resistor, analog voltage, or D/A converter. Figure 1bprovides an example timing diagram with the Delay Adjust

FIGURE 1. Basic Circuit Connections and Timing Diagram.

pin connected to 0.1µF and duty cycle set for 25%. See the“Delay Adjust” and “Duty Cycle Adjust” text for equationsand further explanation.

Ground (pin 4) is electrically connected to the package tab.This pin must be connected to system ground for theDRV102 to function. This serves as the DRV102 referenceground.

The load (solenoid, valve, etc.) is connected between theoutput (pin 6) and ground. For an inductive load, an externalflyback diode (D1 in Figure 1a) across the output is required.The diode serves to maintain the hold force during PWMoperation. Depending on the application, the flyback diodeshould be placed near the DRV102 or close to the solenoid(see “Flyback Diode” text). The device’s internal clampdiode, connected between the output and ground, should notbe used to carry load current. When driving inductive loads,an additional diode in series with the out pin, D2, is required(see “Series Diode” text).

The Flag (pin 7) provides fault status for under-current,over-current, and thermal shutdown conditions. This pin isactive low with pin voltage typically +0.2V during a faultcondition. A small value capacitor may be needed betweenFlag and ground for noisy applications.

RPWMCD

DelayAdjust

Input(TTL-Compatible)

On

Off


Flag

DRV102

Load

DutyCycleAdjust

VS

24kHzOscillator

PWM

2 3

1

7

6

Out

5

VS

4Gnd (Gnd electricallyconnected to tab)

Delay

tP

tON

OUTPUT

VS

0

INPUT+2.2V to +5.5V

0V to +1.2V

Duty Cycle = = 25%tONtP

RPWM = 90.9kΩtON ≈ 10.4µs

tP ≈ 41.6µs (1/24kHz)

1a). Basic Circuit Connections

CD = 0.1µF (92ms constant dc output before PWM)RPWM = 90.9kΩ

1b). Simplified Timing Diagram

(1)D1

D2

CD = 0.1µF92ms • • •

• • •

Initial dc Output(set by value

of CD)

PWM Mode(resistor or voltage

controlled)

NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle. Flyback diode shown near DRV102. For some applications with remotely located load, it may be desirable to place the diode near the solenoid—see “Flyback Diode” text. Motorola MSRS1100T3 (1A, 100V) or MBRS360T3 (3A, 60V).

0.1µF

(+8V to +60V)


CONSTANT OUTPUT DURATION(Delay Time to PWM Mode) CD

3µs Pin Connected to 5V15µs Pin Open97µs 100pF

0.97ms 1nF97ms 0.1µF

APPLICATIONS INFORMATIONPOWER SUPPLY

The DRV102 operates from a single +8V to +60V supplywith excellent performance. Most behavior remains un-changed throughout the full operating voltage range. Param-eters which vary significantly with operating voltage areshown in the Typical Performance Curves.

CONNECTIONS TO LOAD

The PWM switching voltage and currents can cause electro-magnetic radiation. Proper physical layout of the load cur-rent will help minimize radiation. Load current flows fromthe DRV102 output terminal to the load and returns throughthe ground return path. This current path forms a loop. Tominimize radiation, make the area of the enclosed loop assmall as possible. Twisted pair leading to the load is excel-lent. If the ground return current must flow through a chassisground, route the output current line directly over the chassissurface in the most direct path to the load.

FLYBACK DIODE LOCATION

Physical location of the flyback diode may affect electro-magnetic radiation. With most solenoid loads, inductance islarge enough that load current is virtually constant duringPWM operation. When the switching transistor is off, loadcurrent flows though the flyback diode. If the flyback diodeis located near the DRV102 (Figure 2a), the current flowingin long lines to the load is virtually constant. If the flybackdiode is, instead, located directly across the load (Figure 2b),pulses of current must flow from the DRV102 to the distantload. While theory seems to favor placing the diode at theDRV102 output (constant current in the long lines), indi-

TABLE I. Delay Adjust Pin Connections.

vidual situations may defy logic; if one location seems tocreate noise problems, try the other.

SERIES DIODE FOR INDUCTIVE LOADS

An additional bias diode, located in series with the output, isrequired when driving inductive loads. Any silicon diode,such as the 1N4002, appropriately rated for current willwork. The diode biases the emitter of the internal powerdevice such that it can be fully shut off during the “off”portion of the PWM cycle. Note that the voltage at the loaddrops below ground due to the flyback diode. If it is not used,apparent leakage current can rise to hundreds of milliamps,resulting in unpredictable operation and thermal shutdown.

ADJUSTABLE INITIAL 100% DUTY CYCLE

A unique feature of the DRV102 is its ability to provide aninitial constant dc output (100% duty cycle) and then switchto PWM mode to save power. This function is particularlyuseful when driving solenoids which have a much higherpull-in current requirement than hold current requirement.

The duration of this constant dc output (before PWM outputbegins) can be externally and independently controlled witha capacitor connected from Delay Adjust (pin 2) to groundaccording to the following equation:

Delay Time ≈ CD • 106

(time in seconds, CD in Farads)

Leaving the Delay Adjust pin open results in a constantoutput time of approximately 15µs. The duration of thisinitial output can be reduced to less than 3µs by connectingthe pin to 5V. Table I provides examples of desired “delay”times (constant output before PWM mode) and the appropri-ate capacitor values or pin connection.

FIGURE 2. Location of External Flyback Diode.

The internal Delay Adjust circuitry is composed of a 3µAcurrent source and a 3V comparator as shown in Figure 3.Thus, when the pin voltage is less than 3V, the output deviceis 100% on (dc output mode).

FIGURE 3. Simplified Circuit Model of the Delay Adjust Pin.

DRV102

Load

VS

6Out

5

4

2a) Flyback Diode Near DRV102

DRV102

Load

VS

6Out

5

4

2b) Flyback Diode Near Load

3µA

2

CD

VS3V Reference

Comparator

Delay Adjust

DRV102


FIGURE 6. Simplified Circuit Model of the Duty CycleAdjust Pin.

FIGURE 5. Using a Voltage Source to Program Duty Cycle.

DRV102

D/AConverter(or analogvoltage)1kΩ(1)

PWM

VPWM 3 Gnd 4

6

5VS

Out

NOTE: (1) Required if voltage source can go below 0.1V.

200µA

3

VS

Comparator

Duty CycleAdjust

DRV102

19kΩ

Resistor orVoltage Source(1)

NOTE: (1) Do not drive pin below 0.1V.

3.8V

0.7V

f = 24kHz

ADJUSTABLE DUTY CYCLE

The DRV102’s externally adjustable duty cycle provides anaccurate means of controlling power delivered to the load.Duty cycle can be set from 10% to 90% with an externalresistor, analog voltage, or the output of a D/A converter.Reduced duty cycle results in reduced power dissipation.This keeps the DRV102 and load cooler, resulting in in-creased reliability for both devices. PWM frequency is aconstant 24kHz.

Resistor-Controlled Duty Cycle

Duty cycle is independently programmed with a resistor(RPWM) connected between the Duty Cycle Adjust pin andground. Increased resistor values correspond to decreasedduty cycles. Table II provides resistor values for typical dutycycles. Resistor values for additional duty cycles can beobtained from Figure 4. For reference purposes, the equationfor calculating RPWM is included in Figure 4.

FIGURE 4. RPWM versus Duty Cycle.

RESISTOR(1) VOLTAGE(2)

DUTY CYCLE RPWM (kΩ) VPWM (V)

10 536 3.6720 137 3.3130 66.5 2.9140 39.2 2.4950 24.9 2.0760 16.2 1.6670 10.5 1.2680 6.65 0.8890 4.42 0.56

NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do notdrive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typicalperformance curve.

TABLE II. Duty Cycle Adjust. TA= +25°C, VS = +24V.

Voltage-Controlled Duty Cycle

Duty cycle can also be programmed with an analog voltage,VPWM. With VPWM ≈ 0.5V, duty cycle is 100%. Increasingthis voltage results in decreased duty cycles. For 0% dutycycle, VPWM is approximately 4V. Table II provides VPWMvalues for typical duty cycles. See the “Duty Cycle vsVoltage” typical performance curve for additional duty cyclevalues.

The Duty Cycle Adjust pin should not be driven below 0.1V.If the voltage source used can go between 0.1V and ground,a 1kΩ series resistor between the voltage source and the DutyCycle Adjust pin (Figure 5) is required to limit swing. If thepin is driven below 0.1V, the output will be unpredictable.

The DRV102’s internal 24kHz oscillator sets the PWMperiod. This frequency is not externally adjustable. DutyCycle Adjust (pin 3) is internally driven by a 200µA currentsource and connects to the input of a comparator and a 19kΩresistor as shown in Figure 6. The DRV102’s PWM controldesign is inherently monotonic. That is, a decreased voltage(or resistor value) always produces an increased duty cycle.

10 20 40 60 10080

Duty Cycle (%)

RP

WM

(kΩ

)

1000

100

10

1

RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]–1

where: a = –4.9686 x 10–8

b = –5.9717 x 10–8

c = 2.9889 x 10–8

d = –5.4837 x 10–10

e = 5.9361 x 10–12

RPWM = [–4.9686 x 10–8 + (–5.9717 x 10–8) (50) + (2.9889 x 10–8) (50)2

+ (–5.4837 x 10–10) (50)3 + (5.9361 x 10–12) (50)4]–1

DC = duty cycle in %

For 50% duty cycle:

= 24.9kΩ


STATUS FLAG

Flag (pin 7) provides fault indication for under-current,over-current, and thermal shutdown conditions. During afault condition, Flag output is driven low (pin voltagetypically drops to 0.2V). A pull-up resistor, as shown inFigure 7, is required to interface with standard logic. A smallvalue capacitor may be needed between Flag and ground innoisy applications.

Figure 7 gives an example of a non-latching fault monitoringcircuit, while Figure 8 provides a latching version. The Flagpin can sink several milliamps, sufficient to drive externallogic circuitry or an LED (Figure 9) to indicate when a faulthas occurred. In addition, the Flag pin can be used to turn offother DRV102’s in a system for chain fault protection.

Over/Under Current Fault

An over-current fault occurs when the output current ex-ceeds the current limit. All units are guaranteed to drive 2Awithout current limiting. Typically, units will limit at 2.7A.The status flag is not latched. Since current during PWMmode is switched on and off, the flag output will be modu-lated with PWM timing (see flag waveforms in the TypicalPerformance Curves).

An under-current fault occurs when the output current isbelow the under-scale current threshold (typically 16mA).For example, this function indicates when the load is discon-nected. Again, the flag output is not latched, so an under-current condition during PWM mode will produce a flagoutput that is modulated by the PWM waveform. An initial,brief under-current flag normally appears driving inductiveloads and may be avoided by adding a parallel resistorsufficient to move the initial current above the under-currentthreshold. Avoid adding capacitance to pin 6 (Out) as it maycause momentary current limiting.

Over-Temperature Fault

A thermal fault occurs when the die reaches approximately165°C, producing a similar effect as pulling the input low.Internal shutdown circuitry disables the output and resets theDelay Adjust pin. The Flag is latched in the low state (faultcondition) until the die has cooled to approximately 150°C.A thermal fault can occur in any mode of operation. Recov-ery from thermal fault will start in delay mode (constant dcoutput).

FIGURE 8. Latching Fault Monitoring Circuit.

FIGURE 7. Non-Latching Fault Monitoring Circuit.

DRV102


6

5

7

VS

Out

4Gnd

5kΩPull-Up

+5V

Flag

TTL or HCT

DRV102


5

7

6

20kΩ

+5V

Flag

Q

Q

CLR

Flag

Flag

Flag Reset

J

CLK

GND K

VS

74XX76A

(1)

NOTE: (1) Small capacitor (10pF) may be required in noisy environments.

4Gnd

VS

Out

FIGURE 9. LED to Indicate Fault Condition.

DRV102


7

5kΩ

+5V

Flag

(LED)HLMP-Q156

5

6

4Gnd

VS

Out


FIGURE 11. TO-220 Thermal Resistance versus Aluminum Plate Area.

For best thermal performance, the tab of the DDPAK sur-face-mount version should be soldered directly to a circuitboard copper area. Increasing the copper area improves heatdissipation. Figure 12 shows typical thermal resistance fromjunction-to-ambient as a function of the copper area.

POWER DISSIPATION

Power dissipation depends on power supply, signal, and loadconditions. Power dissipation is equal to the product of

FIGURE 10. TO-220 and DDPAK Solder Footprints.

PACKAGE MOUNTING

Figure 10 provides recommended PCB layouts for both theTO-220 and DDPAK power packages. The tab of bothpackages is electrically connected to ground (pin 4). It maybe desirable to isolate the tab of TO-220 package from itsmounting surface with a mica (or other film) insulator (seeFigure 11). For lowest overall thermal resistance, it is best toisolate the entire heat sink/DRV102 structure from themounting surface rather than to use an insulator between thesemiconductor and heat sink.

7-Lead DDPAK(1)

KTW Package(2)7-Lead TO-220KVT Package(2)

0.33

5

0.15

0.05

0.45

0.51

0.1050.05

0.035

0.04

0.2

0.08

5

Mean dimensions given in inches. Refer to the end of this data sheet for tolerances and detailed package drawings. For further information on solder pads for surface-mount devices, consult Application Bulletin AB-132 (SBFA015), available for download at www.ti.com.

For improved thermal performance increase footprint area.See Figure 11, Thermal Resistance vs Circuit Board Copper Area.Refer to the mechanical drawings at the end of this document.

NOTES:(1)

(2)

0 1 2 3 4 5 6 7 8

18

16

14

12

10

8

The

rmal

Res

ista

nce

JA (

°C/W

)

Aluminum Plate Area (inches2)

THERMAL RESISTANCEvs ALUMINUM PLATE AREA

Aluminum Plate Area

Flat, RectangularAluminum Plate

DRV102TO-220 Package

θ

0.030

0.062

0.050

Vertically Mountedin Free Air

Optional mica or film insulatorfor electrical isolation. Addsapproximately 1°C/W.

Aluminum PlateThickness (inches)


low as possible for increased reliability. Junction tempera-ture can be determined according to the equation:

TJ = TA + PDθJA (1)

where, θJA = θJC + θCH + θHA (2)

TJ = Junction Temperature (°C)

TA = Ambient Temperature (°C)PD = Power Dissipated (W)

θJC = Junction-to-Case Thermal Resistance (°C/W)

θCH = Case-to-Heat Sink Thermal Resistance (°C/W)θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)

θJA = Junction-to-Air Thermal Resistance (°C/W)

Figure 13 shows maximum power dissipation versus ambi-ent temperature with and without the use of a heat sink.Using a heat sink significantly increases the maximumpower dissipation at a given ambient temperature as shown.

FIGURE 12. DDPAK Thermal Resistance versus Circuit Board Copper Area.

THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA

50

40

30

20

10

0

The

rmal

Res

ista

nce,

θJA

(°C

/W)

0 1 2 3 4 5

Copper Area (inches2)

DRV102DDPAK

Surface-Mount Package1oz. copper

Circuit Board Copper Area

DRV102DDPAK

Surface-Mount Package

output current times the voltage across the conducting out-put transistor times the duty cycle. Power dissipation can beminimized by using the lowest possible duty cycle necessaryto assure the required hold force.

THERMAL PROTECTION

Power dissipated in the DRV102 will cause the junctiontemperature to rise. The DRV102 has thermal shutdowncircuitry that protects the device from damage. The thermalprotection circuitry disables the output when the junctiontemperature reaches approximately +165°C, allowing the de-vice to cool. When the junction temperature cools to approxi-mately +150°C, the output circuitry is again enabled. Depend-ing on load and signal conditions, the thermal protectioncircuit may cycle on and off. This limits the dissipation of thedriver but may have an undesirable effect on the load.

Any tendency to activate the thermal protection circuitindicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should belimited to +125°C, maximum. To estimate the margin ofsafety in a complete design (including heat sink), increasethe ambient temperature until the thermal protection istriggered. Use worst-case load and signal conditions. Forgood reliability, thermal protection should trigger more than40°C above the maximum expected ambient condition ofyour application. This produces a junction temperature of125°C at the maximum expected ambient condition.

The internal protection circuitry of the DRV102 was designedto protect against overload conditions. It was not intended toreplace proper heat sinking. Continuously running theDRV102 into thermal shutdown will degrade reliability.

HEAT SINKING

Most applications will not require a heat sink to assure thatthe maximum operating junction temperature (125°C) is notexceeded. However, junction temperature should be kept as

FIGURE 13. Maximum Power Dissipation versus AmbientTemperature.

10

8

6

4

2

0

Pow

er D

issi

patio

n (W

atts

)

0 25 50 75 100 125

Ambient Temperature (°C)

MAXIMUM POWER DISSIPATIONvs AMBIENT TEMPERATURE

TO-220 with Thermalloy6030B Heat Sink JA = 16.5°C/W

PD = (TJ (max) – TA) / JATJ (max) = 125°C

With infinite heat sink( JA = 3°C/W),max PD = 33Wat TA = 25°C

θ

θ

DDPAK

JA = 26°C/W (3 in2 1 oz.copper mounting pad)

θ

DDPAK or TO-220

JA = 65°C/W (no heat sink)θ

θ


The difficulty in selecting the heat sink required lies indetermining the power dissipated by the DRV102. For dcoutput into a purely resistive load, power dissipation is simplythe load current times the voltage developed across theconducting output transistor times the duty cycle. Other loadsare not as simple. Once power dissipation for an applicationis known, the proper heat sink can be selected.

Heat Sink Selection Example

A TO-220 package’s maximum dissipation is 2 Watts. Themaximum expected ambient temperature is 80°C. Find theproper heat sink to keep the junction temperature below125°C.

Combining Equations 1 and 2 gives:

TJ = TA + PD(θJC + θCH + θHA) (3)

TJ, TA, and PD are given. θJC is provided in the Specifica-tions table, 3°C/W. θCH can be obtained from the heat sinkmanufacturer. Its value depends on heat sink size, area, andmaterial used. Semiconductor package type, mounting screwtorque, insulating material used (if any), and thermaljoint compound used (if any) also affect θCH. A typical θCHfor a TO-220 mounted package is 1°C/W. Now we can solvefor θHA:

(4)

To maintain junction temperature below 125°C, the heatsink selected must have a θHA less than 18.5°C/W. In otherwords, the heat sink temperature rise above ambient must beless than 37°C (18.5°C/W • 2W). For example, at 2 WattsThermalloy model number 6030B has a heat sinktemperature rise of about 33°C above ambient, which isbelow the 37°C required in this example. Figure 13 showspower dissipation versus ambient temperature for a TO-220package with a 6030B heat sink.

Another variable to consider is natural convection versusforced convection air flow. Forced-air cooling by a small fancan lower θCA (θCH + θHA) dramatically. Heat sink manufac-turers provide thermal data for both of these cases. Foradditional information on determining heat sink require-ments, consult Application Bulletin AB-038.

As mentioned earlier, once a heat sink has been selected, thecomplete design should be tested under worst-case load andsignal conditions to ensure proper thermal protection.

θ θ θ

θ

HAJ A

DJC CH

HA

T T

P= +( )

= ° ° ° + °( ) = °

––

125 C – 80 C

2W– 3 C/W 1 C/W 18.5 C/W


APPLICATION CIRCUITS

FIGURE 14. Fluid Flow Control System.

FIGURE 15. Instrument Light Dimmer Circuit. FIGURE 16. 4-20mA Input to PWM Output.

DRV102

Duty Cycle Adjust

Input(On/Off)

Twisted Pair

5

6

VS

Out

1

3 4

4-20mA

NOTE: (1) Rectifier diode required for inductiveloads to conduct load current during the off cycle.

100Ω

187Ω

Coil(1)2

DelayAdjust

DRV102


24kHzOscillator

PWM

Delay

TTL Control Input

Off

On

Flexible Tube

Plunger

Pinch Valve

Solenoid Coil

VS

5

Out

6

7

2

1

CD RPWM

3 4 Gnd

Flag

DelayAdjust

Duty CycleAdjust(1)

(10% to 90%)

Can drive most typesof solenoid-actuatedvalves and actuators

NOTE: (1) Duty cycle can be programmed bya resistor, analog voltage, or D/A converter.

Do not drive below 0.1V.

Microprocessor

+5V

5kΩ

VS

DRV102

Lamp

Cadmium SulfideOptical Detector

(Clairex CL70SHLor CLSP5M)

Aimed atambient

light

On/Off

λ

Brighter light results inincreased duty cycle

1

3 42

DelayAdjust

10kΩ

VS

5

Out

6


FIGURE 17. Improved Switching Time When Driving Multiple Loads.

DRV102

1

3 4

RPWM150kΩ

CD0.047µF

5+40V (max for TPIC6273)

(25% Duty Cycle)

Reduced mechanical actuation delay with high voltage pull-in followed by low duty cycle

VS

6

Out

2

On/Off

Full power pulse width is controlplus interval set by CD.

4

20

+5V

10

5 6

TI TPIC6273(Octal Power Switch)

TTL/CMOS Solenoid Selection Inputs

7 14 15 16 17

74LS05

Control

11

2 3 8 9 12 13 18 19

• • •• • •


FIGURE 18. (a) Constant Temperature Controller. (b) Improved Accuracy Constant Temperature Controller.

On/Off

Thermistor

DRV102

REF200

VS

HeatingElement

Duty CycleAdjust

1

DelayAdjust

2

Gnd43

5

6

Out

1 2

0.1µF

2µF Film

72

3

4

6

100µA 100µA

1kΩ

10kΩ

10MΩ

OPA134

IN4148(1)

orThermistor

5kΩ at +25°C

20kΩ

4.7V

Integrator improves accuracy

NOTE: (1) Or any common silicon diode suitedto the mechanical mounting requirements.

TemperatureControl

Higher temperature resultsin lower duty cycle.

Higher temperature resultsin lower duty cycle.

7, 8

R1

R2

0.1µF

On/Off

DRV102

HeatingElement

DutyCycleAdjust

a)

b)

1

DelayAdjust

2

Gnd43

5

VS

VS

6

Out

10µF


FIGURE 19. Constant Speed Motor Control.

FIGURE 20. DC Motor Speed Control Using AC Tachometer.

One-Shot

–15V

5nFNP0

VFC32

0V to +10V

1kΩ

40kΩ

DRV102

2 3

5

6

1

100kΩ

470kΩ

Frequency In

22kΩ

47kΩ10kΩ

M

TAC

Tachometer

Coupled to Motor

+15V

+15V

0.5µF

1nF

2N2222

Speed Control Input

VOUT

Delay Adjust

Open circuit willprovide 3.4V“on” signal

4

+40V

DRV102

dc TachometerCoupled to Motor

T

R1 R2

3 4

Speed Control(1)

M

NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.

Input(On/Off)

1

5+12V

6

Out

2

DelayAdjust


FIGURE 22. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.

FIGURE 23. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.

FIGURE 21. Constant Current Output Drive.

DRV102

1

3 4

R2

VS = +8V to +60V

R1

R34.87kΩ

R44.87kΩ

C120µF

+

4.3VDIN5229

Duty Cycle Adjustafter soft start

Select R1 and R2 to dividedown VS to 5.5V max.

For example: with VS = 60VR1 = 11kΩ, R2 = 1kΩ

VIN = • 60V = 5V

Sets start-upduty cycle

1kΩ1kΩ + 11kΩ

5VS

6

Out

2

Delay Adjust

DRV102Phase 3StepperLogic In

6

5VS


6

5VS


6

5

Motor

Only one DRV102 isturned on at sequence time.

VS

+24V

On

Off

Duty CycleAdjust

DelayAdjust

VZ

Load

RSHUNT0.1Ω

DRV102

32

1

5

Current Set

0.6V gives ~ 90% Duty Cycle3.7V gives ~ 10% Duty Cycle

Out

6

4

VS

VZ

2kΩ

100kΩ

25kΩ5.1VZener

1kΩ

100kΩ

5kΩ

OPA237

0.1µF

0.1µF


Revision History

DATE REVISION PAGE SECTION DESCRIPTION

1 Front Page Updated front page appearance.

12 Package Mounting Changed Figure 10 to show TI package designator.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

5/09 B

PACKAGE OPTION ADDENDUM

www.ti.com 10-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

DRV102F OBSOLETE DDPAK/TO-263

KTW 7 TBD Call TI Call TI

DRV102F/500 ACTIVE DDPAK/TO-263

KTW 7 500 Green (RoHS& no Sb/Br)

CU SN Level-2-260C-1 YEAR DRV102F

DRV102FKTWT ACTIVE DDPAK/TO-263


CU SN Level-3-245C-168 HR DRV102F

DRV102FKTWTG3 ACTIVE DDPAK/TO-263


CU SN Level-3-245C-168 HR DRV102F

DRV102T ACTIVE TO-220 KVT 7 50 Green (RoHS& no Sb/Br)

CU SN N / A for Pkg Type DRV102T

DRV102TG3 ACTIVE TO-220 KVT 7 50 Green (RoHS& no Sb/Br)

CU SN N / A for Pkg Type DRV102T

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

http://www.ti.com/product/DRV102?CMP=conv-poasamples#samplebuy





http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 10-Apr-2013

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DRV102F/500 DDPAK/TO-263

KTW 7 500 330.0 24.4 10.95 16.5 5.15 16.0 24.0 Q2

DRV102FKTWT DDPAK/TO-263

KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Dec-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV102F/500 DDPAK/TO-263 KTW 7 500 346.0 346.0 41.0

DRV102FKTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Dec-2015

Pack Materials-Page 2

MECHANICAL DATA

MPSF015 – AUGUST 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.010 (0,25) A M

4201284/A 08/01

0.385 (9,78)0.410 (10,41)

M MB C

–A–0.006

–B–

0.170 (4,32)

0.183 (4,65)

0.000 (0,00)

0.012 (0,305)

0.104 (2,64)0.096 (2,44)

0.034 (0,86)0.022 (0,57)

0.050 (1,27)

0.055 (1,40)

0.045 (1,14)

0.014 (0,36)0.026 (0,66)

0.330 (8,38)

0.370 (9,40)

0.297 (7,54)0.303 (7,70)

0.0585 (1,485)

0.0625 (1,587)

0.595 (15,11)

0.605 (15,37)

0.019 (0,48)

0.017 (0,43)

0°~3°

0.179 (4,55)

0.187 (4,75)

0.056 (1,42)

0.064 (1,63)

0.296 (7,52)

0.304 (7,72)

0.300 (7,62)

0.252 (6,40)

F

C

C

H

H

H

C

A

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.

C. Lead width and height dimensions apply to theplated lead.

D. Leads are not allowed above the Datum B.E. Stand–off height is measured from lead tip

with reference to Datum B.F. Lead width dimension does not include dambar

protrusion. Allowable dambar protrusion shall notcause the lead width to exceed the maximumdimension by more than 0.003”.

G. Cross–hatch indicates exposed metal surface.

H. Falls within JEDEC MO–169 with the exceptionof the dimensions indicated.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2015, Texas Instruments Incorporated

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pwm solenoid/valve driver (rev. b) - texas instruments

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