Pushing CMOS to the Limit

Ali M. Niknejad

Berkeley Wireless Research Center

University of California, Berkeley

Outline

Motivation

CMOS Device Scaling

Effect of scaling on:

Gain, Noise, Distortion, Power

Passive devices

Conclusion

MOTIVATION

Wideband High DR Front-End

Broadband, high dynamic range, reconfigurable front-end

Can we design such a front-end using 45nm CMOS?

32nm? When is the party over?

The “Last Inch”

Wireless HD Video

Required Link Budget

Need +10dBm power, +10dB system NF zero link

margin

Low Power Phased-Array

A fully-integrated low-cost Gb/s data communication using 60 GHz band.

10 Gb/s at 100mW per channel should be possible!

Distributed MIMO

Automotive Radar

Short range radar for

parking assist, object

detection

Long range radars for

automatic cruise

control, low visibility

(fog) object detection,

impact warning

Long range vision:

automatic driver

mm-Wave Imaging … THz?

Use of microwave scattering from

objects to predict image

A low-cost, noninvasive solution

(meV versus keV)

Active and Passive Microwave

Imaging

Ultrawideband imaging

THz detection … ?

TeraView Ltd

SCALING TO ATOMIC LIMITS

Process Cross Section

Typical process offers isolated high fT PMOS/NMOS

device, multiple Cu metal layers, high quality MIM caps

(or enough layers to realize it in standard metalization)

Scaling Rules

Originally formulated by Dennard (JSSC 1974)

Lgate scaling improved speed of device

Tox gate oxide scaling (now at atomic limits)

Xj junction scaling (keep gate control)

VDD supply scaling (reduce fields for better SCE)

Show stoppers:

Gate leakage

Parasitic resistance

Mobility degradation

CMOS Technology Scaling

CMOS technology is getting faster and faster…

But lower supply voltage hurts analog. At best,

constant dynamic range requires quadratic increase in

current with voltage scaling.

Vdd fT

Lmin

ITRS Scaling

CMOS Technology Trends

130nm 90 nm 65nm 45nm

Ft 70 GHz 100 GHz 150 GHz 280 GHz

Fmax 135 GHz 200-300 GHz 300 GHz 560 GHz

NFmin

(60 GHz)4-5 dB 3-4 dB 3 dB 2.3 dB

Measured ITRS+projection

dsschggggdmg

tmax

gg

mt

g)RrR()CCg(R2

ff

C2

gf

From Bulk to Multi-Gate

Scaled CMOS is not your uncles Si + SiO2 + Al:

Using materials from the entire periodic table!

45nm Technology Node:

Bulk CMOS

Metal gate/high-K (low leakage)

Strain for mobility enhancement

32nm likely to be a bulk device

22nm is going to be a multi-gate device

TEENY TINY BUT VERY FAST

fmax vs. Finger Width

Increasing gate resistance

Gate Drain

Source

fmax in GHz

Mason’s Unilateral Gain

Apply lossless feedback to unilateralize the 2-port

Properties of U:

If U > 1, the two-port is active. Otherwise, if U 1, the two-port is

passive.

U is the maximum unilateral power gain of a device under a lossless

reciprocal embedding.

U is the maximum gain of a three-terminal device regardless of the

common terminal.

U is very sensitive to any loss in the 2-port. Good way to test

accuracy of model and measurements.

VGS = 0.65 V

VDS = 1.2 V

IDS = 30 mA

W/L = 100x1u/0.13u

130-nm Device Performance

90nm Technology Performance

Use short fingers to minimize

gate resistance and substrate

resistance.

Can easily cascode devices

(shared junc).

Compared to 130nm, 90nm

technology has

~ 1 dB higher MSG

~1-2 dB lower noise

fmax ~ 180 GHz (compared to

135 GHz in 130nm)

“Roundtable” Layout

MSG 60GHz = 8.5 dB, NFmin ~ 3-4 dB

fmax= 300 GHz (extrapolated), fT= 100 GHz

Highest reported fmax/fT=3 ratio for CMOS!

104 GHz Oscillator (90nm)

Core Rountable Transistor

Output power -8 dBm

DC Power < 7 mW

Highest reported VCO efficiency > 100 GHz

Pre

sen

ted

at

ISS

CC

200

7

104 GHz CMOS Amplifier (90nm)P

resente

d a

t IS

SC

C 2

007

Operating above Ft (100 GHz)

Highest reported CMOS amp

Designed with non-optimal device

mm-Wave Cascode Device

Cascode HF Bilaterization

MSG of cascode close to U of common-source device

below 30 GHz

At 60 GHz MSG of cascode same as common-source …

device is no longer unilateral

Cascode Gain Enhancement

Tune out parasitics or design as a two-stage

amplifier.

Cannot use shared junction layout.

Unilateralization of Cascode Device

Possible to simultaneously cancel the real and imaginary of

Y12 using a gate inductance on cascode device.

Substantial gain enhancement possible (MSG 8 dB 20 dB).

SMALL SIGNALS: NOISE

Limits for RF Noise

MOSFET noise at high frequency limited by thermal noise

and correlated gate noise.

Using the Pospiezalski noise model, the lowest possible

device noise figure is given by

Using short transistor fingers to minimize the gate

resistance, Rg, noise, this is bounded by

gm

T

Rgf

fF

21min

5

121min

Tf

fF

Minimum Achievable Noise

NFmin (dB)

fT (GHz)

130nm

90nm

65nm

mm-Wave Noise Measurements

Broadband Techniques

LsZin

-A

LsZin

Cpad

Rf

Cpar

LsZin

A

ZL

Ls

Cgs

CpadZin

[A. Liscidini et al. VLSI’05] [D. Allstot et al. RFIC’04]

[F. Brucoleri et al. ISSCC02]

36

Rs

M1

M3

M4

M2

R1 RL

Vx

Vy

Vout

Vs

Noise Cancellation

in2

also in [ C-F, Liao et al. CICC’05 ] Reduce M1 noise by proper choice of gm3/gm4

LARGE SIGNALS: DISTORTION

Important MOS Non-Linearity

Square law high field/short channel effects

Mobility degradation

Universal mobility curve (phonon and surface

scattering) Vgs

Velocity saturation & ballistic transport Vds

Body effect (non-uniform doping)

Output impedance non-linearity (and interaction

with gm)

Cgs for high input swings

Mobility with Coulomb Scattering

2 4 6 8 100

1x102

2x102

3x102

4x102

5x102

6x102

123K

173K

300K

Ho

le M

ob

ility(c

m2/V

s)

Qinv(x1012

/cm2)

data model model w/o C.S.

inb

b

effeff

eff

QQ

QUCEUBEUA

2

0

1

Single Equation I-V Curve: “Smoothing Approach”

Since we have good models for weak/strong

inversion, but missing moderate inversion, we can

“smooth” between these regions and hope we

capture the region in between (BSIM 3/4 do this

too)

The factor θ models short-channel effects and η

models the weak-inversion slope

X

XKVVfI TGSDS

1)(

2

kT

VVq TGS

eq

kTX 2

)(

1ln2

Limiting Behavior

In strong inversion, the exponential

dominates giving us square law

In weak inversion, we expand the ln

function

TGS

kT

VVq

VVeq

kTX

TGS

2

)(

1ln2

X

XKVVfI TGSDS

1)(

2

xx 1ln

kT

VVq

DS

TGS

eq

kTKKX

X

XKI

)(2

22

21

kT

VVq TGS

eq

kTX 2

)(

2

I-V Derivatives

X

XKVfIDS

1)(

2

VXV Xff VVXVXXVV XfXff 2

VVVXVVVXXVXXXVVV XfXXfXff 33

2)1(

)2(

X

XXKfX

3)1(

2

XKfXX

4)1(

6

XKfXXX

21

1

s

XV

21

1

2

sskT

qXVV

31

1

2

2

2

ss

ss

kT

qXVVV

Distortion Calculation

Source: Manolis Terrovitis Analysis and Design of Current-Commutating CMOS Mixers

44

0 0.2 0.4 0.6 0.8 1-0.02

-0.01

0

0.01

0.02Drain current and its derivatives

VGS

(V)

(A),

(A

/V),

(A

/V2)

0 0.2 0.4 0.6 0.8 1-0.1

-0.05

0

0.05

0.1Drain current and its derivatives

VGS

(V)(A

/V3)

IDS

gm

gm

gm

0 0.2 0.4 0.6 0.8 1-20

-10

0

10

20

30

VGS

(V)

Viip

3 (

dB

v)

Taylor series representation

MOSFET Linearity Sweet Spot

Transconductor

TOHvg

vg

vg

TOHvV

Iv

V

Iv

V

Ii

gsm

gsm

gsm

gs

GS

DSgs

GS

DSgs

GS

DSd

..!3

"

!2

'

..!3

1

!2

1

32

3

3

32

2

2

"83

m

mIIP

g

gV

0 0.2 0.4 0.6 0.8 10

0.003

0.006

0.009

0.012

0.015Drain current and its derivatives

VGS

(V)

(A),

(A

/V),

(A

/V2)

IDS

gm

gm

0 0.2 0.4 0.6 0.8 10

1.25

2.5

3.75

5x 10

-3 Drain current and its derivatives

VGS

(V)

(A),

(A

/V)

IDS

gm

3rd order nonlinearity

i d

Vgs

Sweet spot

i d

Vgs

[0.13um]

“Multiple Gated Transistors” Notice that we can use two

parallel MOS devices, one

biased in weak inversion

(positive gm3) and one in strong

inversion (negative gm3).

The composite transistor has

zero gm3 at bias point!

Source: A Low-Power Highly Linear Cascoded Multiple-Gated Transistor CMOS

RF Amplifier With 10 dB IP3 Improvement, Tae Wook Kim et al., IEEE MWCL, Vol.

13, NO. 6, JUNE 2003

MGTR Linearization Range

VgsVgs1 Vgs2

Rs

M1

M3

M4

M2

R1 RL

Vx

Vy

Vout

Vs

Rs

M1

M3

M4

M2

R1 RL

Vx

Vy

Vout

Vs

47

0 0.2 0.4 0.6 0.8 1-1.5

-1

-0.5

0

0.5

1

1.5

2

Vgs (V)

2n

d d

eri

va

tive

of g

m

MGTR

single transistor

weak inversion bias

strong inversion bias

composite transistor

Noise and Distortion Cancellation

Vgs1 Vgs2

M3/M4 perform both IM3 cancellation and M1 noise

cancellation

[ Tae W. et al. IEEE MWCL’06 ]

Volterra Series Analysis

Vs

mgmg mg LmSmSfundout RgVBgVAV 3141,

][ 3

3

34

3

33, LmSmSoutRgVBgVAV rd

]66

[ 33

143

1 Lm

Sm

S Rg

VBg

VA

LmSmS RgVBBgVAA ][ 3

3

214

3

21

LmSmSfundout RgVBgVAV 3141,

][ 3

3

34

3

33, LmSmSoutRgVBgVAV rd

]66

[ 33

143

1 Lm

Sm

S Rg

VBg

VA

Both M3/M4 bias and size are

governed by the first 2

cancellations

Residual Vout IM3 due to

second-order interaction

could be substantial

m)

LmSmS RgVBBgVAA ][ 3

3

214

3

21

Single-ended “Differential Pair”

A2/B2 related to gm’ of the common-gate transistor

Single-ended PMOS/NMOS pair zeros out gm’

3

3

34

3

33, LmSmSoutRgVBgVAV rd

66 33

143

1 Lm

Sm

S Rg

VBg

VA

LmSmS RgVBBgVAA 3

3

214

3

21

Silicon Implementation

IFX 0.13um

Regular VT transistors

MIM caps

Inductorless

S-parameters and Noise Figure

Bandwidth

(S11<-8.5dB)0.8~2.1GHz

Gain (S21)>8.6dB

(6dB more on chip)

Noise Figure (NF) <2.6dB

52

WCDMA IIP3 Test

WCDMA blocker

compliant test

P1dB=-12dBm

53

IIP3/NF bias sensitivity

50mV

POWER IN NUMBERS

Power Amplifiers

Peak Output Power

Efficiency

Power Gain

Amplifier Linearity

Stability over VSWR

Ability to transmit into an unknown/varying

load

Power Control

Step size, range

CMOS Oxymoron of a PA

Is CMOS a viable technology for power amplifiers?

Low voltage means less power available for a given

device width

Higher current from given device increases sensitivity

to series loss

Low supply voltage means high impedance

transformation ratio (and thus higher insertion loss)

New power amplifiers should be more

linear and operate more efficiently over a

wide range of output power!

Cal Tech DAT

Use virtual grounds wisely to turn 1:1 coupled lines into a

transformer loop.

Power Combining and Control

Use transformer to

perform efficient

power combining

Can also use structure

for efficient power

back-off to improve

average power

efficiency

At moderate back-off

(6 dB), efficiency

close to peak level

Transformer FOM

Unlike inductor Q factor, there

is no obvious “silver bullet”

FOM for transformers.

For power combining

applications, the maximum

power gain (bi-conjugate

match) has been used as a

figure of merit

For a simple 1:1 transformer,

the maximum gain is a function

of only the Q and K factors

Transformer Efficiency

Notice that relatively low insertion loss is possible with moderate

on-chip Q and K factors, thus allowing fully-integrated

transformers.

CMOS “RF” Prototype

Each stage is a pseudo-differential cascode amplifier

Can scale output power by adding more stages to transformer

Use dual thick metal layers to implement high “K” low loss

transformer (80% efficient)

Measured Linear PA Performance

Fully 130nm CMOS integrated

prototype

27 dBm (30% efficiency)

Linear mode: 24 dBm (25%)

No external passives

Measurements with EDGE Signals

Freq = 2.4-GHz, Peak Power Mode

Measurements with 802.11g Signals

Pout = 14.5-dBm EVM = 4.48%

Freq = 2.4-GHz, Peak Power Mode

Table of PA Performance

Technology 0.13-μm RF CMOS

Supply voltage 1.2-V

DC Current 114-mA

P-1dB 24-dBm

Drain efficiency 25%

Saturated Power 27-dBm

Drain efficiency 32%

Improved Layout…

Using two primary windings

Improved coupling

Lower loss (current crowding at edge of conductors)

More symmetric primary/secondary for optimal power

transfer

Prototype PA in Digital CMOS

Four stage

differential

design

Single-ended

50Ω output

Thin oxide

90nm

transistors

Measured Output Power

Peak power is 24 dBm. Good match to simulation up to

1dB compression point.

24 dBm

Measured Efficiency

27%

THE FATE OF PASSIVE ELEMENTS

Passive Devices Don’t Scale

For fixed frequency, area of inductors roughly constant

Multiple metal layers allow more compact inductors but

high Q inductor still single layer (top thick layer)

Microprocessor or Inductor?

It is widely appreciated that the area of an inductor

in today’s CMOS is equivalent to a powerful CPU

Low frequencies: Get rid of them

Use broadband circuit techniques

Analog design = RF design … use feedback

Use linearity enhancement schemes for out of band

blockers

High frequencies:

Area is still reasonable

T-line versus lumped?

What to do with all that metal?

Slow wave structures

Scaling Helps and Hurts

Can build very high density caps

Cu and thick metal stacks were very

exciting (130nm, 90nm)

Metals are getting thinner (low K)

Inductors and T-lines are getting worse

Inductor or T-Line?

LC resonators have good Q factor … varactors are problematic

above 40GHz

High Z0 quarter wave resonators loop inductors

Optimum Taper Profile

Andress and Ham [JSSC

2005] showed that a tapered

resonator has improved Q

Assumed a constant Z0 line.

What if you remove this

constraint?

Result looks like an LC tank!

Transformers Scale to mm-Waves

Isolation, impedance

matching, biasing …

Good insertion loss

Compact layout

compared to T-lines

Conclusion

CMOS technology offers

Fast transistors (low noise)

Low supply voltage

Poor linearity

Circuit techniques can overcome many limitations

in linearity and power

Technology scaling mostly beneficial for mm-

wave

High fmax transistors, reduced power consumption

Increase in parasitic resistances can be detrimental to

fmax scaling

Si technology is the new playing field for

electromagnetic structures … room for creativity!

Acknowledgements

DARPA TEAM Program, C2S2

STMicroelectronics & Infineon

chip fabrication and support

BWRC Member Companies