Project 1

Part 1a: A 4-to-1 multiplexer with 8-bit busses and 2-bit selection

Specification: Multiplexors are combinational circuits that select binary information from one of

(normally) 2^n input lines based on the selection of n selection switches, called selection inputs.

Some multiplexors use a 2-4 decoder to select the input line, however I chose not to and wired

the selection switches directly into the multiplexor for the sake of cutting down on gate cost. The

design features one subdesign which is a 1-bit 4-to-1 multiplexer.

Design 1a-a:

1-bit 4-to-1 Multiplexor

Gates: 2 INV, 4 3inputAND, 1 4inputOR

Inputs: i0, i1, i2, i3, s0, s1

Outputs: notNamedY

Decided to leave everything unassigned so it is easier to see here

Verification 1a-a: Figuring out how to verify a 4-to-1 multiplexor can be tricky due all of the

possible input combinations (2^6). However by looking at the truth table for a simple AND gate

you will see that the only way for an AND to pass a signal is for all of its input values to equal 1.

AND Truth Table

A B Y

0 0 0

0 1 0

1 0 0

1 1 0

Knowing this and the equation for a 4-to-1 multiplexor (pg. 133):

Y = (S1’)(S0’)I0 + (S1’)(S0)I1 + (S1)(S0’)I2 + (S1)(S0)I3

“ ‘ “ Used to denote a NOT.

We can see that the only inputs allowed to be passed on to the OR gate are the ones

where the correct combination of s1 and s0 are chosen. I’ve included another truth table to

demonstrate:

S1 S0 S1’ S0’ S1’ S0 S1 S0’ S1 S0

0 0 1 1 1 0 0 1 0 0

0 1 1 0 1 1 0 0 0 1

1 0 0 1 0 0 1 1 1 0

1 1 0 0 0 1 1 0 1 1

With this information I determined that only 4 out of the possible 2^6 combinations were

necessary to test, as shown in the fallowing truth table. The waveform following that shows the

results.

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From top to bottom: i0-i3, selector0, selector1, notNamedY (the output)

As we can see all four inputs for my circuit produce the appropriate waveform, verifying

the circuit functions as it is supposed to.

Design 1a:

4-to-1 multiplexor using 8-bit busses as input and output

Gates: 8 1-bit 4-to-1 multiplexers (part1a-1)

Inputs: 4 8-bit busses (i0-i3), s0, s1

Outputs: Output

Again, unassigned for clarity

Verification 1a: This more complex circuit will use the same logic as the simpler 1-bit 4-to-1

multiplexers. Since we have verified that the other circuit does work properly we will know that

this one will also function correctly. I will set all 4 inputs to a different decimal value to

differentiate them in the waveform.

From top to bottom: Selector1 and 2(s0 and s1), n4 (Output), and 0-3input (i0-i3)

As you can see the value of the output signal matches that of the input selected by the

selector switches verifying the circuit.

Part 1b: An 8-bit adder

Specification: A full adder is a circuit that will output the sum of the inputs. A 1-bit full adder

will take three inputs and produce to separate outputs, the “sum” and the “carry”, with the carry

representing an overflow. My design for the final adder will feature inputs from two 8-bit busses

and will make use of 8 full adders to add all the bits separately. The adders will add them in

order from the least to the most significant bit, allowing each adder to pass on its carry bit to the

next adder.

Design 1b-a:

1-bit Full Adder

Gates: 2 2AND, 2 2XOR, 1 2OR

Inputs: in0, in1, carryIn

Outputs: out, carryout

Unassigned for clarity

Verification: With only 8 inputs this circuit is easy to match with its truth table (pg. 152)

X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From top to bottom: input0, input1, carriedIn, output, carriedOut

Some HADES weirdness in causing output to spike at 10, 11, 12, 13 seconds.

Design 1b:

Adder that adds up two 8-bit buses

Gates: 8 1-bit Full Adders

Inputs: input0, input1 (8-bit busses), firstCarryIn

Outputs: Output, finalCarry

Once more, unassigned for clarity

Verification: This circuit will be easy to verify with four tests. When both values equal to zero

resulting in output 0, when the firstCarryIn is active with a result of 1, when both values add up

to some other value (I’ll use a sum of 255 to show all connections work) resulting in there sum,

and then when the sums are a value over 255 to make sure the overflow is carried out.

Top to bottom: finalCarryOut1, n6 (finalOutput), firstCarryInSig, input1, input0

As we can see the output is indeed the sum of the two inputs and the carry in. We can

also see that when the sum exceeds 255 that the overflow (finalCarryOut1) activates. This

verifies the circuit.

References

Mano, M. M., & Kime, C. R. (2004). Logic Computer Design Fundamentals. New Jersey:

Pearson Prentice Hall.