National Sun Yat-sen University Embedded System Laboratory

Presenter: Hong-Wei Zhuang

On-Chip SOC Test Platform Design Based

on IEEE 1500 Standard

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:18 , Issue: 7 )

Kuen-Jong Lee, Tong-Yu Hsieh, Ching-Yao Chang,Yu-Ting Hong, and Wen-Cheng Huang

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IEEE 1500 Standard defines a standard test interface for embedded cores of a system-on-a-chip (SOC) to simplify the test problems. In this paper we present a systematic method to employ this standard in a SOC test platform so as to carry out on-chip at-speed testing for embedded SOC cores without using expensive external automatic test equipment. The cores that can be handled include scan-based logic cores, BIST based memory cores, BIST-based mixed-signal devices, and hierarchical cores. All required test control signals for these cores can be generated on-chip by a single centralized test access mechanism (TAM) controller. These control signals along with test data formatted in a single buffer are transferred to the cores via a dedicated test bus, which facilitates parallel core testing.

Abstract

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A number of design techniques, including on-chip comparison, direct memory access, hierarchical core test architecture, and hierarchical test bus design, are also employed to enhance the efficiency of the test platform. A sample SOC equipped with the test platform has been designed. Experimental results on both FPGA prototyping and real chip implementation confirm that the test platform can efficiently execute all test procedures and effectively identify potential defect(s) in the target circuit(s).

Abstract(Cont.)

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As SOC designs become more and more complex, requirements for ATE to accurately and efficiently test various types of cores have drastically increased the SOC test cost.

external automatic test equipment (ATE) provide test stimuli as well as collect test responses through chip I/O

pins

What is the Problem

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Related work

using pure software

[7]

On-Chip SOC Test Platform Design Basedon IEEE 1500 Standard

usually difficult to achieve high fault converge

require extensive use of external

automatictest equipment (ATE) [4],[5],[6]

increased the SOC test cost

using software together with some extra hardware

[8-10]

core is wrapped by an

IEEE 1500 wrapper

[10]

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PROPOSED SOC TEST PLATFORM TAMC : a test access mechanism controller TAPC : a test access port controller (TAPC) for each

1500 core

Proposed method

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test platform generates a set of control signals that can be shared by 1149.1 and 1500 standards so as to reduce the extra area overhead.

test bus can be specially configured in a multiple-level hierarchy so as to reduce the loading of the test bus.

TAMC provides a parallel-to-serial mechanism to deliver test patterns from memory to scan chains of cores and a serial-to-parallel mechanism to transfer the test results from the cores to the TAMC

SOC test platform

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Outline of the test flow

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Control Unit TAMC according to the setup information provided by the embedded processor

and issues proper signals for test control.

Memory Access Unit This unit generates the addresses for the memory to be accessed via a number of counters

Wrapper Control Unit This unit generates the control signals for each wrapper according to the setup information

stored in the internal data registers of the TAMC.

Comparator An XOR-based comparator is designated to verify test results in TAMC

Shift Buffers Due to the format difference between the data obtained

。 parallel-in-serial-out operations for test pattern application

。 serial-in-parallel-out operations for test response collection

TEST ACCESS MECHANISM CONTROLLER (TAMC)

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Scan-Based Testing Hierarchical Testing

Memory BIST

SUPPORTED TEST MODES

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Area overhead

Test time

Compare with other methods

Before the Experiment

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The wrappers require 3.721% of the processor and core

The test platform requires additional 1.384%

Area Overhead

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All test operations are completed with 712 697 test cycles, which is only approximately 0.009 s when the system clock runs at 80 MHz

Test time

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at-speed testing is achieved

no extra test pins are required

no signal distortion problem exists through chip I/O pins

the requirement of external ATE is minimized

carry out all core test procedures

test control signals can be generated on-chip

test buffers can be shared by all cores

Hierarchical core testing can be supported

test bus loading problem can be resolved

both static and dynamic parameter analyses for analog or mixed-signal devices can be done on-chip.

Conclusion

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This paper help me known that SOC test platform

We can faster to test on chip SOC than before

My Comment