Present by Present by

Pitipund Lorchirachoonkul 43650225Pitipund Lorchirachoonkul 43650225

Uchot Jitpaisarnsook 43650373Uchot Jitpaisarnsook 43650373

Present by Present by

Pitipund Lorchirachoonkul 43650225Pitipund Lorchirachoonkul 43650225

Uchot Jitpaisarnsook 43650373Uchot Jitpaisarnsook 43650373

Arm (Advance RISC Arm (Advance RISC Machine)Machine)

Arm (Advance RISC Arm (Advance RISC Machine)Machine)

RISC Overview

A large uniform register file

A load-store architecture

Simple addressing modes

Uniform and fixed length instruction fields

Arm Overview

Control over both the ALU and shifter

Auto-increment and auto-decrement addressing modes

Load and store multiple instructions

Conditional execution of all instructions

ARM registers

31 registers , 32-bit: 16 are visible and other are used to speed up exception processing

Program counter (R15)

Link register (R14)

Other registers

User/Systerm Supervisor Abort Undefined Interrupt Fast Interrupt

R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

R8 R8 R8 R8 R8 R8_FIQ

R9 R9 R9 R9 R9 R9_FIQ

R10 R10 R10 R10 R10 R10_FIQ

R11 R11 R11 R11 R11 R11_FIQ

R12 R12 R12 R12 R12 R12_FIQ

R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ

R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ

PC PC PC PC PC PC

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ

Mode

Types of Exceptions

Two levels of interrupt

Memory aborts

Attempted execution of an undefined instruction

Software interrupts

ARM Instruction Set

Branch

Data-processing

Load and store

Coprocessor

Branch Instructions

General branch Intructions

Branch with Link

Software interrupt

Data-processing Instructions

Data-processing instructions proper

Multiply instructions

Status register transfer instructions

Load and Store Instructions

Load or store single register

Load and store multiple register

Swap a register value with the

value of a memory location

Coprocessor Instructions

Data-processing instructions

Register transfers

Data-transfer instructions

The CPU Core5 stage pipeline

Harvard architecture

ARM v4T compliant

110,000 transistors

TSMC 0.18m:0.3 mW/MHz (1.8V)

220MHz (1.65 V)

1 mm2

ARM Application

Typical appliance that running Java application

Jazelle instruction set

ARM instruction set

Thumb instruction set

Java ByteCodes

Java ByteCodes

Directly executed bytecodes

Emulated bytecodes

Undefined bytecodes

Directly executed bytecodes

140 bytecodes executed directly in HWconstant loads, (iconst_0, dconst_0, …)variable loads/stores, (iload, dstore, … )array load/stores, (iaload, dastore, … )integer data operations (iadd, isubb, i2b, … )branches (ifeq, icmp_ifeq, … )quick constant pool loads(idc_quick, … )quick static/field operations (getfield_quick, … )

Emulated bytecodes

94 bytecodes emulated in softwarefloating point (ddiv, dadd, dmul, … )integer division (idiv, irem, ldiv, lrem)switch (tableswitch, lookupswitch)invoke (invokevirtual, invlkestatic, … )return (ireturn, return, … )new (new, newarray, … )unresolved ldc (ldc, ldc_w, ldc2_w)unresolved field/static (getstatic, putfield, … )

Jazelle Operation

New ARM instruction:

Cond Rm31…28 3…0

BXJ Rm

If Condition then J = 1, PC = Rm;enters Java state and begins Byte Code execution at (Rm)

Jazelle Operation

Addition of ‘J’ bit to CPSR:

Flags I F T ModeJ31…27 24 4…07 6 5

J=0 : Processor in ARM or Thumb state (depending on T bit)J=1, T=0 : Processor in Java state

Register Re-use and Stack Optimization

Use of ARM Registers in Jazelle State:

R0-R3 Used to cache Java expression stackR4 Local variable 0 (‘this’ pointer)R5 Pointer to table of SW handlersR6 Java stack pointerR7 Java variables pointerR8 Java constant pool pointerR9-R11 Reserved for JVM (not used by h/w)R12, R14 Scratch usage / Java return addressR13 Machine stack pointerR15 Java PC

Interrupt Behavior / Real-time performance

Jazelle is Compatible with ARMProgramming Conventions for Interrupt Handlers:

JavaProgram

InterruptHandler

Java State ARM State

CPSR->SPSRpc->r14

CPSR<-SPSRpc<-(r14-4)

STM r13!, {reg. list} ; save regs used in ; interrupt handler

LDM r13!, {reg, list} ; restore regsSUBS pc, r14, #4 ; return & restore state

Support for Java Run-time Environments

Competitor Comparison / Review of existing solutions

Competitor Comparison / Review of existing solutions

Software Emulation(SUN JDK, ARM9)

JIT

ExecutionPerformance

CM/MHz

Real-timeSystem

Performance

MemoryCost

HardwareImplementation

Cost

Legacy Code /RTOS support

Software Emulation(ARM JDK, ARM9)

Co-processor(eg Jedi Tech, JSTAR)

Dedicated Processor

ARM with architectureextensions

0.67

1.7

6.2*

2.9

3

5.5

Poor

Excellent

~ 16kbyte

~ 16kbyte

-

> 100kbyte

-

~ 8kbyte

-

-

-

~ 25k gates

20-30k gates

~ 12k gates

Yes

Yes

Yes

Yes

No

Yes

The only solution to meet all of the performance & application requirements.

*Note: JIT performance excludes compilation overhead.

ENDEND

ARM7TDMIMCLKnWAITECLKnIRQnFIQ

ISYNCnRESETBUSEN

BIGENDnENIN

HIGHZ

nENOUTnENOUTI

ABEAPEALEDBETBE

BUSDISECAPCLK

VDDVSS

DBGRQBREAKPT

DBGACKnEXEC

EXTERN 1EXTERN 0DBGEN

RANGEOUT 0RANGEOUT 1

DBGRQICOMMRXCOMMTX

Clocks

Interrupts

Controls

Power

Debug

Bus

TCKTMSTDI

nTRSTTDO

TAPSM[3:0]IR[3:0]

nTDOENTCK1TCK2

SCREG[3:0]11

CPBCPA

ABORT

BL[3:0]

nOPCnCPI

LOCKnTRANS

MAS[1:0]nRWSEQ

nMREQ

TBITnM[4:0]

A[31:0]

DOUT[31:0]

D[31:0]

DIN[31:0]

AR

M7T

DM

I

BoundaryScan

Boundary ScanControl SignalsProcessor ModeProcessor State

Memory Interface

MemoryManagementInterface

CoprocessorInterface

ARM7TDMIScan

Control

D[31:0]

nENOUT nENIN

DBE

HIGHZTBITTBEnM[4:0]CPBCPAnCPILOCKSEQnOPCnMREQnTRANSABORTnRESETnFIQnIRQMAS[1:0]nRWnWAITMCLKAPEBL[3:0]ISYNCnEXECECLKDBGACKBREAKPTIDBGRQI

Address Register

A[31:0]

ABEALE

Incre

me

nte

r B

us

AddressIncrementer

PC

Bu

s

Register Bank(31x32-bit registers)(6 status registers)

A B

us

AL

U B

us

32x8Multiplier

32-bit ALU

BarrelShifter

Write Data Register

B B

us

Instruction Pipeline& Read Data Register

& Thumb Instruction Decoder

InstructionDecoder

&ControlLogic