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Use of predefined Intellectual Property (IP)

A platform-based system consists of a RISC processor, memories, busses and a common language

Platform-based design poses the problem of partitioning a solution between hardware (HDL) and software (programming processors)

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Design Method

NRE Unit Cost Power Dissipation

Complexity of Implementation

Time-to-Market

Performance Flexibility

μProcessor/DSP

low medium high low low low high

PLA low medium medium low low medium low

FPGA low high medium medium low medium high

Gate/Array medium medium low medium medium medium medium

Cell Based high low low high high high low

Custom Design

high low low high high Very high low

Platform Based

high low low high high high medium

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23

Design Decision Trade-offs

24

Generalised Design Flow

25

ASIC Design Flow

The Design Productivity Challenge

Source: sematech97 A growing gap between design complexity and design productivity

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

1981

10

Logi

c T

rans

isto

rs p

er C

hip

(K)

Pro

duct

ivity

(T

rans

./Sta

ff-M

onth

)

100

1,000

10,000

100,000

1,000,000

10,000,000

1

XX

X XX

X

x

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

10

2.5m

.35m

.10m19

83

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009

Transistor/Staff Month

Logic Transistors/Chip

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A Simple Processor

MEMORY

DATAPATH

CONTROL

INP

UT

/OU

TP

UT

40 Courtesy: Philips

41

En

erg

y E

ffic

ien

cy (

in M

OP

S/m

W)

Flexibility (or application scope)

0.1-1

1-10

10-100

100-1000

None Fully flexible

Somewhat flexible

Ha

rdw

ire

d c

usto

m

Co

nfi

gu

rab

le/P

ara

me

teri

za

ble

Do

ma

in-s

pe

cif

ic p

roce

sso

r (e

.g.

DS

P)

Em

be

dd

ed

mic

rop

roce

sso

r

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• Design process traverses iteratively between three abstractions: behavior, structure, and geometry • More and more automation for each of these steps

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Digital Circuit Implementation Approaches

Full Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Design Implementation Approaches

SemicustomSemicustomMicroprocessor/DSP

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44

Intel 4004

Courtesy Intel

45

Intel 4004 (‘71) Intel 8080 Intel 8085

Intel 8286 Intel 8486 Courtesy Intel

Cell-based Design (or standard cells)

46

Routing channel requirements are reduced by presence of more interconnect layers

Standard Cell — Example

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[Brodersen92]

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Cell-structure hidden under interconnect layers

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3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

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Initial transistor geometries

Placed transistors

Routed cell

Compacted cell

Finished cell

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x 0 x 1 x 2

AND plane

x 0 x 1

x 2

Product terms

OR plane

f 0 f 1

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Inverting format (NOR-NOR) more effective

Every logic function can be expressed in sum-of-products format (AND-OR)

minterm

53

f0 f1x0 x0 x1 x1 x2 x2

Pull-up devices Pull-up devices

V DD GND f And-Plane Or-Plane

River PLAs A cascade of multiple-output PLAs.

Adjacent PLAs are connected via river routing.

54

PRE-CHARGE

PR

E-

CH

AR

GE

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BUFFER

BU

FF

ER

BU

FF

ER

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BU

FF

ER

PRE-CHARGE

PR

E-

CH

AR

GE

BUFFER

BU

FF

ER

• No placement and routing needed.

• Output buffers and the input buffers of the next stage are shared.

Layout of C2670

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Network of PLAs, 4 layers OTC

River PLA, 2 layers no additional routing

Standard cell, 2 layers channel routing

Standard cell, 3 layers OTC

0.2

0.6

1

1.4

0 2 4 6 area

dela

y

SC NPLA RPLA

Area: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable

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25632 (or 8192 bit) SRAM Generated by hard-macro module generator

57 Synopsys DesignCompiler

58

A Protocol Processor for Wireless

59

HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-Layout Simulation

Post-Layout Simulation

Structural

Physical

Behavioral Design Capture

Des

ign

Itera

tion

60 Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

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Physical Synthesis

RTL (Timing) Constraints

Place-and-Route Optimization

Artwork

Netlist with Place-and-Route Info

Macromodules Fixed netlists

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Pre-diffused (Gate Arrays)

Pre-wired (FPGA's)

Array-based

63

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

Uncommited Cell

Committed Cell (4-input NOR)

64

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation

66

Random Logic

Memory Subsystem

LSI Logic LEA300K (0.6 mm CMOS)

67

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array (VPGA)

[Pileggi02] Exploits regularity of interconnect

Classification of prewired arrays (or field-programmable devices):

Based on Programming Technique ◦ Fuse-based (program-once)

◦ Non-volatile EPROM based

◦ RAM based

Programmable Logic Style ◦ Array-Based

◦ Look-up Table

Programmable Interconnect Style ◦ Channel-routing

◦ Mesh networks

68

69

Open by default, closed by applying current pulse

antifuse polysilicon ONO dielectric

n + antifuse diffusion

2

Open by default, closed by applying current pulse

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PLA PROM PAL

I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1 O 2 O 3

Programmable AND array

Programmable OR array I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1 O 2 O 3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O 0

I 3 I 2 I 1 I 0

O 1 O 2 O 3

Fixed AND array

Programmable OR array

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f 0

1 X 2 X 1 X 0

f 1 NA NA

: programmed node

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F A 0

B

S

1

Configuration

A B S F=

0 0 0 0 0 X 1 X 0 Y 1 Y 0 Y X XY X 0 Y Y 0 X Y 1 X X 1 Y 1 0 X 1 0 Y 1 1 1 1

XY XY

X Y

73

A

B

SA Y

1

C

D

SB

1

S0S1

1

Out

ln1 ln2

Mem

ory In Out

00 00

01 1

10 1

11 0

74

75

D 4

C 1 ....C 4

x xxxxx

D 3

D 2

D 1

F 4

F 3

F 2

F 1

Logic function

of xxx

Logic function

of xxx

Logic function

of xxx

xx

xx

4

xx xx xx

xx xx xx xx

x x x

xxxx xxxx xxxx

H P

Bits control

Bits control

Multiplexer Controlled by Configuration Program

x

x x

x

xx

x xx xx

xxxx

x

xx xxxx

xx

x

xx

x xx

xx

Xilinx 4000 Series

76 Vertical tracks

Input/output pin Programmed interconnection

Interconnect Point

Horizontal tracks

Cell

M

77

Switch Box

Connect Box

Interconnect Point

78 Courtesy Dehon and Wawrzyniek

79 From Smith97

80

LAB2

PIA

LAB1

LAB6

t PIA

t PIA

row channel column channel

LAB

Array-based (MAX 3000-7000)

Mesh-based (MAX 9000)

81

I/O Buffers

Program/Test/Diagnostics

I/O Buffers

I/O B

uffe

rs

I/O B

uffe

rs

Vertical routes

Rows of logic modulesRouting channels

Standard-cell like floorplan

82

2

12

8

4

3

2

3

CLB

8 4 8 4

Quad

Single

Double

Long

Direct Connect

Direct Connect

Quad Long Global Clock

Long Double Single Global Clock

Carry Chain

Long 12 4 4

83

Xilinx XC4000ex

84

Array Size: 8x8 (2 x 4 LUT)

Power Supply: 1.5V & 0.8V

Configuration: Mapped as RAM

Toggle Frequency: 125MHz

Area: 3mm x 3mm

85

1-mm 2-metal CMOS tech

1.2 x 1.2 mm2

600k transistors

208-pin PGA

fclock = 50 MHz

Pav = 3.6 W @ 5V

Basic Module: Datapath

PADDI-2 (UC Berkeley)

86

RAM

500 k Gates FPGA + 1 Gbit DRAM Preprocessing

Multi-

Spectral Imager

mC

system +2 Gbit DRAM Recog- nition

Ana

log

64 SIMD Processor Array + SRAM

Image Conditioning

100 GOPS

Embedded applications where cost, performance, and energy are the real issues!

DSP and control intensive

Mixed-mode

Combines programmable and application-specific modules

Software plays crucial role

Reuse comes in generations

87

Generation Reuse element Status

1st Standard cells Well established

2nd IP blocks Being introduced

3rd Architecture Emerging

4th IC Early research

Source: Theo Claasen (Philips) – DAC 00

Silicon System Platform

◦ Flexible architecture for hardware and software

◦ Specific (programmable) components

◦ Network architecture

◦ Software modules

◦ Rules and guidelines for design of HW and SW

Has been successful in PC’s

◦ Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)

◦ Speed (compute power)

◦ Dissipation

◦ Costs

◦ Real / non-real time data

88

A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer

New platforms will be defined at the architecture-micro-architecture boundary

They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations

Key to such approaches is the representation of communication in the platform model

89

“Only the consumer gets freedom of choice;

designers need freedom from choice”

(Orfali, et al, 1996, p.522)

Source:R.Newton

90

• 0.25um 6-level metal CMOS

• 5.2mm x 6.7mm

• 1.2 Million transistors

• 40 MHz at 1V

• 2 extra supplies: 0.4V, 1.5V

• 1.5~2 mW power dissipation Interface

Reconfigurable

Data-path

FPGA

ARM8 Core

91

Xilinx Vertex-II Pro

High-speed I/O

Embedded PowerPc Embedded memories

Hardwired multipliers

FPGA Fabric

The selling price of an IC Stotal=Ctotal/(1-m), Ctotal is manufacturing cost for a single IC, m desired profit margin

Costs for produce an IC ◦ Non-recurring engineering costs (NREs)

◦ Recurring engineering costs

◦ Fixed costs

95

Non-recurring engineering costs (NREs) ◦ Engineering design cost ◦ Prototype manufacturing cost

Recurring costs ◦ Process ◦ Package ◦ Test

96

Fixed-costs, e.g. data sheets, application notes

Schedule need to estimate the design cost and design time ◦ The variable costs should be optimized

◦ Additional people in a project delay delivery

Person-power

97

Project management Design reuse Data sheets-Documentation ◦ Summary ◦ Pinout ◦ Description operation ◦ DC specifications ◦ AC specifications ◦ Package diagram ◦ User manual

98

Digital CMOS Design is kicking and healthy Some major challenges down the road

caused by Deep Sub-micron ◦ Super GHz design ◦ Power consumption!!!! ◦ Reliability – making it work Some new circuit solutions are bound to emerge

Who can afford design in the years to come? Some major design methodology change in the making!

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