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Power EstimationXilinx TrainingWelcomeIf you are new to FPGA design, this module will help you estimate your FPGA power consumptionThese design techniques promote fast and efficient FPGA design developmentPerformance (MHz)PMAXPackage PowerLimitReal World DesignPower ConsumptionHigh DensityLowDensityObjectivesAfter completing this module, you will be able to:List the three phases of the design cycle where power calculations can be performedEstimate power consumption by using the XPower Estimator spreadsheetEstimate power consumption by using the XPower software utilityPower Consumption OverviewAs devices get larger and faster, power consumption goes upFirst-generation FPGAs hadLower performanceLower power requirementsNo package power concernsTodays FPGAs haveMuch higher performanceHigher power requirementsPackage power limit concernsA System Monitor that provides active monitoring of the die temperatureRefer to the Virtex-6 User Guide for more informationPerformance (MHz)PMAXPackage PowerLimitReal World DesignPower ConsumptionHigh DensityLowDensityPower Consumption ConcernsHigh-speed and high-density designs require more power, leading to higher junction temperaturesPackage thermal limits exist125 C for plastic150 C for ceramicPower directly limitsSystem performanceDesign densityPackage optionsDevice reliabilityJunction temperature within an FPGA device is a function of the power consumption and thermal resistance of the selected package.Several factors determine power consumption within an FPGA, including supply voltage, system speed, and device utilization.As devices get bigger and faster, power consumption can become a limiting factor in determining device utilization and performance. For example, you may not be able to use all of the resources of a device or run the FPGA as fast as possible without risking reliability problems because of overheating.Estimating Power ConsumptionEstimating power consumption is a complex calculationPower consumption of an FPGA is almost exclusively dynamicPower consumption is dependent on design and is affected byOutput loadingSystem performance (switching frequency)Design density (number of interconnects)Design activity (percent of interconnects switching)Logic block and interconnect structureSupply voltageEstimating Power ConsumptionPower calculations can be performed at three distinct phases of the design cycleConcept phase: A rough estimate of power can be calculated based on estimates of logic capacity and activity ratesUse the Xilinx Power Estimator spreadsheetDesign phase: Power can be calculated more accurately based on detailed information about how the design is implemented in the FPGAUse the XPower AnalyzerSystem Integration phase: Power is calculated in a lab environmentUse actual instrumentationAccurate power calculation at an early stage in the design cycle will result in fewer problems laterEstimating power consumption usually has one of two goals: thermal reliability evaluation or power-supply sizing.The XPower Estimator spreadsheets can be found on the Web at www.xilinx.com/power. It is not included with the ISE software.The XPower Analyzer bridges the gap between the XPower Analyzer and lab measurements by using the implemented design files to estimate power consumption more closely.

Activity RatesAccurate activity rates (also known as toggle rates) are required for meaningful power calculationsClocks and input signals have an absolute frequencySynchronous logic nets use a percentage activity rate100% indicates that a net is expected to change state on every clock cycleAllows you to adjust the primary clock frequency and see the effect on power consumptionCan be set globally to an average activity rate on groups or individual netsLogic elements also use a percentage activity rateBased on the activity rate of output signals of the logic elementLogic elements have capacitance

The device quiescent power (also called static power) is automatically determined depending on the FPGA or CPLD device selected. No input into the XPower Analyzer Analyzer for static power consumption required. This amount represents the power drawn by the device when it is powered up and there is no switching activity. This requires knowing the power supply voltages provided to the FPGA (both core and I/O voltages because they are powered separately) and a simple explanation of the amount of FPGA resources (both logic, dedicated hardware, and routing used) and information about the chosen device family and speed grade.

Dynamic power represents the fluctuating power as your design runs. It represents the amount of power generated by the switching user logic and routing. This is described through an activity rate (also known as toggle rates). For the most accurate information we would need to know the detailed activity rate for each resource in the design. For example, if we had a 16 bit counter, the least significant bit would be switching every rising clock edge and have a 100% toggle rate, while the most significant bit would be toggling far less often. While this may be the most accurate, since we are estimating at the concept stage knowing this kind of detailed would not be beneficial. But knowing this, when we need a better estimate (done later with the XPower utility) we can get more detailed information by loading in a simulation output file (.VCD or SAIF) to get more accurate information.

Xilinx Power EstimatorExcel spreadsheets with power estimation formulas built inEnter design data in white boxesPower estimates are shown in gray boxesSheetsSummary (device totals)Clock, Logic, I/O, Block RAMs, DSP, MMCMGTX, TEMAC, PCIETo download go to http://www.support.xilinx.com -> Technology Solutions -> Power Download the XPE spreadsheet for your device familyXPE is not installed with the ISE softwareThe Power Solutions page has numerous resources

XPower Estimators are a set of Excel spreadsheets that can be found on the Web at www.xilinx.com/power. The spreadsheets support all Xilinx FPGAs. Xilinx Power Estimator

Summary and Quiescent powerWhite boxes allow you to enter design dataGray boxes show you the Power estimatesTabs at bottom allow you to enter power information per device resources (not shown)Settings reviews device, system, and environment informationOn-Chip Power breaks the estimated power consumption into device resources

The device quiescent power (also called static power) is automatically determined depending on the FPGA device selected. This amount represents the power drawn by the device when it is powered up and there is no switching activity.

Xilinx Power Estimator

Summary and Quiescent powerPower Supply reviews what power sources will be necessarySummary describes your systems total power and estimated junction temperature

Xilinx Power Estimator

Clock PowerLogic PowerI/O PowerXilinx Power Estimator

Block RAM, DSP, and MMCM powerXilinx Power Estimator

Power GraphsWhat is the XPower Analyzer?A utility for estimating the power consumption and junction temperature of FPGA and CPLD devicesReads an implemented design (NCD file) and timing constraint dataYou supply activity ratesClock frequenciesActivity rates for nets, logic elements, and output pinsCapacitive loading on output pinsPower supply data and ambient temperatureDetailed design activity data from simulation (VCD file)The XPower Analyzer calculates the total average power consumption and generates a reportThe XPower Analyzer is accurate to within +/ 10 percent, given accurate activity rates. XPower software can only calculate average power and cannot predict power spikes that can occur.

Expand Implement Design Place & RouteDouble-click XPower Analyzer to launch the XPower utility in interactive modeUse the Generate Power Data process to create reports using VCD files or TCL scripts

Running the XPower Analyzer

Summary

Estimated junction temperatureReporting, settings, and thermal information is all placed in one utilityAs you manipulate system characteristics you will update the generated reportReport Navigator allows for quick migration to various reports and functions of the utility

Report Navigator

Thermal Information

Voltage Source InformationSettings

Each box is color coded

Advanced ReportProduced as a simple text fileFile is given .pwr extensionReport is more detailed and stored in one text fileSome what-if analysis information is includedIncludes a Power Improvement Guide

What Next?If you have a problem with your thermal budget there are many things you can considerDetermine which components in your design are using the most powerTry to use as much of the dedicated hardware as possibleReview the Power Improvement Guide section in the Advanced Power ReportEvaluate your activity ratesReduce excess signal power or excess device utilizationSynthesis optionsImplementation tool optionsHDL codeReduce excess static powerAdjust the external environmentSynthesis toolEnable settings which favor power optimization or area minimization. Experiment with synthesis options which affect the design size, the number of signals, or the activity rate. Loosen constraints when possible to limit the number of logic replications. Change mapping thresholds or add constraints to implement more of your logic into dedicated and lower power hardware blocks such as block RAM (BRAM) or DSP elements.Implementation Tools Enable implementation tool settings which favor power optimization. Experiment with the MAP and PAR (Place and Route) options which may affect power, such as options which modify the input netlist, packing, placement, or routing resources used. Loosen constraints when possible to get a more tightly packed design.Design Source CodeEnsure the design code is efficiently written for the targeted device. Code reused from previous or different device generation may be synthesized sub-optimally. Minimize the number of control-sets. Remove asynchronous resets which are typically not necessary in FPGAs.Reduce Excess Static PowerThere is very little you can do with the implementation tools to lower static power. You will most likely need to change the design code or I/O interface.Adjust External Environment Properties Affecting Device PowerAt this stage in the development cycle the printed circuit board is already being designed and the voltage regulators, cooling devices and other device environmental properties are set, so changes you can make in this area are often restricted. It may, however, be possible to supply more cooling or lower the supplied voltages.

SummaryPower calculations can be performed at three distinct phases of the design cycleConcept phase: (Power Estimator spreadsheet)Design phase: (XPower Analyzer)System integration phase: (Lab measurements)Accurate power calculation at an early stage in the design cycle will result in fewer problems laterThe Power Estimator spreadsheet and the XPower Analyzer can be used for estimating the power consumption and the junction temperature of all Xilinx FPGA and CPLD devicesThe Power Estimator and XPower Analyzer uses activity rates to calculate total average power consumptionWhere Can I Learn More?Command Line Tools User Guide: XPower chapterHelp Software Manuals Command Line Tools User Guide Online help from the XPower GUIXilinx Power Solutions Web Pagewww.support.xilinx.com Technology Solutions Power SolutionsGet the XPower Estimator spreadsheets for all Xilinx devices7 Steps to Worst Case Power Estimation, WP353Spartan-6 Power Management User Guide, UG394Power Consumption at 40 and 45 nm, 298Application Notes: Help Xilinx on the Web Xilinx Application NotesApplication Note XAPP158: Powering Xilinx FPGAsXilinx Education Services courseswww.xilinx.com/trainingXilinx tools and architecture coursesHardware description language coursesBasic FPGA architecture and other topics (free Videos!)Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

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