post layout em simulation for signal integrity verification · 2009-08-04 · post layout...

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Post Layout EM Simulation for Signal Integrity Verification

Post Layout Simulation in ADS2

Agenda

• Introduction to Fast Channel Simulation for Pre Layout Design • Introduction to SAS Specifications• Post Layout Extraction and Simulation of SAS/SATA Board & Backplane• Eye Diagram Simulation with Transmit Equalization• Receive Equalization at 6 Gbps using ADS2009 Update 1


Channel System Architecture

• Basic components: transmitter, channel, receiver and crosstalk

• Rise and fall edges of each bit are modulated by various jitters


Eye Diagram and BER

• Eye opening is determined by jitter and crosstalk.


Different Jitter Type• Inter-symbol-interference (ISI): caused by channel dispersion.

• Duty-cycle-distortion (DCD)

1 0 1 1 0

t

ideal edge

DCD

ISI

• Periodic jitter (PJ): due to modulation (AM, PM & FM), power switching and period EMI source.

• Random jitter (RJ) in Tx

• RJ in Rx sample time


Crosstalk

• Crosstalk is caused by coupling between forward and crosstalk channels.

Tx channel

Xtlk channelcoupling

Output

• Synchronous crosstalk: relative signal phase between Xtlk & Tx is fixed

• Asynchronous crosstalk: signal phase is random relative to Tx

Tx Emphasis

post-cursor

main cursorpre-cursor

t

LL +∆−+∆−++∆++= − )2()()()()( 2101 tVatVatVatVatV ininininout

Before emphasis After emphasis


Rx Equalizer

L+−+−+= )2()()()( 210 TtVaTtVatVatV inininout

• Continue-time-equalizer (CTE): pole-zero

• Feed-forward-equalizer (FFE)

L

L

))(())(()(

11

21

pspszszsAsH

−−−−

=

Before EQ After EQ



Challenges in Signal Integrity Simulation

• Extremely low BER.• Reliable statistics require samples of millions of bits.

Regular transient simulation is impractical.• Account for different types of jitter: ISI, DCD, PJ & RJ.• Tx and Rx equalizers.• Effects of crosstalk channels.• Optimization of channel and equalizer.

ADS Channel Simulator: An Integrated Solution for SI Designs

Subst1Dielectric-i : ER[i], H[i], TAND[i]

Metal-i : T[i], COND[i], TYPE[i]

Metal-2

Metal-1

Dielectric-1TL2

TL1

blahblah_1ModelType=MW

Via2

Via1

S4PSNP1

4

1 2

3 Ref

ML2CTL_VCLin1

TX2

TX_CLKB TXN_NEAR

TXP_NEARTX_CLK

TxDriver

RX1

RXN

RXP

RX_INN

RX_INP

RxAmp

EyeDiff_ProbeEyeDiff

V+

V-



Simulation Technologies: Superposition in LTI Systems

• Response of single bit.

• Response of multiple bits.

Superposition

ISI


Simulation Techniques

• Assume LTI system.

• Channel characterization: run transient to calculate step response S(t) of Txchannel and each Xtlk channel.

• Include Tx and Rx equalizers in S(t).

• Bit-by-bit superposition of pulse response of Tx and Xtlk bits.

)]()([)]()([)( jXtlkjj

XtlkiTxii

Txout tftSrttStftSrttStv −−−+−−−= ∑∑

• ISI is included in superposition.

• Rise time tr and fall time tf are modulated by DCD, PJ and RJ.


Asynchronous Crosstalk

)()()(),(),( 21

21

voverconvolvevpvptvptvpvvvv

XtlkXtlkTxout

XtlkXtlkTxout

∗∗=++=

Phase between TX and Xtlk is random

• Average Xtlk PDF over UI

• Convolve Tx PDF with averaged Xtlk PDF

Rx Random Jitter• Rx jitter smears sample time

• Equivalent to averaging PDF with Gaussian kernel along time axis

)()(),()(),(),( toverconvolvetgtvpdgtvptvp ininout σσ τττ ∗=+= ∫


SAS-2 SpecificationsThe SAS-2 6Gb/s Rx/ Tx requirements assumption

Data Rate 6Gb/s Transmitter

Differential Amplitude mV(p-p) 800 –1200 Return loss dB < 6a at 3GHz Recommenced Rise/Fall time 20-80% ps > 30 Differential impedance Ohm 100Ohm +/-15% DJ UI < 0.15 RJ, CDF level 1e-15 UI < 0.15

Transmitter- Equalizer 1-tap post cursor de-emphasis with gain dB < 6dB

Receiver Return loss dB <6a Differential impedance Ohm 100 +/-15%b Equalized eye amplitude mV(p-p) > 100 TJ, CDF level 1e-15 UI < 0.6

Rx-Equalizer DFE with number of taps (or equivalent in performance FIR filter) - 5 Adaptability Yes Limit for the sum of DFE taps for Tx =1Vpp, absolute value Vpp 0.263


Compliance Mask Specifications


Challenges for Post Layout Simulation

• Complex multilayer board• Long trace lengths (typically 3” to 17” or more)• 4 to 40 layer stack-up• Multiple power and ground planes

• Complex via structures• Long via stubs• Crosstalk and impedance mismatch

• EM Simulation• Accuracy• Time and memory requirement


SAS/SATA Channel

Plug in Unit

BackplaneConnector


SAS/SATA Channel

FCI 10039851-101LF FC

I

100

4354

6-10

1LF

Vite

sse

VS

C71

57-0

2 ex

pand

er (U

12)

PIU Left Side Via Transition

Drive_2_RX

Drive_2_TX

PIU Right Side Via Transition

Backplane Left Side Via Transition

Backplane Right Side Via Transition

Backplane Differential Trace –Layer 12

Backplane Differential Trace –Layer 12


Plug in Unit Card

Critical net ExtractionDRIVE_12_C_TX_PDRIVE_12_C_TX_NDRIVE_12_C_RX_PDRIVE_12_C_RX_N


Allegro/APD to ADS Flow

APD/Allegro Momentum Export Setup

Select Critical Netsor Entire Layout Select Stackup Layers

Cookie-cut Power and Ground Planes Portion

Create Ports Export to ADS Layout

Import in ADS Layout Ground Ref Port Adjustments if required

Verify Layout using 3-D Preview and Simulate


Export Setting

• Default settings – Fine setting A– Fine setting B– Medium setting– Coarse setting

• User defined settings– Change in arc resolution– Bring signal via as is and convert gnd via

to rectangular– Remove non-functional pads– ...


Simulation MethodologyBoard File

Critical nets Extraction using

Allegro DFI

ADS Import

Crop Via Portion

Run EMDS

Board File

Critical nets Extraction using Allegro DFI with stack-up limited

between PWR/GND

planes

Crop Diff pair portion

Run Momentum RF

For board/backplane post layout analysis take advantage of board layout properties

ADS Import

EMDS

EMDS

Momentum RF


What is Momentum?

• Method of Moments simulator for restricted 3D passive circuits

• Frequency Domain• Uses precomputed Green’s functions for faster EM

simulations than full 3D simulators can achieve• Layout driven (accepts arbitrary geometry)• Visualization of current and far-field patterns• Layout Components for ADS schematic• Co-simulation/Co-optimization with circuits/systems


Application Overview

• 3D CircuitComponents - LTCC- Embedded

passives

• Packages andInterconnects

• Circuit- System-3DEM Co-simulation


EMDS-G2 TechnologyFinite Element Method (FEM)

Generate mesh of triangles on ports and tetrahedrons in 3D spaceCompute Port modes and use as excitation for 3D structureApproximate electric field over each tetrahedron with a second-order polynomial containing unknown coefficientsSolve resulting matrix to determine values for the polynomial coefficientsDerive S-parameters


PIU Left Side Via Simulation

Positive Pwr/Gnd were converted to slot layers


Left Side Via -3D Preview

PIU Left Side Via using Momentum MW Mode Simulation


EMDS Simulation of PIU Left Side Via

EMDS Plot

Momentum Plot

Comparison of simulation results


Comparison on Via Simulation Results

EMDSMomentum MW

Momentum RF

RF mode provide good performance

Momentum MW mode or EMDS is essential


Drive_12_TX Nets

Differential pair brought in with stack up reduced to top ground


Drive_12_TX Nets – Simulation Results

2 4 6 8 10 12 14 16 180 20

-60

-40

-20

-80

0


Drive_12_RX : Receive Nets

The differential pair was limited to upper power plane. The Bottom layer was an open substrateAllegro DFI Setup can be used to limit differential pair stack up between top and bottom gnd planes


Drive_12_RX Net Simulation Results

2 4 6 8 10 12 14 16 180 20

-60

-40

-20

-80

0


EDOB Right Side Via


Connector Models

Connector S-parameter files were provided


Backplane Simulation

Left side via

Right side viaBackplane trace


Layout Modifications for Via Simulation

• Select all• Using Edit > Modify >Crop • Select a rectangular window

around differential via with adjacent ground via

Number of layers : 32 (dielectric+ conductor+pwr/gnd)

Negative planes : No

Number of Pwr/Gnd planes : 8


Backplane Left Side Via Models

Gnd Via

Signal Via


Converting Positive Layers to Slot Layers

Boolean operation is used to convert finite Pwr/Gnd planes in slot layers

Provide speed advantage for Momentum simulation and overcome any resonance due to finite power ground planes shapes

Modify stack up for slot layers

ADS2009 Update will provide automatic conversion from +ve to –ve planes


Comparison of Two Models

Finite PWR/GND Plane Metallization

PWR/GND Plane Modeled as Slot Layer


Simulation Statistics

Notice that the non-functional have been removed from all other layers except two signal layers


Left Side Backplane Via Simulation Results

Slot layer view of the structure

Momentum S-parameter plots


Backplane Differential Trace – Layer 12

Via portion at both end were cut out and simulated separately. The traces were imported by limiting the differential pair within adjacent PWR/GND planes


Backplane Differential Trace Simulation- Layer 12

Mesh Frequency : 20 GHz

Edge Mesh : ON


Backplane Differential Trace – Layer 14

Via portion at both end were cut out and simulated separately. The traces were imported by limiting the differential pair within adjacent PWR/GND planes


Backplane Differential Trace – Layer 14 Simulation Results

Mesh Frequency : 20 GHz

Edge Mesh : ON

Mesh Density : 20 C/W


Right Side Backplane Via Extraction and 3 D Preview

Non Functional PADS were removed


Right Side Via Simulation- Results

Insertion Loss Plots


Complete Channel Model


Channel Model- S Parameter Simulation

2 4 6 8 10 12 14 16 180 20

-60

-50

-40

-30

-20

-10

-70

0

freq, GHz

dB(S

(1,2

))dB

(S(4

,3))

dB(S

(1,1

))dB

(S(2

,2))


Eye Diagram Simulation @ 3Gbps


Eye Diagram Simulation @ 3Gbps with 3.5 dB De-emphasis

Eye diagram acceptable with 3.5 dB TX de-emphasis


Eye Diagram Simulation @ 6Gbps

Transmit de-emphasis may be required to open eye


Eye Diagram Simulation @ 6Gbps with 3.5 dB De-emphasis

55

ADS 2009 Update 1


What’s New in ADS2009 Update 1?

• Decision Feed Back Equalization• Ability to auto generate optimized tap coefficient for FFE and DFE• Adaptive Equalization for FFE and DFE utilizing LMS,RLS, ZF • Arbitrary eye mask display and automatic positioning within eye diagram• Statistical simulator Integrated within Channel Simulator


SAS/SATA Channel @ 6Gbps with Optimized FFE/DFE

Equalized receiver utilizing:FFE: 1 precursor

2 post cursor DFE: 3 Tap DFE

Optimized coefficients are auto generated and can be stored in a fileNumerous ways to define/calculate tap coefficients


Standard Mask Definition

•Convenient eye mask display

•Flexible specification format compatible with Agilent scopes

•Browse and select any arbitrary mask file and preview

•Mask is automatically position within eye diagram across timing and amplitude axis

Sample Eye Mask


Statistical Eye Contours and Bathtub @ 6Gbps

SAS/SATA Eye diagram and Bathtub plots

Channel Simulator Updates

Statistical analysis option in the Channel Simulator for fast simulation down to very low BER

Agilent’s proprietary technology extends StatEye principles

Height at BER

Width at BER

Contour at given BER

ChannelSimChannelSim1

EnforcePassivity=yesToleranceMode=AutoNumberOfBits=1000

ChannelSim



Summary

• Discussed channel simulation requirements• Established an efficient high data rate post layout extraction flow• Introduced channel simulation and how if could be using for post layout

verifications• Introduced new capabilities of ADS2009 Update 1 for channel analysis

post layout em simulation for signal integrity verification · 2009-08-04 · post layout...

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