UCSB HEP ASIC Class Slide 1

CMOS Circuit Design, Layout and Simulation

Sam Burke

UCSB HEP Group

UCSB HEP ASIC Class Slide 2

References

• Text CMOS Circuit Design, Layout, and Simulation by R. J.

Baker, Li and Boyce IEEE Press Oct 2002 ISBN-81-203-1682-7

• URL http://cmosedu.com/cmos1/book.htm

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The Well

• P Type Wafer boron acceptor atoms (25

ohm*cm)

• Transistors Nmos Transistors on p-

substrate Pmos Transistors on n-well

• Diode formed between the n-well

and p-substrate

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Historical Methods

• Point Contacts 1948

• Grown Junctions 1950

• Alloy Junctions 1952

• Planar Technology or Junction Technology 1953

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A Little History

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Patterning

• Start with clean bare wafer

• Grow Oxide wet oxide dry oxide

• Apply Resist

• Photo-resist pattern

• Expose

• Develope

• Etch to remove oxide

• Ready for Diffusion

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Growing an N-Well

• Donor Atom Diffusion Donor valance=5

– Phosphorus Si valance=4

• N Well Resistivity 0.75 ohm*cm

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The N-Well

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The Well Resistor• R=[p/t]*L/W

R=Resistance p=resistivity

• R=Rsq*L/W Rsq=sheet resistance

(ohm/square)

• For N-Well p=0.75ohm*cm t=3um L=100um W=10um R=2500*100/10=25kohms

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Si Resistivity

• Experimental Data N-Type

donor concentration shown for resistor example

• Ref: Grove, A.S “Physics and Tech - -

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N-Well Cross Section

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L-Edit

• Demo the creation of an N-Well using L-Edit Error checking

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Design Process

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Well and Contacts

• N-Well contact on left metal1 active

• Bulk contact on right metal1 active P Implant

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PN Junction Depletion

• Carrier drift

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PN Junction Voltage

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Diode Junction Capacitance

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Diode V/I Equation

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Forward Biased Diode

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S-Edit

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T-Spice

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Net List of Diode Circuit

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Diode Storage Time