planting of carbon nanotubes on nano-textured and micro-structured silicon substrates

Planting of Carbon nanotubes on nano-textured and micro-structured silicon substrates

S. Taak, Sh. Rajabali S. Darbari, M. Poudineh, Z. Sanaee and S. Mohajerzadeh,

Thin Film and Nano-Electronic Laboratory,

Faculty of Electrical and Computer Engineering,

University of Tehran, Tehran, Iran

In this work we have developed a novel method to place previously grown CNTs on desired nano-textured and micro-machined substrates. Once the desired structures are created on a given substrate (silicon here) the already grown nanotubes are planted on the created holes either by a mechanical rubbing or solution dispersing approach. The main idea of this work is to plant partially vertical nanostructures on textured substrates.

Introduction

Carbon nanotubes are promising candidates for field emission applications where the sharp points of their tip enhance the local electric field. This enhanced field yields in a significantly higher emission current which is a favorable effect in field emission displays and devices. Since the growth of CNTs requires high temperature processing steps, the use of substrates is limited.

In this paper a novel method is introduced to place previously grown CNTs on desired nano-textured or micro-machined substrates. At this stage, only silicon substrate is used, although other materials can be examined. The process constitutes of the texturing of the silicon substrates by means of deep reactive ion etching. This process can be performed on desired places and in desired shapes. Figure 1 shows the SEM images of nano-textured surfaces.

Figure 1.Texturing of silicon surfaces using deep reactive etching. Sharp conical structures are obtained.

Apart from texturing the silicon surface, the process employs carbon nanotubes which can be obtained by vertical alignment of CNTs on silicon surfaces, as seen in Figure 2. As seen from this figure, the tip of the CNTs contains Ni which has been acting as the seed for the initial growth.

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Figure 2.SEM image of carbon nanotubes, grown on silicon substrates. These nano-structures can be employed to be planted on secondary surfaces either in a random dispersion method or by an ordered arrangement.

To improve the field emission properties, branched CNTs can be used. Figure 3 depicts the micro-graph of the highly branched structures on desired patterns on silicon substrates. Such branched CNTs are most suitable for field emission applications. The field emission data are presented in the right side of this figure.

Figure 3.SEM image of highly branched structures. The field emission electrical measurements show the superior performance of such structures compared to normal CNTs.

Once the substrate surface is textured, normal or branched CNTs can be placed on desired places using a mixture of CNT dispersed in Di-methyl-formamide (DMF) solution. A sonication step is required to ensure that carbon nanotubes are entrapped between partially vertical/conical silicon textures [1]. Figure 4 shows the entrapment of CNTs on highly textured silicon surface where partial vertical planting is observed.

ECS Transactions, 45 (20) 57-62 (2013)



Figure 4. The planting (entrapment) of CNTs on highly textured surfaces and in a rather random fashion. Some of CNTs are placed vertical while some of them are layed down. Arrows show the partial vertical entrapment of CNTs on Si textures.

Figure 5. Schematic drawing for carbon plantation. (top) Etching of the substrate. (bottom) planting of CNTs in the desired places. SEM image shows typical features obtained which are suitable for this CNT-planting process.

As observed from Figure 4, the chance of vertical planting of CNTs is limited if a highly textured surface is used. To improve the planting performance, a micro-machining process is being practiced where the preliminary scheme is presented in Figure 5. Starting with highly ordered patterns on silicon substrate (or any other substrate), deep holes are obtained. By means of sonication of CNT-holding solution, the chance of their planting is improved and highly vertical yet ordered structures are expected.. This process can also be repeated on glass substrates.

Fabrication Procedure

Using RCA#1, p-type silicon wafers are cleaned (NH4OH: H2O2: H2O; 1:1:5) and blow dried. Figure 6 describes the fabrication procedure for this investigation. The prepared wafers are oxidized. The oxidization could be dry oxide or wet oxide. After this step, a protective Cr layer is deposited on the oxidized substrates by means of an electron beam evaporation system. The thickness of the Cr is between 20 to 40nm. Then the Cr is patterned by using a mask of holes, with the hole sizes of almost 2µm. As we use standard photo-lithography the minimum feature size which can be obtained is 1µm and for having structures under 1µm, we have to use other kinds of lithography, such as polystyrene nano-sphere




lithography (NSL), which has been practiced in order to obtain hole sizes under 1µm.After patterning of the holes, the oxide layer in holes must be removed. The removal process is possible through a DC-PECVD method as described in [2]. The main point of using this method in comparison with HF solution is the vertical removal of the oxide using hydrogen and C2H2 plasma. Then to complete the process, one has to etch away silicon inside the patterns which is achieved through RIE (Reactive Ion Etching) as reported elsewhere [3].The etching is done in 2 sub-sequences. The first sub-sequence is the etching step where by using plasma of SF6, silicon is etched. To ensure a vertical etching, the etched layer must be passivated in the next step to avoid undesired underetching. The passivation process is done using plasma of O2 and H2 with a trace value of SF6. By repeating these steps, deep vertical features are obtained.

Figure 6. (a) Silicon substrate, (b) The silicon is oxidized, (c) Deposition of chromium layer, (d) Lithography of chromium and patterning holes, (e) Removal of Oxide using hydrogen plasma, (f) Etching

of Si with RIE, (g) Planting CNTs in the holes.

Results and Discussions

Figure 7 demonstrates the evolution of vertical holes in silicon substrates as described in the previous sections. These holes can be exploited for planting CNTs in a near vertical fashion. The previously grown CNTs are prepared for being planted in patterned-substrates. CNTs are grown through a DC-PECVD method. In order to prepare the CNTs to be transferred to the hole-substrate structure, they must be unattached from their main substrates which can be achieved using a reactive ion etching unit. The use of plasma of SF6 in a very short time weakens the attachment of CNTs to their silicon substrates. The weak CNTs could be planted in the hole-substrate. Two processes were used for this purpose, which are solution method and mechanical rubbing. Using the former approach, a solution such as Di-methyl-formamide (DMF) is used as the transferring medium, which places the CNTs in holes. Using this method a bunch of CNTs are planted in the micro-structured holes, which is not desired. We wish to place the CNTs separately. In order to approach this purpose, another method which is mechanical rubbing is used. In this process the unattached CNTs are rubbed against the hole-substrate, so the CNTs are transferred into the holes, because these holes make a rough surface, suitable for planting the CNTs.




Figure 7. The holes are patterned and etched.

If smaller features and holes are required, a nano-sphere lithography is used where polyestyrene spheres are spred on a silicon surface. By means of a lift-off process it is possible to transfer the circular shape of the spheres onto a silicon substrate to be further processed to realize high aspect ratio deep holes. In Figure 8 one can see the results of small (nano-size) holes which have been realized on silicon substrates using NSL method.

(a) (b) Figure 8.(a) The formation of nano-sized holes by a lift-off process using polystyrenes Nano-Sphere

lithography, (b) High precision deep etching of nano-sized holes. The depth of individual holes is 1 µm.

(a) (b) (c)

Figure 9.CNTs planted in (a) larger holes, (b) and (c) smaller holes in a near vertical fashion. Arrows show the planting of CNTs within the holes.




The Planted CNTs in holes are illustrated in Figure 9. Part (a) shows the presence of planted nanotubes just inside the holes while in parts (b) and (c) one can see closer views of the CNTs. The holes are micro-sized and nano-sized. For larger holes, CNTs are not placed in the desired fashion, whereas for smaller holes, the vertical placement of CNTs is quite evident from these images. Finally the field emission test of these structures is done using a Keithley 2361 parameter analyzer. The output of the test is current versus voltage. This test is done in a vacuum of 10-2Torr. The distance between anode and cathode is approximately 170µm. The current-voltage diagram is presented in Figure 10.

Figure 11. The current-voltage characteristics of the CNTs, indicating a sharp rise in the emission current with the applied voltage.

Summary and Conclusion

In this work, we have studied the planting of carbon nanotubes in a near vertical fashion and in desired placed. This post-growth planting is suitable for the formation of field emission devices on any substrate including silicon wafers. In addition, we have investigated the field emission effect of CNTs from planted structures. It has been observed that the field emission is enhanced if they are isolated from each other to minimize the screening effect. The evolution of highly vertical features on silicon is underway.

Acknowledgement

Authors wish to acknowledge the technical assistance of Ms. S. Mohammadi. The financial support of the research council of the University of Tehran is cordially appreciated.

References 1. M. Mehran, Z. Kolahdouz, Z. Sanaee, S. Azimi and S. Mohajerzadeh, Eur. Phys. J. Appl. Phys.

55, 11302 (2011). 2. M. Abdolahad, J. Naghsh-nilchi and S. Mohajerzadeh, “Fluorine-free high resolution selective

etching of Silicon-oxide layers on silicon substrates”, Journal of Physics, D, vol. 43, number 395402 (2010).

3. Z. Sanaee, M. Poudineh, M. Abdolahad and S. Mohajerzadeh, “High aspect ratio micro- and nano-machining of silicon using time-multiplexed reactive ion etching” , Journal of Micromechanics and Microengineering, Vol. 21, number 12 , p. 125012, 2011.




planting of carbon nanotubes on nano-textured and micro-structured silicon substrates

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