place decap

15
nning is basically the arrangement of logical blocks (i.e. mu gates, buffers) on silicon chip.

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https://www.udemy.com/vlsi-academy http://vlsisystemdesign.com/place_decap.php Once the critical cells are placed on the chip, it becomes necessary to surround the critical cells by decoupling capacitors. The placement of de-coupling capacitors surrounding the pre-placed cells improves the reliability and efficiency of the chip.

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Page 1: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

Page 2: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells

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Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio

Page 4: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Define locations of pre-placed cells

Page 5: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Place de-coupling capacitors surrounding pre-placed cells

Page 6: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• Power Planning

Page 7: Place decap

Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

It is attained by following steps:

• IO Pin/Pad placement

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• We have defined the Width and Height of the core.

• Also defined the locations of pre-placed cells

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Block a Block b

Block c

Core

Die

Pre-placedCells

W

H

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• We have defined the Width and Height of the core.

• Also defined the locations of pre-placed cells

• We need to encapsulate the Pre-placed Cells by Decoupling capacitor .

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04/12/2023 11

• A decoupling capacitor is used to decouple the pre-placed cells from main power supply, in order to protect the cells from the disturbance occurring in the power distribution lines and source

• The purpose of using decoupling capacitors is to deliver required current to the gates during switching

Decoupling capacitor encapsulate the Pre-placed Cells

Page 12: Place decap

Block a Block b

Block c

Core

Die

Pre-placedCells

DECAP1

Page 13: Place decap

Block a Block b

Block c

Core

Die

Pre-placedCells DECAP2

DECAP1

Page 14: Place decap

Block a Block b

Block c

Core

Die

Pre-placedCells DECAP2

DECAP1

DECAP3

Page 15: Place decap

Block a Block b

Block c

Core

Die

Pre-placedCells DECAP2

DECAP1D4

DECAP3