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William StallingsComputer Organizationand Architecture7 th Edition

Chapter 3System Buses

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Program Concept

Hardwired systems are inflexible General purpose hardware can do

different tasks, given correct controlsignals

Instead of re-wiring, supply a new set of control signals

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What is a program?

A sequence of steps For each step, an arithmetic or logical

operation is done For each operation, a different set of

control signals is needed

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Function of Control Unit

For each operation a unique code isprovidede.g. ADD, MOVE

A hardware segment accepts the code and

issues the control signals

We have a computer!

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Components

The Control Unit and the Arithmetic andLogic Unit constitute the CentralProcessing Unit

Data and instructions need to get into the

system and results outInput/output

Temporary storage of code and results isneededMain memory

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Computer Components:Top Level View

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Instruction Cycle

Two steps:FetchExecute

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Fetch Cycle

Program Counter (PC) holds address of next instruction to fetch

Processor fetches instruction frommemory location pointed to by PC

Increment PCUnless told otherwise

Instruction loaded into InstructionRegister (IR)

Processor interprets instruction andperforms required actions

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Execute Cycle

Processor-memorydata transfer between CPU and main memory

Processor I/OData transfer between CPU and I/O module

Data processingSome arithmetic or logical operation on data

Control

Alteration of sequence of operationse.g. jump

Combination of above

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Characteristics of Hypothetical Machine

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Example of Program Execution

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Instruction Cycle State Diagram

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Interrupts

Mechanism by which other modules (e.g.I/O) may interrupt normal sequence of processing

Program

e.g. overflow, division by zero Timer

Generated by internal processor timerUsed in pre-emptive multi-tasking

I/Ofrom I/O controller

Hardware failure

e.g. memory parity error

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Classes of Interrupts

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Program Flow Control

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Interrupt Cycle

Added to instruction cycle Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction

If interrupt pending:Suspend execution of current programSave context

Set PC to start address of interrupt handlerroutineProcess interruptRestore context and continue interrupted

program

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Transfer of Control via Interrupts

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Instruction Cycle with Interrupts

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Program TimingShort I/O Wait

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Program TimingLong I/O Wait

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Instruction Cycle (with Interrupts) -State Diagram

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Multiple Interrupts

Disable interruptsProcessor will ignore further interrupts whilst

processing one interruptInterrupts remain pending and are checked

after first interrupt has been processedInterrupts handled in sequence as they occur

Define prioritiesLow priority interrupts can be interrupted by

higher priority interruptsWhen higher priority interrupt has been

processed, processor returns to previousinterrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts Nested

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Time Sequence of Multiple Interrupts

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Connecting

All the units must be connected Different type of connection for different

type of unitMemory

Input/OutputCPU

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Computer Modules

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Memory Connection

Receives and sends data Receives addresses (of locations) Receives control signals

Read

WriteTiming

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Input/Output Connection(1)

Similar to memory from computersviewpoint

OutputReceive data from computer

Send data to peripheral Input

Receive data from peripheralSend data to computer

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Input/Output Connection(2)

Receive control signals from computer Send control signals to peripherals

e.g. spin disk

Receive addresses from computer

e.g. port number to identify peripheral Send interrupt signals (control)

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CPU Connection

Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

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Buses

There are a number of possibleinterconnection systems

Single and multiple BUS structures aremost common

e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

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What is a Bus?

A communication pathway connecting twoor more devices

Usually broadcast Often grouped

A number of channels in one buse.g. 32 bit data bus is 32 separate single bit

channels

Power lines may not be shown

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Data Bus

Carries dataRemember that there is no difference between

data and instruction at this level

Width is a key determinant of

performance8, 16, 32, 64 bit

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Address bus

Identify the source or destination of data e.g. CPU needs to read an instruction

(data) from a given location in memory Bus width determines maximum memory

capacity of systeme.g. 8080 has 16 bit address bus giving 64k

address space

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Control Bus

Control and timing informationMemory read/write signalInterrupt requestClock signals

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Bus Interconnection Scheme

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Big and Yellow?

What do buses look like?Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boards

e.g. PCI

Sets of wires

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Physical Realization of Bus Architecture

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Single Bus Problems

Lots of devices on one bus leads to:Propagation delays

Long data paths mean that co-ordination of bus usecan adversely affect performance

If aggregate data transfer approaches bus capacity

Most systems use multiple buses toovercome these problems

Traditional (ISA)

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Traditional (ISA)(with cache)

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High Performance Bus

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Elements of Bus Design

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Bus Types

DedicatedSeparate data & address lines

MultiplexedShared lines

Address valid or data valid control lineAdvantage - fewer linesDisadvantages

More complex control

Ultimate performance

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Bus Arbitration

More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one

time

Arbitration may be centralised ordistributed

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Centralised or Distributed Arbitration

CentralisedSingle hardware device controlling bus access

Bus Controller Arbiter

May be part of CPU or separate

DistributedEach module may claim the busControl logic on all modules

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Timing

Co-ordination of events on bus Synchronous

Events determined by clock signalsControl Bus includes clock line

A single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an event

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Synchronous Timing Diagram

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Asynchronous Timing Read Diagram

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Asynchronous Timing Write Diagram

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Bus Data Transfer Types

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PCI Bus

Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines

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PCI Bus Lines (required)

Systems linesIncluding clock and reset

Address & Data32 time mux lines for address/data

Interrupt & validate lines Interface Control Arbitration

Not sharedDirect connection to PCI bus arbiter

Error lines

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PCI Bus Lines (Optional)

Interrupt linesNot shared

Cache support 64-bit Bus Extension

Additional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit

transfer

JTAG/Boundary ScanFor testing procedures

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Typical desktop system

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Typical server system

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Mandatory PCI Signal Lines

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Mandatory PCI Signal Lines

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Optional PCI Signal Lines

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PCI Commands

Transaction between initiator (master)and target

Master claims bus Determine type of transaction

e.g. I/O read/write Address phase One or more data phases

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Interpretation of PCI Read Commands

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PCI Read Timing Diagram

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PCI Bus Arbiter

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PCI Bus Arbitration

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Foreground Reading

Stallings, chapter 3 (all of it) www.pcguide.com/ref/mbsys/buses/

In fact, read the whole site!

www.pcguide.com/