physical and opto electronics-mosfet

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Sri Lanka Institute Of Information Technology Lab 7 EC304 – hysical an! O"to Electronics Name : H.M.N.S.S.B Herath Registered No : EN13530518 Course : BSc in Engineering Fied o! S"eciai#ation : Eectrica and Eectronic Engineering

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MOSFET Transistor

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Sri Lanka Institute Of Information Technology

Lab 7EC304 Physical and Opto ElectronicsName

: H.M.N.S.S.B Herath

Registered No

: EN13530518

Course

: BSc in Engineering

Field of Specialization: Electrical and Electronic Engineering

AbstractThe purpose of this lab is to explore the operation ofMOSFETs. The operation of the MOSFET will be investigated under the DC operation conditions. And to analyse characteristics of a MOSFET by measuring VDS, VGS and ID.Introduction

The metaloxidesemiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figure 1 shows the schematic diagram of the structure of an nMOS device before and after channel formation.

Output Characteristics of a MOSFET

The characteristics of an nMOS transistor can be explained as follows. As the voltage on the top electrode increases further, electrons are attracted to the surface. At a particular voltage level, which we will shortly define as the threshold voltage, the electron density at the surface exceeds the hole density. At this voltage, the surface has inverted from the p-type polarity of the original substrate to an n-type inversion layer, or inversion region, directly underneath the top plate as indicated in Fig. 1. This inversion region is an extremely shallow layer, existing as a charge sheet directly below the gate. In the MOS capacitor, the high density of electrons in the inversion layer is supplied by the electronhole generation process within the depletion layer. The positive charge on the gate is balanced by the combination of negative charge in the inversion layer plus negative ionic acceptor charge in the depletion layer. The voltage at which the surface inversion layer just forms plays an extremely important role in field-effect transistors and is called the threshold voltageVtn. The region of output characteristics whereVGSVt) ID vs VDS measurements obtained.

ID vs VDS graphs plotted in same axis for different VGS values.

Trans-conductance gm was obtained from the graph.

Results

N-Channel Mosfet

VGS (V)ID (mA)

2.60.1*10-3

2.80.5*10-3

3.04.5 *10-3

3.236*10-3

3.4260*10-3

3.61.56

3.815.64

4.032.63

4.266.15

4.4109.4

4.6118.1

4.8120.8

5.0121.8

5.2122.5

5.4123.0

5.6123.2

6.0123.7

6.5124.2

7.0124.5

8.0124.8

9.0124.9

10.0125.0

ID vs VGS graph

From the graph,

Threshold voltage Vt = 2.8V

VGS = 3V

VDS (V)ID (mA)

2.80.5*10-3

3.04.0*10-3

3.238.9*10-3

3.4204.0*10-3

3.61.37

3.827.83

4.044.8

4.277.1

4.4213

4.6255.2

4.8255.3

5.0255.5

5.5255.8

6.0255.9

VGS = 5V

VDS (V)ID (A)

2.60.1*10-3

2.80.7*10-3

3.04.3*10-3

3.243.8*10-3

3.4329.1*10-3

3.62.10

3.832.3

4.0110

4.2150

4.4275.5

4.6275.5

4.8275.6

P-Channel Mosfet

VGS (V)ID (mA)

2.60.1*10-3

2.80.5*10-3

3.05.8 *10-3

3.234.9*10-3

3.4652*10-3

3.613.77

3.841.3

4.094.6

4.2118.2

4.4120.6

4.6122.6

4.8123.3

5.0124.0

5.2124.4

5.4124.5

5.6124.8

6.0124.9

6.5125.2

7.0125.4

8.0125.8

9.0125.9

10.0126

ID vs VGS graph

From the graph,

Threshold voltage Vt = 2.9V

VGS = 3V

VDS (V)ID (mA)

2.60.1*10-3

2.80.3*10-3

3.05.6*10-3

3.2163.4*10-3

3.41.25

3.68.37

3.856.4

4.0112.2

4.2255.4

4.4255.4

VGS = 5V

VDS (V)ID (A)

2.60.1*10-3

2.81.0*10-3

3.04.1*10-3

3.290.2*10-3

3.41.26

3.66.66

3.892.3

4.0150.9

4.2265.2

4.4265.5

Figure 1

Fig 2

Fig 3