pentek digital

11111

Digital RDigital RDigital RDigital RDigital Receiver Handbook:eceiver Handbook:eceiver Handbook:eceiver Handbook:eceiver Handbook:Basics of Software RBasics of Software RBasics of Software RBasics of Software RBasics of Software Radioadioadioadioadio

PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc. � One Park Way, Upper Saddle River, NJ 07458 � Tel: (201) 818-5900 � Fax: (201) 818-5904 � Email: [email protected] � http://www.pentek.com

Digital Receiver Handbook:Basics of Software Radio

Fourth Edition

PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 � Fax: (201) 818-5904Email: [email protected] � http://www.pentek.com

Copyright © 1998, 2001, and 2003 Pentek Inc.All rights reserved.

Contents of this publication may not be reproduced in any form without written permission.Specifications are subject to change without notice.

Pentek, GateFlow and VIM are a registered trademarks of Pentek, Inc.

TheorTheorTheorTheorTheory of Operationy of Operationy of Operationy of Operationy of Operation

ApplicationsApplicationsApplicationsApplicationsApplications

PPPPProductsroductsroductsroductsroducts

by

RRRRRodger Hodger Hodger Hodger Hodger H. Hosking. Hosking. Hosking. Hosking. HoskingVice-President & Cofounder of Pentek, Inc.

®

22222



Preface

Digital receivers have revolutionized electronic systems for avariety of applications including communications, data acquisition and signal processing.

This handbook shows how digital receivers, the fundamental building block for software radio,can replace conventional analog receiver designs, offering significant benefits in performance, density and cost.

In order to fully appreciate the benefits of digital receivers a conventional analog receiversystem will be compared to its digital receiver counterpart, highlighting similarities and differences.

The inner workings of the digital receiver will be explored with an in-depth description of the internalstructure and the devices used. Finally, some actual receiver system implementations and available

off-the-shelf board level digital receiver products for embedded systems will be described.

33333



RFAMP

LOCALOSCILLATOR

DEMODULATION(Detector)

AUDIOAMPLIFIER

IF AMPLIFIER(Narrowband Filter)

ANTENNA

SPEAKERMIXER

Figure 1

The conventional heterodyne radio receiver as seenin Figure 1 has been in use for nearly a century. Let’sreview the structure of the analog receiver so comparisonto the digital receiver becomes apparent.

First the RF signal from the antenna is amplified,typically with a tuned RF stage which amplifies a regionof the frequency band of interest.

This amplified RF signal is then fed into a mixerstage. The other input to the mixer comes from the localoscillator whose frequency is controlled by the tuningknob on the radio.

The mixer translates the desired input signal to theIF (intermediate frequency). See Figure 2.

The IF stage is a bandpass amplifier which only letsone signal or radio station through. Common centerfrequencies for IF stages are 455 kHz and 10.7 MHzfor commercial AM and FM broadcasts.

The demodulator recovers the original modulatingsignal from the IF output using one of several differentschemes.

For example, AM uses an envelope detector and FMuses a frequency discriminator. In a typical home radio,the demodulated output is fed to an audio amplifier andthen to a speaker.

0 Fif Fsig

MIXER TRANSLATESINPUT SIGNAL BAND

to IF FREQUENCY

LOCALOSCILLATORFlo = Fsig - Fif

IF BW

Figure 2

Analog RAnalog RAnalog RAnalog RAnalog Receiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagram Analog RAnalog RAnalog RAnalog RAnalog Receiver Mixingeceiver Mixingeceiver Mixingeceiver Mixingeceiver Mixing

The mixer performs an analog multiplication of thetwo inputs and generates a difference frequency signal.

The frequency of the local oscillator is set so that thedifference between the local oscillator frequency anddesired input signal (the radio station you want toreceive) equals the IF (intermediate frequency).

For example, if you wanted to receive an FMstation at 100.7 MHz and the IF frequency is 10.7 MHz,you would tune the local oscillator to:

100.7 - 10.7 = 90 MHz

This is called “down conversion” or “translating”since a signal at a high frequency is shifted down to alower frequency by the mixer.

The IF stage acts as a narrowband filter which onlypasses a “slice” of the translated RF input. The band-width of the IF stage is equal to the bandwidth of thesignal (or “station”) that you are trying to receive.

For commercial FM, the bandwidth is about 100kHz and for AM it is about 5 kHz. This is consistentwith channel spacing of 200 kHz and 10 kHz, respectively.

TheorTheorTheorTheorTheory of Operationy of Operationy of Operationy of Operationy of Operation

44444



DIGITALLOCAL

OSCILLATOR

DIGITALLOWPASS

FILTER

AUDIOAMP

SPEAKER

RFAMP

ANTENNA

A/DCONV DSP

(DEMODU-LATION)

D/ACONV

MIXERRF

TRANS-LATOR

Figure 3

0 fo fs/2 fa fs

Aliased image at fs - fa

Figure 4

TheorTheorTheorTheorTheory of Operationy of Operationy of Operationy of Operationy of Operation (continued)(continued)(continued)(continued)(continued)

Digital RDigital RDigital RDigital RDigital Receiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagram

Take a look at the digital receiver block diagramshown in Figure 3. Note the strong similarity to theanalog receiver diagram—all of the basic principles ofanalog receivers still apply.

Right after the RF amplifier and an optional RFtranslator stage, we use an A/D (analog-to-digital)converter to digitize the RF input into digital samplesand all of the subsequent mixing, filtering and demodu-lation are performed using digital signal processingelements.

Before we continue, lets first review a theoremfundamental to sampled data which lays the foundationfor the A/D converter requirements.

Nyquist’s Theorem:

“Any signal can be represented by discrete samples ifthe sampling rate is at least twice the bandwidth ofthe signal.”

For example, if we use an A/D converter sampling at70 MHz, then the bandwidth of the analog input mustbe less than 35 MHz.

Now let’s see what happens if we ignore Nyquist’scriterion.

AliasingAliasingAliasingAliasingAliasing

Figure 4 shows a frequency display of a system beingsampled at frequency fs. For all input signals below fs/2,such as the one at fo, we fully meet the Nyquist crite-rion. In fact, any number of signals can be present in theshaded region and all will be correctly represented in thesampled data.

But if we have a signal present at say, fa, which isabove fs/2, the sampling process will generate an aliasedimage which will appear in the sampled data at fs - fa.This image cannot be distinguished from a true signalwhich might have been present at that same frequency.

The point is, that once an aliased image is created inthe sampling process, no amount of further processingcan distinguish between a true signal and an aliasedsignal.

Therefore, it is imperative to prevent aliasing beforeit occurs.

55555



0 fo fs/2 fa fs

Low Pass Filter Response

Figure 5 DIGITALLOCAL

OSCILLATOR

DIGITALLOWPASS

FILTER

AUDIOAMP

SPEAKER

RFAMP

ANTENNA

A/DCONV DSP

(DEMODU-LATION)

D/ACONV

MIXER

DIGITAL RECEIVER CHIP

RFTRANS-LATOR

CLOCK

Figure 6


Anti-Anti-Anti-Anti-Anti-Aliasing FAliasing FAliasing FAliasing FAliasing Filterilterilterilterilter

The most straightforward way to prevent aliasing isto use a low pass filter before the A/D converter whichremoves all signals above fs/2.

This filter is called an anti-aliasing filter seen inFigure 5. Now the signal at fa is blocked so the A/Dconverter never sees it.

Anti-aliasing filters are often included on the sameboard as the A/D converter as a convenience for the user.

As a side note, Nyquist’s criterion can also be met bylimiting the bandwidth of the sampled signal using othertypes of filters.

For example, suppose we really wanted to receivesignals between fs/2 and fs in the above diagram. If weused a bandpass filter with a passband from fs/2 to fs, wewould fully meet the Nyquist criterion because thebandwidth is equal to one half the sampling rate.

Once the sampling is done, the band of signals fromfs/2 to fs is “folded” into the frequency band from DC tofs/2. The half-sampling frequency is often called the“folding frequency.”

This technique is sometimes called “under-sam-pling” and while this works well in theory, care must betaken in actual practice to ensure that the A/Dconverter supports the higher input frequencies it musthandle.


Looking again at the overall block diagram, thedigital A/D samples coming out of the A/D converterare being fed to the next stage which is the digitalreceiver chip (in the dotted line as shown in Figure 6).

The digital receiver chip is typically contained on asingle monolithic chip which forms the heart of thedigital receiver system. It is also sometimes referred to asa digital down converter (DDC) or a digital dropreceiver (DDR).

Inside the digital receiver chip there are three majorsections:

• Local Oscillator

• Mixer

• Decimating Low Pass Filter

Note that the inputs to the digital chip are thedigital samples from the A/D and the A/D sample clock.With a 70 MHz A/D, samples are fed into this chip andprocessed in real time at rates up to 70 MHz!

We will now explore each section of the digitalreceiver system shown in Figure 6, starting with thedigital local oscillator.

66666



Figure 7

PARALLELDIGITALINPUTFROM

A/D

DECIMATINGLOW PASSFIR FILTER

BANDWIDTHDECIMATIONFACTOR = NLOCAL OSCILLATOR

(DIRECT DIGITALSYNTHESIZER)

fs/Nfs fs

Real

IQ

COMPLEXMIXER

CENTER FREQUENCYDC to fs/2

SIN COS

CLOCKFROM

A/D

SIN

COS

F1 F2

Figure 8


The Local Oscillator has very impressive frequencyswitching characteristics as shown in Figure 8.

When switching between two frequencies, thedigital accumulator precisely maintains the phase of thesine and cosine outputs for phase continuous switching.When the frequency is changed, what actually changes isthe amount of phase advance per sample.

This allows the local oscillator to perform FSK(frequency shift keying) and very finely resolved sweeps.Transients and settling normally associated with othertypes of local oscillators, such as phase-locked loopsynthesizers, are eliminated.

The time it takes to retune the local oscillator issimply the time it takes to load a new digital frequencyword (32-bit binary number) into a register, usually wellbelow one microsecond.

Some digital receiver chips employ a local oscillatorwith a built-in “chirp” function. This is a fast, program-mable and precise frequency sweep which is very usefulin radar systems.

First, let’s explore the Local Oscillator highlighted inFigure 7. It’s a direct digital frequency synthesizer (DDS)sometimes called a numerically controlled oscillator(NCO). This device is implemented entirely with digitalcircuitry.

The oscillator generates digital samples of two sinewaves precisely offset by 90 degrees in phase, creatingsine and cosine signals. It uses a digital phase accumula-tor and sine/cosine lookup tables.

Note that the A/D clock is fed into the local oscilla-tor. The digital samples out of the local oscillator aregenerated at a sampling rate exactly equal to the A/Dsample clock frequency, fs.

It is important to understand that the output samplingrate is always fixed at fs, regardless of the frequency setting.The sine/cosine output frequency is changed by program-ming the amount of phase advance per sample.

A small phase advance per sample corresponds to alow frequency and a large advance to a high frequency. Thephase advance per sample is directly proportional to theoutput frequency and is programmable from DC to fs/2with up to 32-bit of resolution.

Using a 70 MHz sampling clock, the frequencyrange is from DC to 35 MHz and the resolution is wellbelow 1Hz.

LLLLLocal Oscillatorocal Oscillatorocal Oscillatorocal Oscillatorocal Oscillator Phase Continuous SwitchingPhase Continuous SwitchingPhase Continuous SwitchingPhase Continuous SwitchingPhase Continuous Switching

77777




A/D




fs/Nfs fs

Real

IQ

COMPLEXMIXER


SIN COS

CLOCKFROM

A/D

Figure 9

0 Fsig

MIXER TRANSLATESINPUT SIGNAL

BAND to DC

LOCALOSCILLATOR

TUNING

Figure 10


Let’s look at the “difference” mixer product in thefrequency domain as shown in Figure 10. At the outputof the mixer, the high frequency wideband signals in theA/D input have been translated down to DC with a shiftor offset equal to the local oscillator frequency.

This is similar to the analog receiver mixer exceptthat the analog receiver mixes the RF input down to anIF (intermediate frequency).

In the digital receiver, the precision afforded by thedigital signal processing allows us to mix right down tobaseband (or 0 Hz). Overlapping mixer images, difficultto reduce with analog mixers, are strongly rejected by theaccuracy of the sine and cosine local oscillator samplesand the mathematical precision of the multipliers in thedigital mixer.

By tuning the local oscillator over its frequencyrange, any portion of the RF input signal can be trans-lated down to DC. In effect, the wideband RF signalspectrum can be shifted around 0 Hz, left and right,simply by changing the local oscillator frequency.

The objective is to tune the local oscillator to centerthe signal of interest around 0 Hz so that the followinglow pass filter can pass only the signal of interest.

The next major component of the digital receiverchip is the Mixer as seen in Figure 9. The Mixer actuallyconsists of two digital multipliers. Digital input samplesfrom the A/D are mathematically multiplied by thedigital sine and cosine samples from the local oscillator.

Note that the input A/D data samples and the sineand cosine samples from the local oscillator are beinggenerated at the same rate, namely, once every A/Dsample clock. Since the data rates into both inputs of themixers are the A/D sampling rate, fs, the multipliers alsooperate at that same rate and produce multiplied outputproduct samples at fs.

The sine and cosine inputs from the local oscillatorcreate I and Q (in-phase and quadrature) outputs thatare important for maintaining phase informationcontained in the input signal. From a signal standpoint,the mixing produces a single-sideband complex transla-tion of the real input.

Unlike analog mixers which also generate manyunwanted mixer products, the digital mixer is nearly idealand produces only two outputs: the sum and differencefrequency signals.

Digital MixerDigital MixerDigital MixerDigital MixerDigital Mixer Digital RDigital RDigital RDigital RDigital Receiver Mixer Teceiver Mixer Teceiver Mixer Teceiver Mixer Teceiver Mixer Translationranslationranslationranslationranslation

88888




A/D




fs/Nfs fs

Real

IQ

COMPLEXMIXER


SIN COS

CLOCKFROM

A/D

Figure 11

0 Fsig

MIXER TRANSLATESINPUT SIGNAL

BAND to DC

LOCALOSCILLATOR

FILTERBANDLIMITS

TRANSLATEDSIGNAL

Figure 12


Once the RF signal has been translated, it is nowready for filtering.

The decimating low pass filter accepts input samplesfrom the mixer output at the full A/D sampling fre-quency, fs. It utilizes digital signal processing to imple-ment a FIR (finite impulse response) filter transferfunction.

The filter passes all signals from 0 Hz up to aprogrammable cutoff frequency or bandwidth, andrejects all signals above that cutoff frequency.

This digital filter is a complex filter which processesboth I and Q signals from the mixer. At the output youcan select either I and Q (complex) values or just realvalues, depending on your system requirements.

Figure 12 shows a representation of the action of thefilter in the frequency domain. The filter passes onlysignals from 0 Hz up to the filter bandwidth. All higherfrequencies have been removed.

Remember, the wideband input signal was translateddown to DC by the mixer and positioned around 0 Hzby the tuning frequency of the local oscillator.

Now at the filter output, we have effectively selecteda narrow slice of the RF input signal and translated it toDC. Note that we have blocked all other signals aboveand below the band of interest.

The bandlimiting action of the filter is analogous tothe action of the IF stage in the analog receiver exceptthat the decimating low pass filter operates around DCinstead of being centered at an IF frequency.

Decimating LDecimating LDecimating LDecimating LDecimating Low Pow Pow Pow Pow Pass Fass Fass Fass Fass Filterilterilterilterilter Decimating FDecimating FDecimating FDecimating FDecimating Filter Bandlimitingilter Bandlimitingilter Bandlimitingilter Bandlimitingilter Bandlimiting

99999



Figure 13

0 5 10 15 20 25 30 MHz

-3 -2 -1 0 1 2 3 kHz

OUTPUT

INPUT

6 kHz Input Sample Rate Output Bandwidth = --------------------------

N

Input Sample RateComplex Output Samp. Rate = ---------------------------

N

2 * Input Sample Rate Real Output Sample Rate = --------------------------------

N


FFFFFrequency Zoomrequency Zoomrequency Zoomrequency Zoomrequency Zoom Decimation FDecimation FDecimation FDecimation FDecimation Factor = Nactor = Nactor = Nactor = Nactor = N

In order to set the bandwidth of the filter, you needto program a parameter called the decimation factor asseen in Figure 14. Since the output bandwidth and theoutput sampling rate are directly related in the DDR,the decimation factor also sets the output sampling rate.

The decimation factor, N, determines the ratiobetween input and output sampling rates and also theratio between input and output bandwidths. Note thatthe output sampling rate for real outputs is twice that forcomplex outputs.

For example, if you have an input sampling rate of70 MHz and a desired nominal output bandwidth of 7kHz, the decimation should be set for 10,000. Theoutput sampling rate would be 7 kHz for complexoutputs and 14 kHz for real outputs.

Note that the usable bandwidth is always less than theNyquist bandwidth, hence in the previous example we see areal input bandwidth of about 30 MHz (with a 70 MHzsampling rate) and an output bandwidth of about 6 kHz(with a complex output sampling rate of 7 kHz or a 14kHz output for real).

Digital receivers can be divided into two classes,narrowband and wideband, distinguished by theprogrammable range of decimation factors.

Narrowband receivers typically have a range ofdecimation factors from 32 or 64 to 65,536 or 131,072,depending on the chip manufacturer.

Wideband receivers typically have a range of deci-mation factors from 2 to 64.

As an example, take a look at an actual frequencydisplay shown in Figure 13. The top figure shows a 30MHz wideband RF input which was sampled by the A/D converter at 70 MHz.

Suppose we have a signal of interest at 20 MHz andwe know that the bandwidth of the signal is 6 kHz.

By setting the local oscillator to 20 MHz and thebandwidth of the filter to 6 kHz we can translate thesignal and extract only a 6 kHz band as shown in thebottom figure.

Note that the input band around 20 MHz has beentranslated down to DC and the complex output allowsus to compute a complex FFT power spectrum centeredat 0 Hz. Frequency components which were previouslyabove 20 MHz are now to the right of 0 Hz and thosebelow 20 MHz are to the left of 0 Hz. The 20 MHzcarrier is now at 0 Hz exactly.

In this case, we have used the decimating low passfilter to perform a dramatic reduction in the signalbandwidth from 30 MHz down to 6 kHz. The sam-pling rate has also been reduced from 70 MHz to 7 kHz,a factor of 10,000!

Now let’s see exactly how to control the decimationof the FIR filter.

Figure 14

1010101010



Figure 15


FPGA Implementations ofFPGA Implementations ofFPGA Implementations ofFPGA Implementations ofFPGA Implementations ofDigital RDigital RDigital RDigital RDigital Receiverseceiverseceiverseceiverseceivers

FPGAs (Field Programmable Gate Arrays) havebecome more appropriate for implementing digitalreceiver functions because of new built-in hardwaremultipliers and generous RAM. Remember that thedigital mixer section is nothing more than a hardwaremultiplier. The FIR filter also uses one multiplier foreach filter tap plus RAM for delay memory.

Pentek’s GateFlow IP Core Library for softwareradio includes fast FFT engines, radar pulse compres-sors, and digital receivers. These cores allow FPGAdesigners to readily incorporate these highly optimizedfunctions in FPGA-based products.

Most of Pentek’s recent software radio productsinclude user-configurable FPGAs in the signal path tosupport IP cores and custom DSP algorithms. Pentekalso offers factory installation of IP cores in several ofthese products, eliminating the FPGA design effort andallowing customers to easily take advantage of thisexciting new technology.

Figure 15 above shows a dual channel A/Dconverter VIM-2 module with the Pentek GateFlowWideband Receiver Core 421 installed. This corereplaces the GC1012B and offers higher dynamic rangeand user-programmable FIR coefficients. It accepts 16-bit inputs instead of the 12-bit inputs on the GC1012to take full advantage of the 14-bit A/D converters. Forthe latest FPGA offerings visit the online FPGA Re-source at www.pentek.com/gateflow.

FPGAs TFPGAs TFPGAs TFPGAs TFPGAs Tackle DSP Fackle DSP Fackle DSP Fackle DSP Fackle DSP Functionsunctionsunctionsunctionsunctions

FPGAs not only offer significant advantages asspecialized replacements for standard ASIC digitalreceivers, they also provide extremely high performancesignal processing capabilities to off-load these tasks fromDSP and RISC processors.

An example is the Pentek GateFlow IP Core 404 4kPoint Complex FFT. Although all GateFlow IP Coresare designed for use on any Virtex-II, Virtex-II Pro orSpartan 3 product, the Core 404 is available as a factoryinstalled option on the Model 6236 Dual ChannelReceiver VIM-2 module shown in Figure 16.

In this case, real data from the A/D converter orcomplex I and Q samples from the wideband digitalreceiver can be directed into the FFT engine. The firststage performs an optional Hanning (or other)windowing function as a pre-processing step before thecomplex 4k point FFT.

The output of the FFT can be optionally convertedto power by summing I2 and Q2. Finally, consecutiveoutputs can be optionally averaged to reduce widebandnoise.

Because of the highly-parallel architecture of this IPCore, it can sustain real time input sampling rates of upto 160 MHz. It would take approximately 16 G4PowerPCs running at 500 MHz to equal the processingpower of this impressive engine!

EXTCLK

CLOCK & SYNC

105 MHz14-BitA/D

Xilinx Virtex-II FPGA (XC2V3000)With GateFlow Factory Installed DDR Core 421

RFIN

VIMI/F

FIR Lowpass

Filter

Local Osc

Decimatorand

Formatter

IQ

IQ

Pentek 6236

105 MHz14-BitA/D

RFIN

VIMI/F

FIR Lowpass

Filter

Local Osc

Decimatorand

Formatter

IQ

IQ

CLOCK & SYNC

Xilinx Virtex-II FPGA (XC2V3000)With GateFlow Factory Installed

IPC Core 404 FFT

POWERCALC AVERAGER

105 MHz14-Bit A/DAD6645

RFIN

WidebandRecei verGC1012B

HANNINGWINDOW

4k POINTCOMPLE X

FFT

EXTCLK

105 MHz14-Bit A/DAD6645

RFIN

WidebandRecei verGC1012B

Pentek 6236

VIMI/Fsame as above

VIMI/F

Figure 16

1111111111



DIGITALLOCAL

OSCILLATOR

DIGITALLOWPASS

FILTER

AUDIOAMP

SPEAKER

RFAMP

ANTENNA

A/DCONV DSP

(DEMODU-LATION)

D/ACONV

MIXERRF

TRANS-LATOR

CLOCK

Figure 18

Returning to our overall digital receiver blockdiagram shown in Figure 18, our output signal is nowtranslated, filtered and bandlimited and is ready forfurther processing.

Note that the output signal from the decimating lowpass filter is still a sampled time signal which couldrepresent any kind of modulated or unmodulated signal.We could send this signal directly to a D/A converter,producing an analog waveform.

For straight single-sideband frequency divisionmultiplexed speech, for example, we could now connectthe D/A output to a speaker and listen to the selectedvoice channel directly.

In many systems, further processing is required, aswith modem demodulation for example. Since theoutput of the digital receiver is now at a much lowersampling rate than the original wideband input signal,this additional modem processing can now be readilyhandled by a DSP or an FPGA.


DIGITAL LOCALOSCILLATOR

DIGITALLOWPASS

FILTER

MIXER

Translation FilteringTranslation Filtering

TUNINGFREQUENCY

DECIMATIONFACTOR

To review, the digital receiver chip performs twomajor signal processing operations controlled by twoprogrammable parameters (Figure 17):

1) Translation of the input signal down to DC iscontrolled by setting the tuning frequency of thelocal oscillator.

2) Low pass filtering bandwidth and outputsampling rate are both controlled by setting thedecimation factor.

Because everything inside the decimating low passfilter is performed with digital circuitry and DSPtechniques, there are no undesirable effects normallyassociated with conventional analog filters.

There are no initial component tolerance or tem-perature variations or aging characteristics. No calibra-tion or preventive maintenance is required. Thisprovides excellent channel-to-channel matching forapplications where phase shift variation between chan-nels is important, such as direction finding.

The FIR digital filters used are linear phase for well-behaved transient response. The filter bandwidth isprogrammable over a wide range (1000 to 1), with abso-lutely predictable and uniform response throughout.

Lastly, the signal is tailored precisely for DSPprocessing by pre-selecting only the signal of interestthrough bandlimiting and providing it to the DSP at theoptimum sampling rate.

TTTTTwowowowowo-Step Signal P-Step Signal P-Step Signal P-Step Signal P-Step Signal Processingrocessingrocessingrocessingrocessing

Figure 17


1212121212



• Dedicated digital receiver hardware pre-selects only signals of interest

• Saves significant DSP horsepower sinceDSP requirements are directly proportionalto sampling rate

Figure 20

! Frequency and Phase Shift Keying (FSK, PSK)! AM, FM, and PM! Spread Spectrum! Custom Frequency Agile Schemes! Signal Analysis (FFT’s), Signal Identification! Signal Recording and Tracking

Figure 19

Virtually any form of demodulation can beimplemented just by loading the DSP or FPGA with theappropriate algorithm (Figure 19). AM can bedemodulated with an envelope detector, FM & PM canbe demodulated using a phase or frequencydiscriminator algorithm.

The ability to quickly change the local oscillatorallows frequency agile modulation schemes to beaccommodated as well.

Analysis functions include energy detection such asrequired by scanning receivers which may beimplemented with an FFT, for example.

Other analysis functions include cryptography,identification of transmitters based on transmissionfrequency, modulation schemes, and other signalcharacteristics.

Once the signal is successfully brought into the DSParena, automated functions such as center frequency andbandwidth tuning can be implemented to track acomplex signal which may be moving or hopping.

Interesting signals can be stored on hard disk, tapeor other media and the time of the signal event can belogged as well.

With this arrangement, when new or proprietarydemodulation, processing or analysis schemes are required,no new hardware is necessary. Instead, a new DSP softwarealgorithm is loaded.

Think of the digital receiver as a hardware pre-processor for DSP. It pre-selects only the signals you areinterested in and removes all others. This provides anoptimum bandwidth and minimum sampling rate intothe DSP.

Since the number of DSP’s required in a system isdirectly proportional to the sampling rate of input data,by reducing the sampling rate you can dramaticallyreduce the cost and complexity of the DSP system whichfollows.

Even if the digital receiver outputs do not require agreat deal of signal processing, reduction of bandwidthand sampling rate helps save time in data transfers toanother sub-system, helps minimize recording time andtape or disk space, and speeds up communicationchannels.

KKKKKey Benefits of Digital Rey Benefits of Digital Rey Benefits of Digital Rey Benefits of Digital Rey Benefits of Digital ReceiverseceiverseceiverseceiverseceiversDSP Demodulation FDSP Demodulation FDSP Demodulation FDSP Demodulation FDSP Demodulation Functionsunctionsunctionsunctionsunctions


1313131313



RRRRReceiver Chip Peceiver Chip Peceiver Chip Peceiver Chip Peceiver Chip Perererererformanceformanceformanceformanceformance

The above chart shows the salient characteristics forseven popular digital receiver chips and two FPGA IPcores. Note that the range of decimation settings for thenarrowband chips on the left are much higher than forthe wideband receivers on the right. The output sam-pling rates for real and complex outputs are shown as afunction of the decimation factor, N.

Notice also that the 3 dB output bandwidth of theFIR filter is expressed as a percentage of the input sam-pling rate divided by N. This percentage reflects thefrequency characteristics of the specific FIR filter functionimplemented inside the digital receiver chip. Each filtercharacteristic has its own passband flatness, rolloff rate,and stop band attenuation characteristics suitable fordifferent applications.

As an example, if we were using the GC1011A witha 64 MHz A/D converter and needed a usable outputbandwidth of 10 kHz, we could solve for the appropri-ate decimation factor setting as follows:

10 kHz = 0.80 • Fs / N orN = 0.80 • 64 MHz / 10 kHz = 5120

Note that the decimation factors of narrowbandreceivers are programmable in steps of 1 or 4 and thewideband receivers are programmable in binary steps asshown. Some receivers allow entry of custom FIR filtercoefficients and others have output resampling stages tosupport custom filter characteristics and output sam-pling rates.

Model numbers of Pentek products using each typeof digital receiver are shown at the bottom.


TI / GC Intersil TI / GC Intersil TI / GC TI / GC TI / GC Pentek Pentek4014 50214B 1011A 50016 4016 1012A 1012B IPC 421 IPC 422

No of Channels 4 1 1 1 4 1 1 1 1

Samp Rate (Fs) 62.5 MHz 65 MHz 70 MHz 75 MHz 100 MHz 80 MHz 100 MHz 140 MHz 280 MHz

Input Bits 14 or 16 16 12 16 14 or 16 12 12 16 16

Min Dec (N) 32 2 64 64 32 2, 4, 8 2, 4, 8 2, 4, 8 2, 4, 8

Max Dec (N) 65k 65k 65k 131k 16k 16,32,64 16,32,64 16,32,64 16,32,64

Resampler No Yes No No Yes No No No No

Custom FIR Yes Yes No No Yes No No Yes Yes

Mag & Phase No Yes No No No No No No No

3 dB Out BW prog prog 0.8Fs/N 0.56Fs/N prog 0.8Fs/N 0.8Fs/N prog prog0.9Fs/N 0.9Fs/N 0.9Fs/N

VME 6532 6509 6508/10 6821Boards 6514/16

PCI Boards 7631Compact PCI 7231

VIM 6210 6230 6216 6235 6235 6250Modules 6231 6236 6236 6251

6232 62506251

PMC Modules 7131

Narrowband Wideband

1414141414



Applications

Applications for Digital RApplications for Digital RApplications for Digital RApplications for Digital RApplications for Digital Receiverseceiverseceiverseceiverseceivers

Digital receivers can be used in many differentsystems:

Tracking receivers and signal intelligence receiverscan be highly automated because digital receivers allowDSP’s to perform the signal identification and analysisfunctions as well as the adaptable tuning functions.

Direction finding is an ideal application for digitalreceivers because of their excellent channel-to-channelphase matching and consistency delay characteristics.

Radar applications benefit from the tight couplingof the A/D, digital receiver and DSP functions toprocess wideband signals. FPGAs are especially wellsuited to handle FFT and pulse compression tasksnormally required in the signal processing sections.

Some of the digital receivers chips employ specialfeatures like a “chirp” sweep generator function in the

local oscillator, ideal for high-performance radar applica-tions.

Cellular phone applications are one of the strongesthigh-volume applications because of the high density oftightly-packed frequency division multiplexed voicechannels.

As a general capability, any system requiring atunable bandpass filter should be considered a candidatefor using digital receivers. Take a look at the followingexample applications to give you some more details.

Product overviews of all models described in theapplications section are included in the last section ofthe handbook.

• Tracking Receiver System• Signal Intelligence Receiver • Direction Finding System• Radar Signal Processor• Radar Recording System• Cellular Phone Base Station

1515151515



ApplicationsApplicationsApplicationsApplicationsApplications (continued)(continued)(continued)(continued)(continued)

32 Channel T32 Channel T32 Channel T32 Channel T32 Channel Tracking Rracking Rracking Rracking Rracking Receiver Systemeceiver Systemeceiver Systemeceiver Systemeceiver System

In the tracking receiver system in Figure 21 wedigitize two IF signals at a 40 MHz sampling rate with aModel 6441 Dual Channel A/D converter.

Using an FPDP (front panel data port) interface,both 12-bit A/D channels are packed across the 32-bitFPDP data field and delivered to one of the FPDPinputs of the Model 6232 32 Channel NarrowbandVIM-4 Receiver. This mezzanine nests in the same slotas the Model 4294 Quad G4 PowerPC processor board.

The A/D is also connected to the input of the Model6099A 512 MB Digital Delay Memory buffer. Thedelayed output is then connected over FPDP to thesecond input of the 6232, which now receives both thedelayed and undelayed A/D output signals.

Using the bypass path of the 6232, the undelayedwideband A/D data is routed around the narrowbandreceivers, through the FPGA and into the top PowerPC.Here, an FFT is performed to locate energy. Thenarrowband receivers are then tuned to the appropriatefrequencies so that when the delayed signals arrive at thereceiver chips, they are pre-tuned to receive the signals atthe new frequency. The other three DSPs process thenarrowband signals for decoding, demodulation andanalysis.

The delay provides the necessary “look ahead”capability to handle even the most difficult “de-hopping”tasks for up to 32 channels. The FPGA is also availablefor off-loading processing tasks from the DSP processors.

Figure 21

PENTEK 6099A512 MB Delay

Memory

256 MBBUFFER256 MB

BUFFER

256 MBBUFFER256 MB

BUFFER

PENTEK 6099A512 MB Delay

Memory

256 MBBUFFER256 MB

BUFFER

256 MBBUFFER256 MB

BUFFER

CH 2 IN

EXT ERNALCLOCK IN

CH 1 IN

CLOCK GENERATOR

41 MHz12-bit A/D

LOW PASSFILTER

LOW PASSFILTER

LOW PASSFILTER

LOW PASSFILTER

41 MHz12-bit A/D

PENTEK 644112-bit 41 MHz

2 Chan A/D

VMEbus

PENTEK 6232 VIM32 Chan Receiver

Xilin

x V

irtex

-E F

PGA

Xilin

x V

irtex

-E F

PGA

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

FPDP

FPDP

FPDP


Xilin

x V

irtex

-E F

PGA

Xilin

x V

irtex

-E F

PGA

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

FPDP

FPDP

FPDP


Xilin

x V

irtex

-E F

PGA

Xilin

x V

irtex

-E F

PGA

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

QuadDDR

FPDP

FPDP

FPDPFPDP

FPDP

PENTEK 4294Quad G4 PowerPC

Altivec G4PowerPC

VIM

VIM

VIM

VIM

RACE++Interface

RACE++

Altivec G4PowerPC

Altivec G4PowerPC

Altivec G4PowerPC

1616161616



Figure 22

32 Channel Signal Intelligence R32 Channel Signal Intelligence R32 Channel Signal Intelligence R32 Channel Signal Intelligence R32 Channel Signal Intelligence Receiver with G4 Peceiver with G4 Peceiver with G4 Peceiver with G4 Peceiver with G4 PowerPC PowerPC PowerPC PowerPC PowerPC Processorrocessorrocessorrocessorrocessor

Taking advantage of the fully “channelized” VIM-compatible products, this compact receiver systemincorporates the entire signal processing signal chainfrom the A/D digitizers, through digital down conver-sion and filtering, to decoding, demodulation andanalysis performed by FPGA and PowerPC’s. And it allfits in just a single VMEbus slot!

The Model 6230 32-Channel Narrowband Receiveris a VIM-4 mezzanine module that includes four 14-bitA/D converters operating a sampling rates up to 80MHz. All four A/D outputs are delivered to eight 4-channel receiver chips so that each of the 32 narrowbandchannels can independently select any one of the four A/D converter as the input source.

The 32 narrowband receiver outputs are sent intotwo FPGAs where channel selection and data formattingtake place prior to sending the data across the VIMinterface to the PowerPC board. Note that the widebandA/D outputs are also delivered directly to the FPGA sothey are also available for transfer to the PowerPC.

Custom algorithms may be incorporated in theFPGA to support decoding, demodulation and othersignal processing tasks, thus off-loading the processor.

Because of its modular, single-board design, thissystem is highly scalable to support low-cost, high-density systems with hundreds of channels in a relativelysmall space.

VIM

VIM

VIM

VIM

RACE++

Pentek 4294 Quad PowerPC MPC7410 Processor

GlobalSDRAM

GlobalPCIBus

64 bits66 MHz

I/OPCIBus

64 bits33 MHz

100-TE-Net

IP PCI Bus64 bits

66 MHz

GlobalFLASH

FIFOPCI Master

PCI toPCI

Bridge

PCI Master

VMEbus

CONTROL

CONTROL

CONTROL

CONTROL

DATA

DATA

DATA

DATA

FIFO

FIFO

FIFO

PowerPCNode

PowerPCNode

PowerPCNode

PowerPCNode

PCI-RACE++Bridge

PCI to VMEBridge

FrontPanel

Pentek 6230 VIM-432 Chan Receiver

AnalogHF or IF Inputs

Xilin

x Vi

rtex

-E F

PGA

80 MHz14-bit A/D

80 MHz14-bit A/D

80 MHz14-bit A/D

80 MHz14-bit A/D

Xilin

x Vi

rtex-

E FP

GA

QuadRecvr

QuadRecvrQuadRecvr

QuadRecvr

QuadRecvr

QuadRecvr

QuadRecvr

QuadRecvr

QuadRecvr





1717171717




Direction FDirection FDirection FDirection FDirection Finding Systeminding Systeminding Systeminding Systeminding System

In this direction finding application, we need toroute digitized signals from eight antennas into a DSPwhich compares the arrival time and phase of each signal.This allows the DSP to compute the location, speed anddirection of travel of a mobile radio source.

Four of the 32-Channel Narrowband Receiversubsystems shown on the previous page (Figure 22) aredriven by eight antennas. Two of the 32 channels ineach subsystem are tuned to the frequency of a sourcetransmitter. In this way, eight difference versions of thesame transmitted signal are acquired, one from eachantenna. The data samples are time stamped, organizedin packets and then sent out over RACEway, a high-performance, industry standard backplane fabric.RACEway allows simultaneous high-speed data transfersbetween pairs of boards. Even though data is sent in

packets, the output samples are fully buffered so no datais lost.

Each RACEway packet contains a header whichincludes channel identification, signal arrival time, androuting instructions to a destination DSP address. Eachof the eight packets for a single source are directed to oneof the DSPs, where phase and arrival time beamformingcalculations are performed. This highly scalable systemsupports continuous, simultaneous tracking of up tosixteen targets.

By simply changing the RACEway packet routingaddresses through software, you can completelyreconfigure your system, and assign any number ofchannels to any number of DSPs. Routing informationcan be allocated dynamically during runtime to accom-modate changing conditions.

Figure 23

DSP

DSP

DSP

DSP

DSP

DSP

DSP

DSP

Model 4292Quad ‘C6203DSP Boards

RACEway ILKCrosspointBackplane

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr RAC

E++

I/F

DSP

DSP

DSP

DSP

Modular ReceiverSub-Systems

RF Tuner

RF Tuner

RF TunerRF Tuner

RF TunerRF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

DSP

DSP

DSP

DSP

RF TunerRF Tuner

RF TunerRF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr RAC

E++

I/F

DSP

DSP

DSP

DSP

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr RAC

E++

I/F

DSP

DSP

DSP

DSP

DSP

DSP

DSP

DSP

RF TunerRF Tuner

RF TunerRF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

RF Tuner

RF Tuner

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

FPGAA/D Recvr

A/D Recvr

FPGAA/D Recvr

A/D Recvr

RAC

E++

I/F

DSP

DSP

DSP

DSP

DSP

DSP

DSP

DSP

RF TunerRF Tuner

RF TunerRF Tuner

Scalability for Receiver Channels Scalability for DSP

RACE++Interface

RACE++Interface

1818181818



Figure 24

Radar is well served by high-speed A/D convertersand wideband digital receivers. The channelized systemshown in Figure 24 takes advantage of two Model 6236Wideband Receiver VIM-2 mezzanine modules mountedon the Model 4292 Quad C6203 DSP processor.

Operating at a sampling rate of up to 100 MHz, theA/D converters can digitize baseband signals withbandwidths up to 45 MHz. After frequency translationand filtering, the receivers deliver complex (I&Q) datainto the Virtex-II FPGAs where data may be processed bycustom, used defined algorithms before it is sent acrossthe VIM interface to the DSPs.

Note that the wideband A/D outputs are alsoconnected directly to the FPGAs, either for delivery tothe DSPs or for internal processing tasks.

The optional GateFlow FPGA Design Kit supports

custom signal processing algorithms including Pentek’sGateFlow IP Core Library offerings. Factory installed IPcores available for the Model 6236 include Core 421Wideband Receiver, Cores 40x FFT’s, and Core 440Pulse Compressor. Gating and triggering signals areaccepted on front panel connectors of the 6236 tocapture transient signals.

Supporting peak data transfer rates up to 100 MHzto each of the four processing nodes, the VIM interfaceeliminates the bottlenecks normally associated withtraditional system interconnect schemes.

An optional RACE++ (enhanced RACEway)interface is available for delivering output data from allfour processing nodes to downstream memory, storage orarray processors at transfer rates up to 267 MB/sec.

RRRRRadar Signal Padar Signal Padar Signal Padar Signal Padar Signal Processing Systemrocessing Systemrocessing Systemrocessing Systemrocessing System


EXTCLOCK CLOCK &

SYNCGENERATOR

XTALOSC

105 MHz14-bit A/D

DIGITALRECEIVER

105 MHz14-bit A/D

DIGITALRECEIVER

BYPASS

BYPASS

LVDS CLOCK& SYNC

Clock

ClockVI

RTE

X-II

3M G

ATE

FP

GA

CH AIN

CH BIN

Model 6236 2 Ch A/D and Receiver

EXTCLOCKLVDS

CLOCK& SYNC

CLOCK &SYNC

GENERATOR

XTALOSC

105 MHz14-bit A/D

DIGITALRECEIVER

105 MHz14-bit A/D

DIGITALRECEIVER

BYPASS

BYPASS

Clock

Clock

VIR

TEX-

II3M

GA

TE F

PG

A

CH CIN

CH DIN


VIM

VIM

RACE++

Model 4292 Quad C6203DSP Processor

GlobalSDRAM

GlobalPCIBus

64 bits33 MHz

I/OPCIBus

64 bits33 MHz

100-TE-Net

GlobalFLASH

FIFOPCI Master

PCI toPCI

Bridge

VMEbus

CONTROL

CONTROL

CONTROL

CONTROL

DATA

DATA

DATA

DATA

FIFO

FIFO

FIFO

C6203Node

VIM

VIM

PCI-RACE++Bridge

PCI to VMEBridge

FrontPanel

IPFIFO

IPFIFO

C6203Node

C6203Node

C6203Node

IPFIFO

IPFIFO

1919191919



Figure 25

RRRRReal-eal-eal-eal-eal-Time RTime RTime RTime RTime Radar Radar Radar Radar Radar Recording Systemecording Systemecording Systemecording Systemecording System

The Pentek RTS 2501 in Figure 25 a highly-scalablereal-time platform for acquiring, down-converting,processing, and recording radar signals.

The heart of the RTS 2501 is the Pentek Model4205 I/O Processor featuring a 1 GHz MPC7457G4 PowerPC, mezzanine sites for both VIM and PMCmodules, and two Xilinx Virtex-II FPGAs. The G4PowerPC acts both as an executive for managing datatransfer tasks as well as performing digital signal process-ing or formatting functions.

Attached to the 4205 I/O Processor are two Model6236 Dual Channel A/D and Wideband Receiver VIMmodules, each with two 14-bit 105 MHz A/D convert-ers, two GC1012B wideband digital downconvertersand a Virtex-II FPGA.

A built-in Fibre Channel interface connects directlyto JBOD or RAID hard disks for real time storage atrates up to 100 MB/sec. Optional RACE++ interfacesprovide excellent I/O connectivity without sacrificingany of the mezzanine sites. Standard RS-232 and 100base T ethernet ports allow the PowerPC to communi-cate with a wide range of host workstations for controland software development applications.

Scalable from 2 to 80 channels in a single 6UVMEbus chassis, RTS 2501 serves equally well as adevelopment platform for advanced research projectsand proof-of-concept prototypes, or as a cost-effectivestrategy for deploying high-performance, multi-channelembedded systems.


RAID orJBOD Array

RAID orJBOD Array

FrontPanel

L3 CACHE

GT64260Dual PCI Node &Memory

Controller

MPC74571 GHz

G4 PowerPC

FibreChannel2 Gbit/sec

VME64UNIV II

SDRAM1 GB

PCI B

us 1

(64

bits

/ 66

MH

z)

P4Optional

Secondary RACE++

VIM

Mez

zani

ne I/

FVI

RTEX

-II F

PGA

PENTEK 4205 G4 PowerPC

RAC

E++

VIM

100 base TETHERNET

VIM

VIM

VIM

VIM

Mez

zani

ne I/

FVI

RTEX

-II F

PGA

PMC Site64 bits

66 MHz

FLASH

RACE++PXB++

VME

RAC

E++

PCI B

us 0

(64

bits

/ 33

MH

z)

FrontPanel

Optional

PCI

I/F

PCI I

/F


EXTCLOCK CLOCK &

SYNCGENERATOR

XTALOSC

105 MHz14-bit A/D

DIGITALRECEIVER

105 MHz14-bit A/D

DIGITALRECEIVER

BYPASS

BYPASS

LVDS CLOCK& SYNC

Clock

Clock

VIR

TEX-

II3M

GA

TE F

PG

A

CH CIN

CH DIN

EXTCLOCK CLOCK &

SYNCGENERATOR

XTALOSC

105 MHz14-bit A/D

DIGITALRECEIVER

105 MHz14-bit A/D

DIGITALRECEIVER

BYPASS

BYPASS

LVDS CLOCK& SYNC

Clock

Clock

VIR

TEX-

II3M

GAT

E F

PG

A

CH CIN

CH DIN


Pentek RTS2501 System

2020202020



Channel A input baseband signal data (blue) flowsfrom the receiver through processor nodes A and D andout to the Model 6228 Digital Upconverter using theGlobal PCI Bus. Channel B data (red) flows throughprocessor nodes B and C using the IP PCI Bus. Thesetwo completely independent signal paths allow high-bandwidth pipelined processing.

The Model 6228 Upconverter interpolates theoutput baseband signal up to a sampling rate of320 MHz and then translates it to a center frequency of70 MHz. Finally, the samples are delivered to two 320MHz 16-bit D/A converters producing analog outputsready for an IF input port. This entire transceiversystem occupies a single 6U VMEbus slot!

Two Virtex-II FPGAs, one on the 6236 and one onthe 6228 support custom signal processing algorithmsfor baseband input and output signals.

Next generation wireless standards require increas-ingly wider bandwidths to support the latest spreadspectrum techniques. The system shown in Figure 26interfaces directly with the IF stages of RF receivers andtransmitters using the Model 6236 Dual ChannelWideband Receiver and the Model 6228 Dual ChannelDigital Upconverter.

IF signals at 70 MHz with a 10 MHz bandwidth areundersampled using a sampling clock of 60 MHz, whichtranslates the band down to a center frequency of 10MHz, with signals ranging from 5 to 15 MHz. Using alocal oscillator setting of 10 MHz, the digital receiverproduces a complex (I&Q) output signal with a band-width of 10 MHz centered at DC. Baseband datasamples from both input channels are delivered across theVIM interfaces to independent Model 4294 G4 PowerPCprocessing nodes A and B.

WWWWWireless Cellular Development Systemireless Cellular Development Systemireless Cellular Development Systemireless Cellular Development Systemireless Cellular Development System

Figure 26


EXTCLOCK CLOCK &

SYNCGENERATOR

XTALOSC

105 MHz14-bit A/D

DIGITALRECEIVER

105 MHz14-bit A/D

DIGITALRECEIVER

BYPASS

BYPASS

LVDS CLOCK& SYNC

Clock

ClockVI

RTE

X-II

3M G

ATE

FPG

A

CH AIN

CH BIN


EXTCLOCKLVDS

CLOCK& SYNC

CLOCK &SYNC

GENERATOR

XTALOSC

320 MHz16-bit D/A

DIGITALUP

CONVERTERClock

Clock

VIR

TEX-

II3M

GA

TE F

PGA

CH BOUT

CH AOUT

Model 6228 2 Ch Upconverter and D/A

VIM

VIM

RACE++

Model 4294 Quad PowerPC MPC7410 Processor

GlobalSDRAM

GlobalPCIBus

64 bits66 MHz

I/OPCIBus

64 bits33 MHz

100-TE-Net

IP PCI Bus64 bits66 MHz

GlobalFLASH

FIFOPCI Master

PCI toPCI

Bridge

PCI Master

VMEbus

CONTROL

CONTROL

CONTROL

CONTROL

DATA

DATA

DATA

DATA

FIFO

FIFO

FIFO

PowerPCNode A

PowerPCNode B

PowerPCNode C

PowerPCNode D

VIM

VIM

PCI-RACE++Bridge

PCI to VMEBridge

FrontPanel

320 MHz16-bit D/A

DIGITALUP

CONVERTER

2121212121



Figure 27

Pentek offers standard off-the-shelf products foreverything from the RF translator through the D/Aconverters as shown in Figure 27.

These products are modular, easy-to-use, andflexible enough to provide a virtually unlimited range ofsystem configurations.

Using the block diagram above, we will start withthe RF translator function and work through a descrip-tion of available products from left to right.

All of the many digital receiver products offered byPentek are completely compatible and are supported bya comprehensive suite of software development tools.

As you develop your system, our fully-trained staffof application engineers can guide you through yourdesign and help you get the most out of your system.

Digital RDigital RDigital RDigital RDigital Receiver System Peceiver System Peceiver System Peceiver System Peceiver System Productsroductsroductsroductsroducts

Products

Figure 28

In case the frequency of the RF input signal is toohigh for direct A/D conversion or for undersampling, anRF receiver or translator must precede the A/D.

These devices, often referred to as “slot receivers,”are implemented using analog RF circuitry includingconventional analog mixers, amplifiers and filters. Thetuning is usually accomplished by setting the frequencyof a local oscillator so that the signal of interest istranslated down to an IF frequency, just as in our analogreceiver described at the beginning.

A typical RF translator shown in Figure 28 uses ofpopular IF frequency of 21.4 MHz. Using an IFbandwidth of 10 MHz allows any translated 10 MHzband from DC up to 2.8 GHz to be centered at 21.4MHz, well within the alias-free sampling range of a 12-bit A/D operating at 65 MHz.

In some designs, an optional A/D converter may beincluded to simplify system complexity.

Note that the local oscillator only needs to be tunedwith relatively coarse steps, say 1 MHz, to ‘ballpark’ thetranslated signal. All of the fine tuning can be per-formed by the digital receiver stage which follows. Insome dedicated applications, the signal of interest maylie within a very narrow range offrequencies and the local oscillator can be a fixedfrequency signal.

These products are available from several differentvendors.

RF TRF TRF TRF TRF Translatorranslatorranslatorranslatorranslator

RF INUp to

2.8 GHz

MULTI STAGERF MIXER

LOCALOSCILLATOR

IF FILTERand AMP

IF OUT10 MHz BW

VMEbus

12-bitA/D

A/D Out12 bits

DIGITALLOCAL

O SCILLATOR

DIGITALLOWPASS

FILTER

AUDIOAMP

SP EAKER

RFAMP

ANTENNA

A/DCONV DSP

(DEMODU-LATIO N)

D/ACONV

RFTRANS-LATOR

Pentek Product Offering

2222222222



Figure 29

PPPPProductsroductsroductsroductsroducts (continued)(continued)(continued)(continued)(continued)

A/D ConverA/D ConverA/D ConverA/D ConverA/D Converters for VMEbusters for VMEbusters for VMEbusters for VMEbusters for VMEbus TTTTTwowowowowo-----Channel 70 MHzChannel 70 MHzChannel 70 MHzChannel 70 MHzChannel 70 MHzA/D ConverA/D ConverA/D ConverA/D ConverA/D Converterterterterter

Pentek offers a number of A/D converters which actas front ends for these digital receivers. They range infrequency from 250 kHz to 210 MHz and in accuracyfrom 10 to 16 bits. All of these products are single slot6U VMEbus boards with either one or two A/D chan-nels per board. They are compatible with all of Pentek’sdigital receiver products using digital inputs.

Parallel digital data and clock are driven out throughfront panel connectors in TTL or differential ECLformat. Many of the 64xx series A/D converters are alsoavailable with FPDP (Front Panel Data Port) outputs tointerface with many other industry standard products.

LOW PASSFILTER

70 MHz10-BIT A/D

ECLDRIVERSCH 1 IN

CLOCK GENERATOR

LOW PASSFILTER

70 MHz10-BIT A/D

ECLDRIVERSCH 2 IN

EXTERNALCLOCK IN

FRONT PANELECL OUTPUT

FRONT PANELECL OUTPUT

Model 6472Model 6472

Figure 30

Figure 30 is an example of one of the 64xx seriestwo channel A/D converters, the Model 6472.

It features two identical A/D sections with built-inanti-aliasing lowpass filters set at 32 MHz. It uses eitheran internal 70 MHz oscillator or an external front panelinput as the sampling clock source. The sample clockfrequency can be changed by replacing the internaloscillator or supplying an external clock at a differentfrequency.

Two multi-pin front panel connectors deliverparallel data to the digital receivers. Because of the highsampling rate, the standard front panel outputs for theModel 6472 are at ECL levels. For lower frequencyapplications, the other A/D converters also offer TTLoutputs.

Two sets of outputs, each with independent drivers,allow quite a good deal of flexibility in cabling and indriving multiple receiver boards.

Model Rate Chans Bits6821 210 MHz 1 126472 70 MHz 2 106465 65 MHz 2 126470 70 MHz 1 106441 41 MHz 2 126425 25 MHz 1 126420 20 MHz 2 146410 10 MHz 2 146402 250 kHz 2 16

DIGITALRECEIVERDIGITAL

RECEIVERDSP

(DEMOD)DSP

(DEMOD)I/O

ADAPTERI/O

ADAPTERA/D

CONVA/D

CONV

2323232323




Digital RDigital RDigital RDigital RDigital Receiver and FPGA Selection Guideeceiver and FPGA Selection Guideeceiver and FPGA Selection Guideeceiver and FPGA Selection Guideeceiver and FPGA Selection Guide

The chart above shows a model number listing ofPentek digital receiver products showing receiver bandtype, form factor and input/output characteristics.

The center section shows the number of channels ofeach type of digital receiver used in each product. TheGateFlow IP Core 421 shown is available as a factoryinstalled option on certain products.

The right section of the chart shows the type andquantity of FPGAs used on each product. The largestdevice available is shown at the top of the column, butsmaller members of the same family are optionallyavailable.

Figure 32

For the latest complete list and full specifications ofall digital receiver products be sure to visit onlinePentek’s Software Radio Central:

www.pentek.com/sftradcentral

For the latest listings and descriptions of Pentek’sGateFlow IP be sure to visit FPGA Resources online at:

www.pentek.com/gateflow

Quantity of Receiver Channels Quantity of FPGAsTI GC Intersil TI GC Intersil TI GC TI GC IP Core XCV XC2V XC2VP

Model Type Form Input Output 4014 50214 1011 50016 4016 1012 421 600 3000 506508 NB VME Dig Comm 86509 NB VME Dig Comm 86510 NB VME Dig Comm 86514 NB VME Dig Comm 166516 NB VME Dig Comm 166532 NB VME Dig Comm 326210 NB VIM-2 Ana VIM 2 6216 WB VIM-2 Ana VIM 26230 NB VIM-4 Ana VIM 32 26231 NB VIM-2 Ana VIM 16 16232 NB VIM-4 Dig VIM 32 26235 WB VIM-2 Ana VIM 2 2 16236 WB VIM-2 Ana VIM 2 2 16250 MB VIM-2 FPDP VIM 4 26251 MB VIM-2 FPDP VIM 4 26821 MB VME Ana FPDP 27131 MB PMC Ana PCI 16 17231 MB cPCI Ana PCI 16 17631 MB PCI Ana PCI 16 1

NB = Narrowband, WB = Wideband, MB = Multiband, Dig = Digital, Ana = Analog, Comm = C40 Comm Port, FPDP = Front Panel Data Port

2424242424



Figure 31


Pentek currently offers a variety of digital receivermodels to choose from.

The first six are stand-alone 6U VME boards withcommunication ports compatible with all of Pentek’s C4x,C6000 DSP and PowerPC boards equipped with commport interfaces.

Note that the front panel connectors exactly matchthe connectors of all the A/D converters we just dis-cussed. Standard flat ribbon cable assemblies join the A/D converters and the digital receivers.

The flexibility of choosing the A/D converter andthe digital receiver modules independently permit thesystem designer to choose the most appropriate combi-nation to satisfy a virtually unlimited number of systemconfigurations.

The 6821 is the latest product that includes an A/Dconverter and delivers its outputs over FPDP (frontpanel data port) connections, also compatible with all ofPentek’s C6000 DSP and PowerPC boards, as well as awide range of third party FPDP products.

New receiver products are always under develop-ment, so be sure to contact the factory for the latestproducts.

Digital RDigital RDigital RDigital RDigital Receivers for VMEbuseceivers for VMEbuseceivers for VMEbuseceivers for VMEbuseceivers for VMEbus

DIGITALRECEIVERDIGITAL

RECEIVERDSP

(DEMOD)DSP

(DEMOD)I/O

ADAPTERI/O

ADAPTERA/D

CONVA/D

CONV

Model Recvr Channels Output 6508 Narrowband 8 Comm + VME6509 Narrowband 8 Comm + VME6510 Narrowband 8 Comm + VME6514 Narrowband 16 Comm + VME6516 Narrowband 16 Comm + VME6532 Narrowband 32 Comm + VME6821 Wideband 1 FPDP + VME

2525252525



MIXER LOW PASS FIFODIGITAL LO

FROMA/D # 1

TO ‘C40 DSPCOMM PORT DRVMUX

MIXER LOW PASS FIFODIGITAL LOMUX

MIXER LOW PASS FIFODIGITAL LO TO ‘C40 DSPCOMM PORT DRVMUX


MIXER LOW PASSDIGITAL LO TO ‘C40 DSPMUX

MIXER LOW PASSDIGITAL LOMUX



VMEbus SlaveInterface VMEbus

FROMA/D # 2

FIFO COMM PORT DRV

FIFO

FIFO COMM PORT DRV

FIFO

Control

COMM PORT REC

COMM PORT REC

FROM ‘C40 DSP

FROM ‘C40 DSP

COMM PORT REC FROM ‘C40 DSP

COMM PORT REC FROM ‘C40 DSP

Model 6508 and 6509 - All Narrowband ChannelsModel 6508 and 6509 - All Narrowband Channels


Figure 32

Eight-Eight-Eight-Eight-Eight-Channel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital Receivereceivereceivereceivereceiver

The Models 6508 and 6509 are 6U single slotboards for VMEbus featuring eight narrowband receiverchannels. Input data for each receiver can be indepen-dently selected from either of two front panelA/D inputs. Sampling rates can be up to 70 MHz.

Output data for each pair of receivers is routedthrough a front panel comm port, fully compatible withPentek’s TMS320C40 DSP boards and capable ofsupporting up to 20 MB/sec each. Alternatively, all eightchannels can be routed through a single comm port.

Again, each of the eight receivers is independentlytunable for center frequency and bandwidth. Program-ming can be done either through an input C40 comm

port for each pair of receivers or via theVMEbus.

The Model 6508 utilizes the Intersil HSP50016receiver chips with 16-bit inputs and a local oscillatorwith built-in chirp generator. The 6509 uses the TIGraychip GC1011A devices which feature 12-bit inputs,ultra-fast frequency switching, and two selectable filtercharacteristics.

The comm port “data out/control in” arrangementallows for an extremely tight coupling between thereceiver chip and the DSP to support complex tuning orfrequency agile tracking applications.

2626262626



Figure 33

MIXER LOW PASS FIFODIGITAL LO

FROMA/D # 1



FROMA/D # 4

MIXER LOW PASS FIFODIGITAL LO TO ‘C40 DSPCOMM PORT DRVMUX







FROMA/D # 2

FROMA/D # 3

FIFO COMM PORT DRV

FIFO

FIFO COMM PORT DRV

FIFO

Control



Eight-Eight-Eight-Eight-Eight-Channel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital Receivereceivereceivereceivereceiver

The Model 6510 shown in Figure 33 is another 6Usingle slot board with eight narrowband receiver chan-nels, similar to the 6508 and 6509 in Figure 32. Inputdata for each group of four receivers can be indepen-dently selected from either of two front panel A/Dinputs. With two groups, a total of four A/D inputs issupported. Sampling rates can be up to 50 MHz.

The 6510 utilizes the 16-bit input IntersilHSP50016 device.

Output data for each pair of receivers is routedthrough a front panel comm port, fully compatible withPentek’s TMS320C40 DSP boards and capable ofsupporting up to 20 MB/sec each. Alternatively, all eight

channels can be routed through a single comm port.Data from the FIFO’s can also be sent out over theVMEbus interface.

Each of the eight receivers is independently tunablefor center frequency and bandwidth, however the inputsampling rate and decimation factor for two channels ina pair must be the same. Because of limited front panelspace for the additional two A/D inputs, no comm portcontrol inputs are provided, as with the 6508 and 6509.

Programming for all tuning, bandwidth and controlis via the VMEbus.

2727272727



Figure 34

DIG REC #2DIG REC #1

FIFO

FROMA/D # 1


MUX

FROMA/D # 4


MUX

TO ‘C40 DSPMUX

MUX

TO ‘C40 DSPMUX

MUX


FROMA/D # 2

FROMA/D # 3

COMM PORT DRV

COMM PORT DRV

Control


FIFO


FIFO


FIFO


FIFO


FIFO


FIFO


FIFO



16-16-16-16-16-Channel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital Receivereceivereceivereceivereceiver

As with the Model 6514, each of the sixteen receiv-ers is independently tunable for center frequency andbandwidth, however the input sampling rate anddecimation factor for the four channels sharing a commport must be the same.

Because of limited front panel space for the addi-tional two A/D inputs, no comm port control inputs areprovided.

Programming for all tuning, bandwidth and controlis via the VMEbus.

The Model 6516 is also a 6U single slot board withsixteen narrowband receiver channels. Input data foreach group of eight receivers can be independentlyselected from either of two front panel A/D inputs.With two groups, a total of four A/D inputs are sup-ported. Sampling rates can be up to 50 MHz.

The 6516 utilizes the 16-bit input IntersilHSP50016 device.

Output data for four receiver channels is routedthrough a front panel comm port, fully compatible withPentek’s TMS320C40 DSP boards and capable ofsupporting up to 20 MB/sec each. Data from the FIFO’scan also be sent out over the VMEbus interface.

2828282828



Figure 35


The Model 6532 is a 6U single slot board with 32narrowband receiver channels. Input data for eachreceiver channel can be independently selected from anyone of the four front panel A/D inputs with eitherdifferential ECL or dual FPDP connector. Samplingrates can be up to 62.5 MHz.

The 6532 utilizes the TI Graychip GC4014, a quaddigital receiver device which also features a user-configurable FIR filter stage. Crossbar switches at thefront of each GC4014 allows all 32-channels to inde-pendently select any one of the four inputs. Output datafrom each pair of GC4014’s is processed by a FPGAlogic block which can be used to compute a sum of alleight channels. Alternatively, unsummed data from eachchannel can be passed through directly.

A total of eight FIFO’s buffer receiver data from theFPGA. FIFO outputs may be directed to the VMEbususing a VME slave interface, or to the on-boardC40 DSP which can be used to format or processreceiver output signals. Four of the C40 comm ports areavailable for front panel connections.

Each of the 32 receiver channels is independentlytunable for center frequency and bandwidth, howeverthe input sampling rate and decimation factor for each8-channel group must be the same. Programming for alltuning, bandwidth, FIR filter coefficients and control isvia the VMEbus.

The summation function by the FPGA is especiallywell suited to beamforming applications. The local C40can satisfy all DSP processing requirements for someapplications.

32-32-32-32-32-Channel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital Receivereceivereceivereceivereceiver

FIFO

X-BarSwitch

VMEbusA32D32Slave

Interface

VMEbusGC4014

QUAD DDRX-BarSwitch FPGA

(ChannelSum)

TMS320C4060 MHz

Flash512 kB

LocalSRAM512 kB

GlobalSRAM

FIFO

FIFO

X-BarSwitch

X-BarSwitch FPGA

(ChannelSum) FIFO

FIFO

X-BarSwitch

X-BarSwitch FPGA

(ChannelSum) FIFO

OVLDDetect

FIFO

X-BarSwitch

X-BarSwitch FPGA

(ChannelSum) FIFO

FourFrontPanelCommPorts

TwoP2

CommPorts

ClockMultiplierx1 to x10

EC

L or

FPD

PD

ual 1

6-bi

t Inp

uts

ECL

or F

PDP

Dua

l 16-

bit I

nput

s


GC4014QUAD DDR

GC4014QUAD DDR

GC4014QUAD DDR

GC4014QUAD DDR

GC4014QUAD DDR

GC4014QUAD DDR

GC4014QUAD DDR

2929292929



210 MHz A/D and FPGA210 MHz A/D and FPGA210 MHz A/D and FPGA210 MHz A/D and FPGA210 MHz A/D and FPGA-based Digital R-based Digital R-based Digital R-based Digital R-based Digital Receivereceivereceivereceivereceiver

Figure 36

The Model 6821 shown in Figure 36 is a 6U singleslot board with the new AD9430 12-bit 210 MHz A/Dconverter.

Capable of digitizing input signal bandwidths up to100 MHz, it is ideal for extremely wideband applica-tions including radar and spread spectrum communica-tion systems.

The sampling clock can be supplied either from afront panel input or from an internal crystal oscillator.Data from the A/D converter flows into two XilinxViretx-II Pro FPGAs where optional signal processingfunctions can be performed. The size of the FPGAs canrange from the XC2VP20 to the XC2VP50.

Because the sampling rate is well beyond conven-tional ASIC digital downconverters, none are includedon the board.


CLOCK & SYNC

GENERATOR

170 MHz12-Bit A/D

AD9430

RF IN

XTALOSC

Ext Clk

VMEbus

Control/StatusControl / Status

XILINXVIRTEX-II PRO

FPGAXC2VP50

VME Slave Interface

XILINXVIRTEX-II PRO

FPGAXC2VP50

Fs Fs/2

210 MHz12-Bit A/D

AD9430 512 MBSDRAM

128kFIFO

FPDP-IIOut 1

32 32

128kFIFO

32 32

128kFIFO

32 32

128kFIFO

32 32

FPDP-IIOut 2

FPDP-IIOut 3

FPDP-IIOut 4

512 MBSDRAM


Instead, the Pentek GateFlow IP Core 422 UltraWideband Digital Downconverter can be used in one orboth of the FPGAs to perform this function. This corecan be incorporated by the customer using the GateFlowFPGA Design Kit or ordered as a factory installedoption. Visit www.pentek.com/gateflow for moreinformation.

Two 512 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking receivers.

Either two or four FPDP-II ports connect theFPGAs to external digital destinations such as processorboards, memory boards or storage devices.

A VMEbus interface supports configuration of theFPGAs over the backplane and also provides data andcontrol paths for runtime applications.

3030303030



Figure 37

VIM, PMC, PCI and CompactPCI Digital RVIM, PMC, PCI and CompactPCI Digital RVIM, PMC, PCI and CompactPCI Digital RVIM, PMC, PCI and CompactPCI Digital RVIM, PMC, PCI and CompactPCI Digital Receiverseceiverseceiverseceiverseceivers

Pentek’s latest family of processor and software radioproducts take advantage of a new architecture calledVIM, for Velocity Interface Mezzanine.

VIM provides a direct path between daughter ormezzanine cards and quad VMEbus processor boards sothat each processor has its own private, dedicatedchannel for high-speed digital data at rates up to 400MB/sec. With four of these interfaces on each quadprocessor board the total mezzanine I/O peak bandwidthis an incredible 1600 MB/sec.

Pentek currently offers seven VIM processor boardsbased on the Texas Instruments DSP chipsTMS320C6201, C6701 and the C6203 and theMotorola AltiVec G4 PowerPC.

VIM mezzanine modules attach to these processorboards and nest in the same slot, providing very high

density single-slot sub-systems. The front panels of theVIM modules actually replace sections of the front panelof the processor boards.

VIM modules are available in two formats: the VIM-2 which connects to two processors and the VIM-4which connects to four. By attaching two different typesof VIM-2 modules, you can create unique combinationsof software radio functions and high-speed interfaces.

For an overview of VIM and a complete listing ofVIM-compatible products, visit VIM Central on ourweb site at: www.pentek.com/vimcentral.

Pentek has now introduced products in three formfactors for PCI bus: PMC (PCI Mezzanine Card), PCIboards and CompactPCI boards.

VIM-4 Module

PMC Module

VIM Processor with VIM Modules Attached(occupies a single 6U VME slot)

VIM-2 Module


PCI Board

3131313131



Figure 38


Dual Channel A/D and Narrowband RDual Channel A/D and Narrowband RDual Channel A/D and Narrowband RDual Channel A/D and Narrowband RDual Channel A/D and Narrowband Receiver - VIM-2eceiver - VIM-2eceiver - VIM-2eceiver - VIM-2eceiver - VIM-2

The Model 6210 Dual Channel Narrowband DigitalReceiver shown in Figure 38 is a VIM-2 module contain-ing two complete channels of A/D conversion, digitalreceiver and demodulation.

Each channel accepts an analog input through afront panel SMA connector. Input signals are amplifiedand bandlimited by a low pass anti-aliasing filter. Thefilter may also be bypassed to support IF inputs inundersampling applications.

Each input signal is digitized by an AD664012-bit 65 MHz A/D converter which is driven by asampling clock from an internal 64 MHz crystal oscilla-tor, an external reference input through a front panelSMA connector, or from a front panel clock and syncbus.

The clock and sync bus uses LVDS differential levelsover flat ribbon cable for synchronizing multiple boards.

The outputs of the A/D converters feed IntersilHSP50214B narrowband digital receivers with decima-tion factors from 4 to 16,384. The FIR filter coefficientsare programmable to support usable output bandwidthsas high as 929 kHz. In addition to the traditional I andQ complex outputs, the HSP50214B also includeshardware Cartesian-to-polar conversion circuitry and afrequency discriminator for generating magnitude, phaseand frequency outputs. Output data flows across the 32-bit VIM interface to the processor board.

The HSP50214B can be bypassed with a softwarecontrolled switch to deliver raw A/D samples to theprocessor instead of the receiver output signals.

65 MHz12-bit A/D

Ch 1 In

32

32

C6x orPowerPC

REG

BI-FIFO

32

32

C6x orPowerPC

REG

BI-FIFO

Intersil 50214Digital RecvrDemodulator

65 MHz12-bit A/D

Ch 2 In

Intersil 50214Digital RecvrDemodulator

Amplifier& Filter

Amplifier& Filter


BYPASS

BYPASS

3232323232




Figure 39

Dual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and Wideband Rideband Rideband Rideband Rideband Receiver - VIM-2eceiver - VIM-2eceiver - VIM-2eceiver - VIM-2eceiver - VIM-2

65 MHz12-bit A/D

Ch 1 In

32

32

C6x orPowerPC

REG

BI-FIFO

32

32

C6x orPowerPC

REG

BI-FIFO

GraychipGC1012

Digital Recvr

65 MHz12-bit A/D

Ch 2 In

Amplifier& Filter

Amplifier& Filter

GraychipGC1012

Digital Recvr

BYPASS

BYPASS


The Model 6216 Dual Channel Wideband DigitalReceiver is a the wideband counterpart of the 6210VIM-2 module, also containing two complete channelsof A/D conversion and digital receiver.

Like the 6210, each channel accepts an analog inputthrough a front panel SMA connector. Input signals areamplified and bandlimited by a low pass anti-aliasingfilter. A transformer coupling input option bypasses theamplifier and filter stages for superior performance for IFinputs up to 90 MHz in undersampling applications.

Again, like the 6210, each input signal is digitized byan AD6640 12-bit 65 MHz A/D converter which isdriven by a sampling clock from an internal64 MHz crystal oscillator, an external reference inputthrough a front panel SMA connector, or from a frontpanel clock and sync bus.

The outputs of the A/D converters drive TIGraychip GC1012 wideband digital receiver chips whichcan be set for decimation values from 2 through 64.With a decimation of 2 the maximum output bandwidthis approximately 26 MHz and with a decimation of 64,it is approximately 800 kHz.

The GC1012 can be bypassed with a softwarecontrolled switch to deliver raw A/D samples to theprocessor instead of the receiver output signals.

For new designs, the Models 6235 and 6236 arerecommended.

3333333333



Figure 40


32-32-32-32-32-Channel Narrowband RChannel Narrowband RChannel Narrowband RChannel Narrowband RChannel Narrowband Receiver with A/D and FPGA - VIM-4eceiver with A/D and FPGA - VIM-4eceiver with A/D and FPGA - VIM-4eceiver with A/D and FPGA - VIM-4eceiver with A/D and FPGA - VIM-4

32

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

VIM-4Module

Model429x

Ch 4 In

80 MHz14-bit A/D

Amp& Filter

Ch 3 In

80 MHz14-bit A/D

Amp& Filter

Ch 2 In

80 MHz14-bit A/D

Amp& Filter

Ch 1 In

80 MHz14-bit A/D

Amp& Filter

Xilinx Virtex-E FPGA

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG



The Model 6230 is a feature-packed VIM-4 modulethat includes four A/D converters, 32 narrowband digitalreceivers and FPGAs (field programmable gate arrays).Coupled with a VIM processor board, the Model 6230affords an extremely powerful receiver system at a verylow cost per channel. It exemplifies the “channelized”system concept, with each segment of the signal process-ing chain in a single VMEbus slot. The Model 6231 isthe VIM-2 version with two A/D’s and 16 narrowbandchannels.

Four front panel SMA connectors accept RF analoginputs which are conditioned by an input amplifier and abypassable low pass anti-aliasing filter. These inputs aredigitized by four AD6645 14-bit 80 MHz A/D convert-ers. The sampling clock is derived from an internal 80MHz crystal oscillator, an external front panel referenceinput or from a LVDS front panel ribbon cable clockand sync board, which can be used to synchronizedmultiple 6230s.

All four A/D digital outputs are delivered to eightGC4016 quad narrowband digital receivers, so that eachreceiver channel can independently select its source fromany one of the four A/D converters. Each receiverchannel can be independently tuned and custom filtercoefficients can be downloaded to each channel’s FIRfilter.

The narrowband receiver outputs and the widebandA/D outputs are delivered into two Xilinx Virtex-EFPGA’s with 300k or 600k gate densities (XCV300 or600). Default factory features of the FPGA include theVIM interface, digital receiver bypass (direct A/D intothe VIM interface) modes, narrowband channel selec-tion, and various packing modes. An optional FPGAdevelopment kit allows custom algorithms to be imple-mented.

Other front panel features include a connector for32 FPGA user I/O lines, two TTL inputs for triggeringand gating, and RF input overload detectors.

3434343434



Figure 41


32-32-32-32-32-Channel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital RChannel Narrowband Digital Receiver with FPDP and FPGA - VIM-4eceiver with FPDP and FPGA - VIM-4eceiver with FPDP and FPGA - VIM-4eceiver with FPDP and FPGA - VIM-4eceiver with FPDP and FPGA - VIM-4

32


4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

4 ChanNarrowBandDDR

VIM-4Module

Model429x


BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG


FPDP#1 - 40 MHzDual 16-bit Inputs

FPDP#2 - 40 MHzDual 16-bit Inputs

The Model 6232 is the digital input counterpart ofthe Model 6230. Instead of four A/D converters, theModel 6232 features two FPDP (front panel data port)input connectors. FPDP is an industry standard inter-connection scheme for transferring 32-bit digital databetween two devices using flat ribbon cable. Clockrates up to 40 MHz are supported and the next genera-tion of FPDP promises rates up to 100 MHz.

Each 32-bit FPDP port is divided into two 16-bitfields so that two digitized input signals can be broughtin over each port at sampling rates up to40 MHz. Most of Pentek’s family of 64xx A/D convert-ers feature FPDP outputs completely compatible withthe Model 6232.

All four 16-bit digital input words are connected tothe inputs of eight GC4016 quad narrowband digitalreceivers, so that each receiver channel can independentlyselect its source from any one of the four A/D converters.

Like the 6230, each receiver channel can be indepen-dently tuned and custom filter coefficients can bedownloaded to each channel’s FIR filter.

Again, using an architecture similar to the Mode6230, the narrowband receiver outputs and the wide-band FPDP digital inputs are delivered into two XilinxVirtex-E FPGA’s in sizes ranging from 300k to 600k gatedensities. Default factory features of the FPGA includethe VIM interface, digital receiver bypass (direct FPDPdata into the VIM interface) modes, narrowband channelselection, and various packing modes. An optionalFPGA development kit allows custom algorithms to beimplemented.

Other features include two clock de-skewing FIFO’sat the FPDP inputs to realign data coming from twosources with variable delay characteristics.

3535353535



Figure 42


32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

GC1012BWideband

DDR

Ch 2 In

105 MHz12 bit A/D

Bypass

GC1012BWideband

DDR

Ch 1 In

105 MHz12 bit A/D

Xilinx Virtex-II FPGA

Bypass

Transformer

Transformer


The Model 6235 Dual Channel Wideband Receiverin Figure 42 resembles the Model 6216 but adds newfeatures and higher levels of performance. Primarilyintended for digitizing wideband IF input signals, eachRF input is transformer coupled to the A/D converter tosupport input signals up to 150 MHz for undersamplingapplications.

Two AD9432 A/D converters convert the RF inputsto 12-bit samples. The sampling clock is derived froman internal 100 MHz crystal oscillator, an external frontpanel reference input or from a LVDS front panel ribboncable clock and sync board, which can be used tosynchronized multiple 6235s. As many as 80 Model6235’s can be synchronized with Pentek’s Model 9190Clock and Sync Generator to support systems with manychannels.

The A/D digital outputs feed two TI GraychipGC1012B wideband receivers, capable of accepting dataat the 100 MHz rates. These chips can be set fordecimation values to support output bandwidths from1.25 MHz to 40 MHz.

Both A/D outputs and both wideband receiveroutputs are delivering into a Xilinx Virtex-II SeriesFPGA (field programmable gate array). Here, factorydefault logic allows channel selection, triggering, receiverbypass and data packing modes.

FPGA densities range from 1 to 3 million gates(XC2V1000 or 3000) and an optional GateFlow FPGADesign Kit is available to support user-defined customalgorithms.

See the Model 6236 (page 36) for GateFlow FPGAIP Core options also available on the 6235.

Dual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and Wideband Rideband Rideband Rideband Rideband Receiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2

3636363636



Dual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and WDual Channel A/D and Wideband Rideband Rideband Rideband Rideband Receiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2eceiver with FPGA - VIM-2

32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

GC1012BWideband

DDR

Ch 2 In

105 MHz14 bit A/D

Bypass

GC1012BWideband

DDR

Ch 1 In

105 MHz14 bit A/D


Bypass

Transformer

Transformer


The Model 6236 is identical to the popular 6235but incorporates two new 105 MHz 14-bit A/D Con-verters (Analog Devices AD6645-105). These convertersoffer two additional bits of resolution for improvedaccuracy and dynamic range over the 6235.

In addition to the GateFlow FPGA Design Kit,Pentek offers several popular GateFlow IP Cores asfactory installed options for both the Models 6235 and6236.

For applications requiring FFTs, three differentinstalled FFT cores are available for either 1k or 4k pointblock sizes (Cores 401, 403 and 404). A complete radarpulse compression core has also been developed speciallyfor the 6235 and 6236 (Core 440).

Because the TI Graychip GC1012B wideband digital

receivers accept only 12-bit inputs, two of the A/Dconverter bits remain unused.

To take advantage of the additional A/D resolution,Pentek’s GateFlow Wideband Digital Receiver IP Core421 can be factory installed in the FPGA, supporting afull 16-bit input, improved dynamic range, and user-configurable FIR filter coefficients.

For this reason, the GC1012Bs are offered as anoption to save costs.

See page 10 for more information on factory in-stalled IP Cores and visit the GateFlow Resources websitefor all the latest information:

www.pentek.com/gateflow

Figure 43


3737373737



16-16-16-16-16-Channel Multiband Digital RChannel Multiband Digital RChannel Multiband Digital RChannel Multiband Digital RChannel Multiband Digital Receiver with A/D and FPGAeceiver with A/D and FPGAeceiver with A/D and FPGAeceiver with A/D and FPGAeceiver with A/D and FPGA

The Model 7131 16 Channel Multiband Receiver isa PMC (PCI Mezzanine Card) module. The 7131 PMCbe attached to a wide range of industry processor plat-forms equipped with PMC sites. The faceplate of aPMC module fits in a cutout on the front panel of theprocessor board, and the PCI bus interface to theprocessor board is made through connectors at the rearof the module.

Versions of the 7131 are also available as PCI boards(7631) and CompactPCI boards (7231). All threeproducts have identical features.

Two 14-bit 105 MHz A/D Converters (AnalogDevices AD6645) accept transformer coupled RF inputsthrough two front panel SMA connectors. Both inputsare connected to four GC4016 Quad Digital Receiverchips, so that all 16 narrowband tuners can indepen-dently select either A/D.

Four parallel outputs from the four receivers deliverdata into the Virtex II FPGA, which can be either theXC2V1000 or XC2V3000. The outputs of the two A/Dconverters are also connected directly to the FPGA tosupport the receiver bypass path to the PCI bus and for

Figure 44


direct processing of the widebandA/D signals by the FPGA.

The unit supports the channel combining mode ofthe GC4016s such that two or four individual 2.5 MHzchannels can be combined for output bandwidths of 5MHz or 10 MHz, respectively.

The sampling clock can be sourced from an internal100 MHz crystal oscillator or from an external clocksupplied through an SMA connector or the LVDS clock/sync bus on the front panel. The LVDS bus allowsmultiple modules to be synchronized with the samesample clock, gating, triggering and frequency switchingsignals. Up to 80 modules can be synchronized with theModel 9190 Clock and Sync Generator. Custominterfaces can be implemented by using the 64 userdefined FPGA I/O pins on the P4 connector.

The FPGA is fully supported with the GateFlowFPGA Design Kit and GateFlow FPGA IP Core Library.Software drivers support VxWorks, Windows and Linuxprocessor board operating systems.

Model 7131 PMC • Model 7631 PCI • Model 7231 cPCIModel 7131 PMC • Model 7631 PCI • Model 7231 cPCI

VIR

TEX

-II3M

gat

e FP

GA

EXTERNALCLOCK IN CLOCK &

SYNCGENERATOR OSC

105 MHz14bit A/D

LVDS CLOCK& SYNC BUS

Clock

105 MHz14bit A/D

QUADRECEIVER

QUADRECEIVER

QUADRECEIVER

QUADRECEIVER

CH A IN

CH B IN

PCI Bus

PCI INTERFACE64 BITS / 66 MHz

P4UserI/O

Model 7131PMC Module

Model 7631PCI Board

3838383838



Figure 45


Dual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with Virtex-II FPGAs - VIM-2tex-II FPGAs - VIM-2tex-II FPGAs - VIM-2tex-II FPGAs - VIM-2tex-II FPGAs - VIM-2

32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG


SRAM64k x 16

SRAM64k x 16

SRAM64k x 16

SRAM64k x 16

FPDP #132-bits - 40 MHz




While not actually containing a digital receiver, theModel 6250 Dual FPDP Adapter in Figure 45 supportsvery high-performance custom signal processing func-tions by incorporating two high-density FPGAs (fieldprogrammable gate arrays).

Two bidirectional FPDP ports transfer 32-bit data atclock rates up 40 MHz. Support for FPDP-II portsallows clock rates as high as 100 MHz (400 MB/sec.)

The FPDP inputs are connected to two XilinxVirtex-II FPGAs with densities of either 1 or 3 milliongates each (XC2V1000 or 3000). The FPGAs areclocked from an on-board 100 MHz crystal oscillator.Factory default FPGA configuration code includes theFPDP interface and the VIM interface so standard unitscan be used as fast FPDP adapter.

Custom FPGA configuration code can be developedusing the optional GateFlow FPGA Design Kit contain-ing the VHDL source for the factory default configura-

tion and provisions for adding user-defined algorithms.Each FPGA is equipped with two 64k x 16 SRAMs forstoring data or coefficients, creating a more powerfulenvironment for custom FPGA applications and incor-poration of third party IP cores.

Pentek’s GateFlow IP Core Library includes real-timeFFTs, wideband digital receivers and pulse compressorswhich can be used with the GateFlow Design Kit orordered as factory installed options. Visit Pentek’sGateFlow Resources website for the latest information atwww.pentek.com/gateflow.

Most of Pentek’s family of 64xx and 6821 A/Dconverters feature FPDP outputs completely compatiblewith the Model 6250, delivering sampling rates from250 kHz to 210 MHz. Since the 6250 can also transmitFPDP data, it can be connected to many other Pentekproducts including digital receivers, digital memorybuffers and DSP boards.

3939393939



Figure 46


Dual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with VirDual FPDP Adapter with Virtex-II Ptex-II Ptex-II Ptex-II Ptex-II Pro FPGAs and SDRAM - VIM-2ro FPGAs and SDRAM - VIM-2ro FPGAs and SDRAM - VIM-2ro FPGAs and SDRAM - VIM-2ro FPGAs and SDRAM - VIM-2

32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

Xilinx Virtex-II Pro FPGA

SDRAM16M x 32

FLASH8M x 16




Xilinx Virtex-II Pro FPGA

SDRAM16M x 32

FLASH8M x 16

A GateFlow FPGA Design Kit is available forcustom algorithm development. It includes all of theVHDL source code for the standard factory functionsand library functions to support the SDRAM memory.

When used in conjunction with FPDP data sourceslike Pentek’s Series 64xx A/D Converters or the new6821 210 MHz 12-bit A/D Converter, the 6251 offerssignificant signal processing horsepower.

Pentek’s GateFlow Wideband Digital Receiver IPCores 421 and 422 can be used to provide high-speedand high-dynamic range digital down conversion.GateFlow FFT IP Cores 401, 404, and 404 deliverworld-class, real-time time-to-frequency domain conver-sion. The GateFlow Pulse Compression IP Core 440handles real-time radar pulse compression with block-floating point precision. Visit the GateFlow Resourceswebsite at www.pentek.com/gateflow.

The Model 6251 is the next generation successor tothe popular 6250 shown on the previous page.

Major new features of 6251 are two Virtex-II ProFPGAs which replace the Virtex-II devices with twice theresources plus two embedded microcontrollers.

In addition, the four 128 kB SRAMs on the 6250have been replaced with 64 MByte SDRAMs on the6251, increasing the memory capacity of the module bya factor of 256!

These larger memories can now support long digitaldelay lines and large data buffers for transient captureapplications. The 16 MB FLASH memories can be usedfor coefficient or boot code storage for the embeddedmicrocontrollers.

The FPGA sizes range from the XC2VP20 to theXC2VP50 to handle a wide range of applications.

4040404040



VIM-2

RF or IF Out

Amplifier& Filter

200 MHz12-bit D/A

AD9856200 MHz

InterpolatorUp-Converter

Unpack

RF or IF Out

Amplifier& Filter

Unpack

200 MHz12-bit D/A

AD9856200 MHz


200 MHz12-bit D/A

AD9856200 MHz



32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG

Figure 47


Dual Channel WDual Channel WDual Channel WDual Channel WDual Channel Wideband Digital Upconverideband Digital Upconverideband Digital Upconverideband Digital Upconverideband Digital Upconverter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2

The Model 6229 Dual Channel Wideband DigitalUpconverter in Figure 47 complements the digitalreceiver products by offering an analogous transmit sidefunction.

The Model 6229 employs two AD9856 DigitalUpconverters containing several stages of signal process-ing within a single monolithic device. The VIM proces-sor delivers complex (I & Q) digital baseband signals atdata rates from audio up to25 Msamples/sec.

The AD9856 uses an interpolation filter to up-sample these inputs to a sampling rate of 200 MHz. Thesignals are then translated in frequency using a quadra-ture mixer and programmable local oscillator.

This single-sideband frequency translation allows thebase band signal to be placed anywhere between DC and80 MHz, suitable for many IF inputs for transmitters orexciters.

Finally, the translated signals are converted to analogby a 12-bit 200 MHz D/A converter and delivered tofront panel SMA connectors though an output amplifierstage.

The Model 6229 is ideal for developers of newwireless standards, for testing receiver systems and as ageneral purpose arbitrary waveform generator. The localoscillator can also be used as CW sinewave oscillatorwith outputs programmable from DC to80 MHz.

4141414141



Dual Channel WDual Channel WDual Channel WDual Channel WDual Channel Wideband Digital Upconverideband Digital Upconverideband Digital Upconverideband Digital Upconverideband Digital Upconverter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2ter and D/A - VIM-2

Figure 48

The Model 6228 Dual Channel Wideband DigitalUpconverter in Figure 48 is the next generation versionof the Model 6229.

It uses two Texas Instruments DAC5686 DigitalUpconverter chips which include an interpolation filter,a local oscillator, a complex mixer and two16-bit D/A converters.

When operated as a digital upconverter, the maxi-mum clock rate is 320 MHz. This allows digitalbaseband complex input sampling rate up to 80 MHzand output IF frequencies tunable up to 160 MHz.

For the real IF output mode, only one of the16-bit D/A converters of each DAC5686 is used.For the complex output mode, both D/A converters areused to deliver both I and Q analog signals.

When operated in the D/A only mode, the fre-quency translation functions are not used. In this mode,the maximum clock frequency for the interpolation filterand D/A converters becomes 500 MHz. With twoupconverter chips in the module, four independent datastreams can be delivered to the four 16-bit D/A convert-ers, with optional interpolation for generation of signalbandwidths as high as 200 MHz.

The Virtex-II FPGA can be used as a pre-processorfront end for the upconverters to implement additionalinterpolation filtering or other custom signal processingfunctions. An arbitrary waveform generator could beconstructed using internal FPGA memory for waveformstorage. A complete GateFlow FPGA Design Kit isavailable.

VIM-2

RF or IF Out

500 MHz16-bit D/A

DAC5686Interpolator

Up-Converter

32

Model429x

BI-FIFO

C6x orPowerPC

REG

32

BI-FIFO

C6x orPowerPC

REG


500 MHz16-bit D/A

DAC5686Interpolator

Up-Converter

AmpFilter

AmpFilter

RF or IF Out

AmpFilter

AmpFilter



4242424242



Figure 49

• Reduces DSP Processing Demands

• Very Fast Tuning - No PLL’S

• Fast Bandwidth Selection

• Zero Frequency Drift and Error

• Precise, Stable Filter Characteristics

• Excellent Dynamic Range

Figure 50


SummarSummarSummarSummarSummaryyyyy

To summarize, we first restate the major benefit ofdigital receivers:

Digital receivers can dramatically reduce the DSPrequirements for systems which need to process signalscontained within a certain frequency band of a widebandsignal.

The fast tuning of the digital local oscillator and theeasy bandwidth selection in the decimating digital filtermake the digital receiver easy to control.

Since all of the circuitry uses digital signal process-ing, the characteristics are precise, predictable, and willnot drift with time, temperature or aging. This alsomeans excellent channel-to-channel matching and no needfor calibration, alignment or maintenance.

With the addition of the new VIM architectures,dramatic increases in systems density have been coupledwith a significantly lower cost per channel. FPGAtechnology allows users to incorporate custom algo-rithms right at the front end of these systems.

As we have seen, there are inherently many benefitsand advantages to you when using digital receivers. Wehope that this introduction to digital receivers has beeninformative. We stand ready to discuss your require-ments and help you configure a complete digital receiversystem.

For all of the latest information about Pentek’sdigital receivers, DSP boards and data acquisitionproducts, be sure to visit Pentek’s comprehensive website regularly at: www.pentek.com.

Pentek offers an impressive array of VMEbus DSPboards featuring the TMS320 family of processorproducts from Texas Instruments and the AltiVec G4PowerPC from Motorola.

Processor densities range from one to eight DSP’sper board with many different memory and interfaceoptions available.

The Model 4290/91/92/93 series of VIM quadprocessor boards features Texas Instruments latestTMS320C6000 family of fixed and floating pointDSP’s, representing a 10-fold increase in processingpower over previous designs.

The Model 4294 and 4295 VIM processor boardsfeatures four MPC74xx G4 PowerPC processors utiliz-ing the AltiVec vector coprocessor capable of deliveringseveral GFLOPS of processing power.

The 4205 G4 PowerPC I/O Processor accepts bothVIM and PMC mezzanines and includes built-in dualRACE++ interfaces plus Fibre Channel.

Once again, the ability of the system designer tofreely choose the most appropriate DSP processor foreach digital receiver application, facilitates systemrequirement changes and performance upgrades.

Full software development tools are available forworkstations running Windows, Solaris, and Linux withmany different development system configurations avail-able.

DSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbus

• Motorola AltiVec G4 PowerPC

• Texas Instruments DSPs:TMS320C3x, C4x, C6000

• Single, Dual, Quad andOctal Processor Versions

• VIM, PMC, MIX Mezzanines

• RACEway, RACE++, FPDP,FPDP-II, and FibreChannel

pentek digital

Documents

digital receiver counterpart

benefits of digital

operationy of operationy

upper saddle river

park way

significant benefits

embedded systems

electronic systems