pe lab manual 2013 autonomous

8/11/2019 PE Lab Manual 2013 Autonomous

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POWER ELECTRONICS

Laboratory Manual

Department of Electrical and Electronics Engineering

Gokaraju Rangaraju I nstitute of Engineer ing & Technology

BACHUPALLY, MIYAPUR, HYDERABAD-500072


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POWER ELECTRONICS

LABORATORY

Name:______________________________

Roll No:_________________ Section:____

Branch:____ Academic year:___________

Gokaraju Rangaraju I nstitute ofEngineer ing & Technology

BACHUPALLY, MIYAPUR, HYDERABAD-500072


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CONTENTSName of the experiment PAGE NO

1) Generation of Cosine Waveform 4

2) Design of DC power supply circuit 7

3) Inverse Cosine control Scheme 10

SIMULATION CIRCUITS

4) 1-Phase Half Wave controlled converter with R-load 16

5) 1-Phase Half Wave controlled converter with RL-load 20

6) 1-Phase Full controlled converter with R-load 24

7) 1-Phase Full controlled converter with RL-load 28

8) 1-Phase semi converter with RL-load 33

9) 1-Phase AC Voltage controller with R-Load 37

10) 1-Phase AC voltage controller using RL-load 41

11) 1-Phase Cyclo converter using R-Load 45

12) 555- Timer Triggering circuit 49

HARDWARE DESIGN CIRCUITS USING THE TRIGGERING CIRCUITSPROJECT WORK

13) AC voltage controller Using UJT triggering circuit 54

14) Semi converter using UJT triggering circuit 57

15) Full controlled converter Using UJT Triggering circuit 60

16) Basic Step Down chopper using 555Timer 63

17) Basic Step up chopper using 555-Timer 66

18) Semi Converter using Inverse Cosine Control scheme 69

19) Half wave controlled converter using Inverse Cosine control scheme 72

20) Full controlled converter using Inverse Cosine control scheme 75


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EXPERIMENT-1

GENERATION OF COSINE WAVEFORM

AIM:To Generate cosine waveform

APPARATUS:

230V AC supply

230/8-0-8 Center tapped Transformer

10k resistor

0.22uF, 63V capacitor

47uF, 63V capacitor

GPCB

BURGER STICKS

CRO

CRO probes -2

CIRCUIT DIAGRAM:


5/127

THEORY:

Generation of the cosine wave form is required for the inverse cosine control scheme. Usually adopted in line

commutated thyristor control circuits.

WAVEFORMS:


6/127

Waveforms:

Result:


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EXPERIMENT-2

DESIGN OF DC-POWER SUPPLY

AIM: Design of DC- power supply circuit

APPARATUS:

PCB

Center tapped transformer 230/15-0-15

230V AC power supply

7812, 7912 voltage regulators

1N4007 Diodes

1000uF, 35V capacitors 2

220uF, 35V capacitors 2

0.1uf capacitors 4

CRO

CRO probes

JUMPERS

CIRCUIT DIAGRAM:


8/127

THEORY:

The circuit Diagram for generation of 12V DC power supply is shown. It consists of AC

supply, center tapped transformer, diode bridge rectifier, voltage regulators, capacitors.

230V, 50Hz AC supply is given to primary side of center tapped transformer. This voltage is stepped

down to a voltage of 15VAC, 50Hz which is available at the secondary side of the transformer. This15VAC voltage is converted to DC voltage by using a diode bridge rectifier as shown. The capacitors

are used to eliminate the filters and Harmonics. The output voltage (15V) of bridge rectifier is

regulated to 12DC by using voltage regulators 7812 and 7912.

We can observe the +12V DC at the output terminal of regulator 7812 and -12V DC at the output

terminal of regulator 7912.

WAVEFORMS:


9/127

Waveforms:

Result:


10/127

EXPERIMENT-3

INVERSE COSINE CONTROL SCHEME

AIM: Design of Firing Circuit to Trigger a Thyristor using Inverse cosine method

APPARATUS:

Transformers 230/12-0-12 2

CRO probes, CRO

Connecting wires, multimeter

Soldering Rod, lead

Resistors:

2.2k 4 0.5w

10k 4 0.5w

47k 4 0.5w

4.7k 3

820k 2

27k 2

22k 4

3.3 ohms 2

220 ohms 2

1k 6

100 ohms 4

Potentiometer

10K 1 1w

Capacitors:

0.022pf 2

0.1uf 2

47uf 2

DIODES: 1N4148 14

Z10 2

ICS

LM741 2


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LM339 1

LM555N 2

Transistors:

2222A 2

2218 2

Pulse Transformer

1:1:1 2

IC bases:

16 pin 1

8 pin 4

Burg sticks 4 strips


12/127

CIRCUIT DIAGRAM:


13/127

THEORY:

Thecircuitdiagram of firing pulse generation is as shown in above figure. Firing

pulses are generated by using inverse cosine control scheme. Cosine wave is given as

input to this firing circuit .This is compared with the DC voltage to generate firing

pulses. The pulses in the positive half cycle are generated by comparing the Inverse

cosine wave with the DC voltage and pulses in the negative half cycle are generated by

comparing the cosine wave with the DC voltage. By varying the DC voltage value

from +12v to -12v the firing angle is varied accordingly. These pulses are given as

triggering pulses to the Thyristors.

WAVEFORMS:

Case1: Firing angle ()


15/127

Waveforms:

Result:


16/127

Experiment No 4

1-PHASE HALF WAVE CONTROLLED CONVERTER

WITH R-LOAD

Aim: To study the performance of a single phase half wave controlled converterwith R-load.

Apparatus: 1. Power Electronics Trainer Kit2. Firing Circuit3. CRO

Circuit Diagram:

Theory:

In the period 0 < t/; the SCR is forward biased. Thencurrent through the load and voltage drop across the load are zero, and all the

supply voltage appears between the anode and cathode of the SCR. Let the SCR be

triggered at an angle of (0


17/127

Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.

3. Observe the load voltage on the CRO and note down the firing angle.

4. Draw the waveforms and calculate the Average and RMS value of output voltage.

Calculations:


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WAVEFORMS:


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Waveforms:

Result:


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Experiment No 5

1-PHASE HALF WAVE CONTROLLED CONVERTER

WITH RL-LOAD

Aim: To study the performance of a single phase half wave controlled converterwith RL-load.

Apparatus: 1. Power Electronics Trainer Kit2. Firing Circuit

3. CRO

4. CRO probes

Circuit Diagram: Vs = 1-Phase 50Hz, 230V supply

Theory:

In the period 0 < t/; the SCR is forward biased. Then current through the load

and voltage drop across the load are zero, and all the supply voltage appears

between the anode and cathode of the SCR. Let the SCR be triggered at an angle of

(0


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of Inductor, energy is stored during the positive Half cycle and this stored energy is

supplied to the SCR to remain in conducting mode even if the supply is negative.

This amount of energy stored depends on the value of inductor. That is more the

value of inductor more is the energy stored and SCR will remain in conducting state

up to the angle .The load current continues to flow until the energy stored in the

Inductor becomes zero.

After the current becomes zero SCR is reverse biased and load voltage is Zero

hence, total supply voltage appears across the SCR up to 2.

Again during the third positive Half cycle supply is positive, SCR is forward biased

and if we give triggering SCR starts conducting and this cycle repeats.

Here is called Extinction Angle.

Procedure:



3. Observe the load voltage on the CRO and note down the firing angle and Extinction

angle.

4. Draw the waveforms and calculate the Average and RMS value of output voltage.

Calculations:


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WAVEFORMS:


23/127

Waveforms:

Result:


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Experiment No 6

1-PHASE FULL CONTROLLED CONVERTER WITH R-

LOAD

Aim: To study the performance of a single phase Full wave controlled converterwith R-load.


3. CRO

Circuit Diagram:

Theory:

In the period 0 < t/; the SCRs T1 and T2 are forward

biased and the SCRs T3 and T4 are reverse biased. Then current through the load

and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at


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an angle of (0


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WAVEFORMS:


27/127

Waveforms:

Result:


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Experiment No 7

1-PHASE FULL CONTROLLED CONVERTER WITH RL-LOAD

Aim: To study the performance of a single phase Full wave controlled converterwith RL-load.


Circuit Diagram:

Theory:In the period 0 < t /; the SCRs T1 and T2 are forward

biased and the SCRs T3 and T4 are reverse biased. Then current through the load

and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at

an angle of (0


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across the SCRs is zero when they are conducting (SCR is assumed ideal).

In the period ( /


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Calculations:


31/127

WAVEFORMS:


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Waveforms:

Result:


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Experiment No 8

1-PHASE SEMI CONVERTER WITH RL-LOAD

Aim: To study the performance of a single phase Semi converter with RL-load.


3. CRO

Circuit Diagram:

Theory:

In the period 0 < t/; the SCRs T1 and Diode D1 are forward biased and the

SCR T2 and Diode D2 are reverse biased. Then current through the load and

voltage drop across the load are zero. Let the SCR T1 be triggered at an angle of

(0


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(+)/


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WAVEFORMS:


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Waveforms:

Result:


37/127

Experiment No 9

1-PHASE AC VOLTAGE CONTROLLER WITH R-LOAD

Aim: To study the performance of a single phase AC Voltage controller with R-load.


Circuit Diagram:

Theory:In the period 0 < t/; The SCR T1 is forward biased and SCR T2 is reverse

biased. Let the T1be triggered at an angle of (0


38/127

Procedure:




4. Draw the waveforms and calculate the RMS value of output voltage.

Calculations:


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WAVEFORMS:


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Waveforms:

Result:


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Experiment No 10

1-PHASE AC VOLTAGE CONTROLLER WITH RL-

LOAD

Aim: To study the performance of a single phase AC Voltage controller withRL-load.


Circuit Diagram:

Theory:In the period 0 < t/; the SCRs T1 is forward biased and the SCR T2 is reverse

biased. Then current through the load and voltage drop across the load are zero. Let

the SCR T1 be triggered at an angle of (0


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remain in conducting state up to the angle for Discontinuous conduction mode

(


43/127

WAVEFORMS:


44/127

Waveforms:

Result:


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Experiment No 11

1-PHASE STEP DOWN CYCLO CONVERTER WITH R-

LOAD

Aim: To study the performance of a single phase Cyclo converter with R-load.Apparatus: 1. Power Electronics Trainer Kit

2. Firing Circuit3. CRO

Circuit Diagram:

Theory:Cyclo converter is a circuit which converts the input voltage at one frequency to the

output vtage at different frequecy.

During the positive half cycle Thyristors P1, N2 are forward biased and Thyristors

P2 and N1 are reverse biased. The circuit is designed for step down cyclo converter

for a output frequency of = .To get the desired frequency the Thyristors are

triggered accordingly.

During the first positive half cycle P1 and N2 are forward biased and to get the

positive output voltage, P1 is triggered at an angle of (+). During the next

positive half cycle P2 and N1 are forward biased, to get required output voltage

thyristor P2 is triggered. In the next half cycle P1 is triggered next N1,N2 and again


46/127

N1 are triggered accordingly. This process repeats.

Procedure:





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WAVEFORMS:


48/127

Waveforms:

Result:


49/127

Experiment No 12

555- TIMER TRIGGERING CIRCUIT

Aim: To generate pulses using 555 Timer Circuit


Circuit Diagram:

Output


50/127

Theory:

The 555 has three main operating modes, Monostable, Astable, and Bistable. Each mode represents a

different type of circuit that has a particular output.

Astable mode:

AnAstable Circuithas no stable state - hence the name "astable". The output continually switches

state between high and low without without any intervention from the user, called a 'square' wave.

This type of circuit could be used to give a mechanism intermittent motion by switching a motor on

and off at regular intervals. It can also be used to flash lamps and LEDs, and is useful as a 'clock'

pulse for other digital ICs and circuits.

Output Waveforms in Astable Mode:

Monostable mode

AMonostable Circuitproduces one pulse of a set length in response to a trigger input such as a push

button. The output of the circuit stays in the low state until there is a trigger input, hence the name

"monostable" meaning "one stable state". his type of circuit is ideal for use in a "push to operate"

system for a model displayed at exhibitions. A visitor can push a button to start a model's mechanismmoving, and the mechanism will automatically switch off after a set time.

Output Waveforms in Monostable Mode:
http://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.htmlhttp://www.555-timer-circuits.com/operating-modes.html


51/127

Procedure:

1. Connect the firing circuit as shown in the circuit diagram

2. Simulate it using Multisim

3. Observe the pulses at the output

4. Vary the circuit parameters to observe the changes.


52/127

Waveforms:

Results:


53/127

HARDWARE CIRCUIT DESIGNS


54/127

Experiment No 13

AC VOLTAGE CONTROLLER USING UJT TRIGGERING

CIRCUIT

Aim:

Circuit Diagram:


55/127


56/127


57/127

Experiment No 14

SEMI CONVERTER USING UJT TRIGGERING

CIRCUIT

Aim:

Circuit Diagram:


58/127


59/127


60/127

Experiment No 15

FULL CONTROLLED CONVERTER USING UJT

TRIGGERING CIRCUIT

Aim:

Circuit Diagram:


61/127


62/127


63/127

Experiment No 16

BASIC STEP DOWN CHOPPER USING 555TIMER

Aim:

Circuit Diagram:


64/127


65/127


66/127

Experiment No 17

BASIC STEP UP CHOPPER USING 555-TIMER

Aim:

Circuit Diagram:


67/127


68/127


69/127

Experiment No 18

SEMI CONVERTER USING INVERSE COSINE

CONTROL SCHEME

Aim:

Circuit Diagram:


70/127


71/127


72/127

Experiment No 19

HALF WAVE CONTROLLED CONVERTER USING

INVERSE COSINE CONTROL SCHEME

Aim:

Circuit Diagram:


73/127


74/127


75/127

Experiment No 20

FULL CONTROLLED CONVERTER USING INVERSE

COSINE CONTROL SCHEME

Aim:

Circuit Diagram:


76/127


77/127


78/127

DATA SHEETS

2N2222

MUR 110

1N4148

IRFZ44

LM 7815

TL 494C

LM339

LM555

TYN612

TL3843


79/127

PIN DESCRIPTION

1 emitter

2 base

3 collector, connected to case

NPN switching transistors 2N2222; 2N2222A

FEATURES

High current (max. 800 mA)

Low voltage (max. 40 V).

APPLICATIONS

Linear amplification and switching.

PINNING

DESCRIPTION1

3

PNP complement: 2N2907A. 2

3 MAM2641

Fig.1 Simplified outline (TO-18) and symbol.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCBO collector-base voltage

2N2222

2N2222A

open emitter

60

75

V

V

VCEO collector-emitter voltage

2N2222

2N2222A

open base

30

40

V

V

IC collector current (DC) 800 mA

Ptot total power dissipation Tamb 25 C 500 mW

hFE DC current gain IC =10mA;VCE =10 V 75

fT transition frequency

2N2222

2N2222A

IC = 20 mA; VCE = 20 V; f = 100 MHz

250

300

MHz

MHz

toff

turn-off time ICon = 150 mA; IBon = 15 mA; IBoff = 15 mA 250 ns


80/127


LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).


VCBO collector-base voltage

2N2222

2N2222A

open emitter

60

75

V

V

VCEO collector-emitter voltage

2N2222

2N2222A

open base

30

40

V

V

VEBO emitter-base voltage

2N22222N2222A

open collector

56

VV

IC collector current (DC) 800 mA

ICM peak collector current 800 mA

IBM peak base current 200 mA

Ptot total power dissipation Tamb 25 C 500 mW

Tcase 25 C 1.2 W

Tstg storage temperature 65 +150 C

Tj junction temperature 200 C

Tamb operating ambient temperature 65 +150 C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 350 K/W

Rth j-c thermal resistance from junction to case 146 K/W


81/127


CHARACTERISTICS

Tj = 25 C unless otherwise specified.


ICBO collector cut-off current

2N2222 IE =0;VCB =50V 10 nA

IE = 0; VCB = 50 V; Tamb = 150 C 10 A

ICBO collector cut-off current

2N2222A IE =0;VCB =60V 10 nA

IE = 0; VCB = 60 V; Tamb = 150 C 10 A

IEBO emitter cut-off current IC =0;VEB =3V 10 nA

hFE DC current gain IC =0.1mA;VCE =10 V 35IC =1mA;VCE =10 V 50

IC =10mA;VCE =10V 75

IC = 150 mA; VCE = 1 V; note 1 50

IC = 150 mA; VCE = 10 V; note 1 100 300

hFE DC current gain

2N2222A

IC = 10 mA; VCE = 10 V; Tamb = 55 C

35

hFE DC current gain

2N2222

2N2222A

IC = 500 mA; VCE = 10 V; note 1

30

40

VCEsat collector-emitter saturation voltage2N2222 IC = 150 mA; IB = 15 mA; note 1 400 mV

IC = 500 mA; IB = 50 mA; note 1 1.6 V

VCEsat collector-emitter saturation voltage

2N2222A IC = 150 mA; IB = 15 mA; note 1 300 mV

IC = 500 mA; IB = 50 mA; note 1 1 V

VBEsat base-emitter saturation voltage

2N2222 IC = 150 mA; IB = 15 mA; note 1 1.3 V

IC = 500 mA; IB = 50 mA; note 1 2.6 V

VBEsat base-emitter saturation voltage

2N2222A IC

= 150 mA; IB

= 15 mA; note 1

0.6 1.2 V

IC = 500 mA; IB = 50 mA; note 1 2 V

Cc collector capacitance IE = ie = 0; VCB = 10 V; f = 1 MHz 8 pF

Ce emitter capacitance

2N2222A

IC = ic = 0; VEB = 500 mV; f = 1 MHz

25 pF

fT transition frequency

2N2222

2N2222A

IC = 20 mA; VCE = 20 V; f = 100 MHz

250

300

MHz

MHz

F noise figure

2N2222A

IC = 200 A; VCE = 5 V; RS = 2 k ;

f = 1 kHz; B = 200 Hz 4 dB


82/127


SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITSwitching times (between 10% and 90% levels); see Fig.2

ton turn-on time ICon = 150 mA; IBon = 15 mA; IBoff = 15 mA 35 ns

Td delay time 10 ns

Tr rise time 25 ns

toff turn-off time 250 ns

Ts storage time 200 ns

Tf fall time 60 ns

Note

1. Pulse test: tp 300 s; 0.02.

VBB VCC

(probe)

RB RC

Vo (probe)oscilloscope oscilloscope

450

R2V

i DUT

450

R1

MLB826

Vi = 9.5 V; T = 500 s; tp = 10 s; tr = tf 3 ns.

R1 = 68 ; R2 = 325 ; RB = 325

; RC = 160 . VBB = 3.5 V; VCC = 29.5 V.

Oscilloscope input impedance Zi = 50 .

Fig.2 Test circuit for switching times.


83/127

w MA M B M


PACKAGE OUTLINE

Metal-can cylindrical single-ended package; 3 leads SOT18/13

j seating plane

B

1b

k

2D1

3

a

A D A L

0 5 10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT A a b D D1 j k L w

mm 5.314.74 2.54

0.470.41

5.455.30

4.704.55

1.030.94

1.10.9

15.012.7 0.40 45

OUTLINEVERSION

REFERENCES

IEC JEDEC EIAJ

EUROPEAN

PROJECTIONISSUE DATE

SOT18/13 B11/C7 type 3 TO-1897-04-18


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MCC

Part Number

Maximum

RecurrentPeak Reverse

Voltage

Maximum

RMS Voltage

Maximum DC

Blocking

Voltage

MUR105 50V 35V 50VMUR110 100V 70V 100VMUR115 150V 105V 150VMUR120 200V 140V 200VMUR140 400V 280V 400VMUR160 600V 420V 600VMUR180 800V 560V 800V

MUR1100 1000V 700V 1000V

Average Forward

CurrentIF(AV) 1 A TA = 55 C

Peak Forward SurgeCurrent

IFSM 35A 8.3ms, half sine

Maximum

Instantaneous

Forward VoltageMUR105-115

MUR120-160MUR180-1100

VF .975V1.35V1.75V

IFM = 1.0A;

TA = 25 C

Max imum DCReverse Current AtRated DC Blocking

Voltage

IR 5 A50 A

TA = 25 C

TA = 150 C

Maximum ReverseRecovery Time

MUR105-120MUR140-160

MUR180-1100

Trr 45ns60ns

75ns

IF=0.5A, IR=1.0A,Irr=0.25A

Typical Junction

CapacitanceCJ 20pF

Measured at

1.0MHz, VR=4.0V

M C C MUR105

THRU

MUR1100

FeaturesHigh Surge Capability

Low Forward Voltage DropHigh Current Capability

Super Fast Switching Speed For High Efficiency

Maximum RatingsOperating Temperature: -50 C to +150 C

Storage Temperature: -50 C to +150 C

1 Amp Super Fast

Recovery Rectifier

50 to 1000 Volts

DO-41

D

Electrical Characteristics @ 25 C Unless Otherwise Specified ACathode

Mark

B

D

C

DIMENSIONS

DIMINCHES MM

NOTEMIN MAX MIN MAXA .166 .205 4.10 5.20B .080 .107 2.00 2.70C .028 .034 .70 .90D 1.000 --- 25.40 ---

*Pulse Test: Pulse Width 300 sec, Duty Cycle 1%


85/127

TJ=25

MUR105 thru MUR1100 M C CFigure 1

Typical Forward Characteristics

20

10

6 1.5

Figure 2

Forward Derating Curve

Amps

4

2

1

.6

.4

.2

.06

25 C

MUR105-115

MUR180-1100

MUR120-160

Amps

1.25

1.0

.75

.5

Single Phase, Half Wave

60Hz Resistive or Inductive Load

.040

25 50 75 100 125 150 175

.02

.01.5 .7 .9 1.1 1.3 1.5

Volts

C

Average Forward Rectified Current - Amperes versus

Ambient Temperature - C

Instantaneous Forward Current - Amperes versusInstantaneous Forward Voltage - Volts

Figure 3

Junction Capacitance

100

60

40

20

pF10

6

4

2

1.1 .2 .4 1 2 4

Volts

10 20 40 100 200 400 1000

Junction Capacitance - pF versus

Reverse Voltage - Volts
http://www.mccsemi.com/


86/127

TA 15 C

TA 10 C

MUR105 thru MUR110M C C

100

60

40

Figure 4

Typical Reverse Characteristics

Figure 5Peak Forward Surge Current

60

50

20

10

6

4

2

Amps 1

.6

40

30

Amps20

10

0

1 2 4 6 8 10 20

Cycles

40 60 80 100

.4

.2

.1

.06

.04

TA=

Peak Forward Surge Current - Amperes versus

Number Of Cycles At 60Hz - Cycles

.02

.0120 40 60 80 100 120 140

Volts

Instantaneous Reverse Leakage Current - MicroAmperes

versus

Figure 6

Reverse Recovery Time Characteristic And Test Circuit Diagram

50 10

+0.5Atrr

25VdcPulse

Generator

Note 2

0

-0.25

1

Notes:

1. Rise Time = 7ns max.

Oscilloscope

Note 1-1.0

1cmSet Time Base for 20/100ns/cm

Input impedance = 1 megohm, 22pF

2. Rise Time = 10ns max.

Source impedance = 50 ohms

3. Resistors are non-inductive


87/127

TYPE NUMBER MARKING CODE

1N4148 1N4148PH or 4148PH

1N4448 1N4448

High-speed diodes 1N4148; 1N4448

FEATURES

Hermetically sealed leaded glass SOD27 (DO-35)package

High switching speed: max. 4 ns

General application

Cont inuous reverse voltage: max. 100 V

Repet i t ive peak reverse voltage: max. 100 V

Repet i t ive peak forward current: max. 450 mA.

APPLICATIONS

High-speed switching.

DESCRIPTION

The 1N4148 and 1N4448 are high-speed switching diodes

fabricated in planar technology, and encapsulated in

hermetically sealed leaded glass SOD27 (DO-35)

packages.

k a

The diodes are type branded.

Fig.1 Simplified outline (SOD27; DO-35) and

symbol.

MARKING

MAM246

ORDERING INFORMATION

TYPE NUMBER PACKAGENAME DESCRIPTION VERSION

1N4148

hermetically sealed glass package; axial leaded; 2 leads SOD27

1N4448


88/127


LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).


VRRM repetitive peak reverse voltage 100 V

VR continuous reverse voltage 100 V

IF continuous forward current see Fig.2; note 1 200 mA

IFRM repetitive peak forward current 450 mA

IFSM non-repetitive peak forward current square wave; Tj = 25 C prior tosurge; see Fig.4

t = 1 s

t = 1 ms

t = 1 s

4

1

0.5

A

A

APtot total power dissipation Tamb = 25 C; note 1 500 mW

Tstg storage temperature 65 +200 CTj junction temperature 200 C

Note

1. Device mounted on an FR4 printed-circuit board; lead length 10 mm.

ELECTRICAL CHARACTERISTICS

Tj = 25 C unless otherwise specified.


VF forward voltage

1N4148

1N4448

see Fig.3

IF = 10 mA

IF = 5 mA

IF = 100 mA

0.62

1

0.72

1

V

V

V

IR reverse current VR = 20 V; see Fig.5 25 nA

VR = 20 V; Tj = 150 C; see Fig.5 50 AIR reverse current; 1N4448 VR = 20 V; Tj = 100 C; see Fig.5 3 ACd diode capacitance f = 1 MHz; VR = 0 V; see Fig.6 4 pF

Trr reverse recovery time when switched from IF = 10 mA toIR = 60 mA; RL = 100 ;

measured at IR = 1 mA; see Fig.7

4 ns

Vfr forward recovery voltage when switched from IF = 50 mA;tr = 20 ns; see Fig.8

2.5 V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-tp) thermal resistance from junction to tie-point lead length 10 mm 240 K/W

Rth(j-a) thermal resistance from junction to ambient lead length 10 mm; note 1 350 K/W

Note

1. Device mounted on a printed-circuit board without metallization pad.


89/127

(1) (2) (3)


GRAPHICAL DATA

300mbg451

600MBG464

IF

(mA)

IF(mA)

200 400

100 200

00 100 200

Tamb (C)

00 1 VF (V)

2

Device mounted on an FR4 printed-circuit board; lead length 10 mm.

Fig.2 Maximum permissible continuous forward

current as a function of ambient

temperature.

(1) Tj = 175 C; typical values.(2) Tj = 25 C; typical values.(3) Tj = 25 C; maximum values.

Fig.3 Forward current as a function of forwardvoltage.

102MBG704

IFSM(A)

10

1

101

1 10 102 103 tp (s)104

Based on square wave currents.

Tj = 25 C prior to surge.

Fig.4 Maximum permissible non-repetitive peak forward current as a function of pulse duration.


90/127


103

IR

mgd2901.2

Cd

MGD004

(A)

102

(pF)

1.0

(1)

10(2)

0.8

1

101

0.6

1020 100

Tj (C)200

0.40 10

VR (V)20

(1) VR = 75 V; typical values.

(2) VR = 20 V; typical values. f = 1 MHz; Tj = 25 C.

Fig.5 Reverse current as a function of junction

temperature.

Fig.6 Diode capacitance as a function of reverse

voltage; typical values.


91/127


D.U.T.

RS

= 50 IFSAMPLING

OSCILLOSCOPE

t r t p

10%

t

I F t rrt

V = VR IF x RSR

i= 50

VRMGA881

90%

input signal output signal

(1)

(1) IR = 1 mA.

Fig.7 Reverse recovery voltage test circuit and waveforms.

I

RS

= 50

1 k

D.U.T.

450

OSCILLOSCOPE

Ri= 50

I90%

V

Vfr

MGA882

10%

t r

tt p

inputsignal

t

outputsignal

Fig.8 Forward recovery voltage test circuit and waveforms.


92/127

UNIT bmax.

D

max.G1

max.L

min.

mm 0.56 1.85 4.25 25.4


PACKAGE OUTLINE

Hermetically sealed glass package; axial leaded; 2 leads SOD27

(1)

b

D L G1 L

DIMENSIONS (mm are the original dimensions)

0 1 2 mm

scale

Note

1. The marking band indicates the cathode.

OUTLINE

VERSIONREFERENCES EUROPEAN

PROJECTION ISSUE DATEIEC JEDEC JEITA

SOD27 A24 DO-35 SC-40 97-06-0905-12-22


93/127

SYMBOL PARAMETER MAX. UNIT

VDSIDPtotTjRDS(ON)

Drain-source voltageDrain current (DC)Total power dissipationJunction temperatureDrain-source on-state

resistance VGS = 10 V

5549

11017522

VAWCm

PIN DESCRIPTION

1

2

3

tab

gate

drain

source

drain

N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement modestandard level field-effect powertransistor in a plastic envelope usingtrench technology. The devicefeatures very low on-state resistanceand has integral zener diodes givingESD protection up to 2kV. It is

intended for use in switched modepower supplies and general purposeswitching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

dtab

g

1 2 3 s

LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)


VDSVDGRVGSIDID

IDM PtotTstg, Tj

Drain-source voltageDrain-gate voltageGate-source voltageDrain current (DC)Drain current (DC)

Drain current (pulse peak value)Total power dissipationStorage & operating temperature

-RGS = 20 k-Tmb = 25 CTmb = 100 C

Tmb = 25 CTmb = 25 C-

-----

--- 55

5555204935

160110175

VVVAA

AWC

ESD LIMITING VALUE


VC Electrostatic discharge capacitorvoltage, all pins

Human body model(100 pF, 1.5 k )

- 2 kV

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Rth j-mb

R

Thermal resistance junction tomounting baseThermal resistance junction to

-

in free air

-

60

1.4 K/W

K/W


94/127


STATIC CHARACTERISTICSTj= 25C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V(BR)DSS

VGS(TO)

IDSS IGSS

V(BR)GSSRDS(ON)

Drain-source breakdownvoltageGate threshold voltage

Zero gate voltage drain current

Gate source leakage current

Gate source breakdown voltageDrain-source on-stateresistance

VGS = 0 V; ID = 0.25 mA;Tj = -55C

VDS = VGS; ID = 1 mATj = 175CTj = -55C

VDS = 55 V; VGS = 0 V;Tj = 175C

VGS = 10 V; VDS = 0 VTj = 175C

IG = 1 mA;VGS = 10 V; ID = 25 A

Tj = 175C

55502.01.0-----

16--

--

3.0--

0.05-

0.04--

15-

--

4.0-

4.410500120-

2242

VVVV

AAAAV

mm

DYNAMIC CHARACTERISTICSTmb = 25C unless otherwise specified


gfs Forward transconductance VDS = 25 V; ID = 25 A 6 - - S

Ciss

CossCrss

Input capacitance

Output capacitanceFeedback capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz -

--

1350

330155

1800

400215

pF

pFpF

QgQgsQgd

Total gate chargeGate-cource chargeGate-drain (miller) charge

VDD = 44 V; ID = 50 A; VGS = 10 V ---

---

621526

nCnCnC

td ontrtd offtf

Turn-on delay timeTurn-on rise timeTurn-off delay timeTurn-off fall time

VDD = 30 V; ID = 25 A;VGS = 10 V; RG = 10Resistive load

----

18504030

26755040

nsnsnsns

Ld

Ld

Ls

Internal drain inductance

Internal drain inductance

Internal source inductance

Measured from contact screw ontab to centre of dieMeasured from drain lead 6 mm

from package to centre of dieMeasured from source lead 6 mmfrom package to source bond pad

-

-

-

3.5

4.5

7.5

-

-

-

nH

nH

nH

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25C unless otherwise specified


IDR

IDRMVSD

Continuous reverse draincurrentPulsed reverse drain currentDiode forward voltage IF = 25 A; VGS = 0 V

IF = 40 A; VGS = 0 V

-

---

-

-0.951.0

49

1601.2-

A

AV

trrQrr

Reverse recovery timeReverse recovery charge

IF = 40 A; -dIF/dt = 100 A/ s;VGS = -10 V; VR = 30 V

--

470.15

--

nsC


95/127


AVALANCHE LIMITING VALUE


WDSS Drain-source non-repetitiveunclamped inductive turn-offenergy

ID = 45 A; VDD 25 V;VGS = 10 V; RGS = 50 ; Tmb = 25 C

- - 110 mJ

120

110100

90

80

70

60

50

40

30

20

10

0

PD% Normalised Power Derating

0 20 40 60 80 100 120 140 160 180

Tmb / C

1000

ID/A

100

10

1

RDS(ON) =VDS/ID

DC

1 10 VDS/V

tp =

1 us

10us

100 us

1 ms

10ms

100ms

100

Fig.1. Normalised power dissipation.

PD% = 100 PD/PD 25 C = f(Tmb)Fig.3. Safe operating area. Tmb = 25 C

ID & IDM = f(VDS); IDM single pulse; parameter tp

120

110

100

90

80

70

60

50

40

30

2010

0

ID% Normalised Current Derating10

1

0.1

0.01

Zth/(K/W)

0.5

0.2

0.1

0.05

0.02

0

PD tp

T

D =tpT

t

0 20 40 60 80 100 120 140 160 180

Tmb / C

Fig.2. Normalised continuous drain current.ID% = 100 ID/ID 25 C= f(Tmb); conditions: VGS 10 V

0.0011E-06 0.0001 0.01 1 100

t/s

Fig.4. Transient thermal impedance.Zth j-mb = f(t); parameter D = tp/T


96/127

BUK959-60

BUK759-60

16

10

9

8.5VGS/V =

VGS/V=

6

6.57

89

10

Tj/C = 175 25

max.

typ.


100

ID/A

80

60

40

20

00 2 4

VDS/V6 8 10

8.0

7.5

7.0

6.5

6.0

5.5

5.04.54.0

30

gfs/S

25

20

15

10

5

00 20 40 60 80 100

ID/A

Fig.5. Typical output characteristics, Tj = 25 C.ID = f(VDS); parameter VGS

Fig.8. Typical transconductance, Tj = 25 C.gfs = f(ID); conditions: VDS = 25 V

RDS(ON)/mOhm 40 2.5

aRds(on) normlised to 25degC

35

2

30

25 1.5

20

1

15

100 10 20 30 40 50 60 70 80 90

ID/A

0.5

-100 -50 0 50 100 150 200Tmb / degC

Fig.6. Typical on-state resistance, Tj = 25 C.RDS(ON) = f(ID); parameter VGS

Fig.9. Normalised drain-source on-state resistance.a = RDS(ON)/RDS(ON)25 C= f(Tj); ID = 25 A; VGS = 10 V

100

ID/A

80

VGS(TO) / V

5

4

60 3

40 2

20 1

00 2 4 6 8 10 12

VGS/V

Fig.7. Typical transfer characteristics.ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

0-100 -50 0 50 100 150 200

Tj / C

Fig.10. Gate threshold voltage.VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS


97/127

Tj/C = 175 25

VDS = 14V

VDS = 4V

Thousand

s

pF

+


1E-01Sub-Threshold Conduction 100

IF/A

80

1E-02

1E-032% typ 98%

60

40

1E-04

20

1E-05

1E-060 1 2 3 4 5

Fig.11. Sub-threshold drain current.

00 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS/V

Fig.14. Typical reverse diode current.ID = f(VGS); conditions: Tj = 25 C; VDS = VGS IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

2.5

2

1.5

1

.5

00.01 0.1 1 VDS/V

Ciss

Coss

Crss

10 100

120

110

100

90

80

7060

50

40

30

20

10

0

WDSS%

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.12. Typical capacitances, Ciss, Coss, Crss.C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Fig.15. Normalised avalanche energy rating.WDSS% = f(Tmb); conditions: ID = 49 A

12

VGS/V

10

8

6

4

VGS

0

L

VDS

T.U.T.

VDD

--ID/100

2 RGSR 01

shunt

00 10 20

QG/nC30 40 50

Fig.13. Typical turn-on gate-charge characteristics. Fig.16. Avalanche energy test circuit.2 BV BV V

VGS = f(QG); conditions: ID = 50 A; parameter VDSWDSS 0.5 LID DSS DSS DD


98/127


+VDD

RD

VGS

0

VDS

-

RGT.U.T.

Fig.17. Switching test circuit.


99/127


MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

10,3

max

3,71,3

4,5max

2,8 5,9min

15,8max

3,0 max

not tinned

1,3

max 1 2 3

3,0

13,5min

(2x)

2,54 2,54

0,9 max (3x)0,6

2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.2. Refer to mounting instructions for SOT78 (TO220) envelopes.3. Epoxy meets UL94 V0 at 1/8".


100/127

LM78XXSeries

VoltageRegulators

May 2000

LM78XX

Series Voltage Regulators

General DescriptionThe LM78XX series of three terminal regulators is available

with several fixed output voltages making them useful in a

wide range of applications. One of these is local on card

regulation, eliminating the distribution problems associated

with single point regulation. The voltages available allow

these regulators to be used in logic systems, instrumenta-

tion, HiFi, and other solid state electronic equipment. Al-

though designed primarily as fixed voltage regulators these

devices can be used with external components to obtain ad-

justable voltages and currents.

The LM78XX series is available in an aluminum TO-3 pack-

age which will allow over 1.0A load current if adequate heat

sinking is provided. Current limiting is included to limit the

peak output current to a safe value. Safe area protection forthe output transistor is provided to limit internal power dissi-

pation. If internal power dissipation becomes too high for the

heat sinking provided, the thermal shutdown circuit takes

over preventing the IC from overheating.

Considerable effort was expanded to make the LM78XX se-

ries of regulators easy to use and minimize the number of

external components. It is not necessary to bypass the out-

put, although this does improve transient response. Input by-passing is needed only if the regulator is located far from the

filter capacitor of the power supply.

For output voltage other than 5V, 12V and 15V the LM117

series provides an output voltage range from 1.2V to 57V.

Featuresn Output current in excess of 1A

n Internal thermal overload protection

n No external components required

n Output transistor safe area protection

n Internal short circuit current limit

n Available in the aluminum TO-3 package

Voltage Range

LM7805C 5V

LM7812C 12V

LM7815C 15V

Connection Diagrams

Metal Can Package

TO-3 (K) Aluminum

Plastic Package

TO-220 (T)

DS007746-2Top View

DS007746-3

Bottom View

Order Number LM7805CK,

LM7812CK or LM7815CK

See NS Package Number KC02A

Order Number LM7805CT,

LM7812CT or LM7815CT

See NS Package Number T03B

2000 National Semiconductor Corporation DS007746 www.national.com
http://www.national.com/http://www.national.com/


101/127

LM78XX

Schematic

DS007746-1


102/127

LM78XX

Absolute Maximum Ratings (Note 3) Maximum Junction TemperatureIf Military/Aerospace specified devices are required, (K Package) 150C

please contact the National Semiconductor Sales Office/ (T Package) 150C

Distributors for availability and specifications. Storage Temperature Range 65C to +150C

Input Voltage Lead Temperature (Soldering, 10 sec.)

(VO = 5V, 12V and 15V) 35VTO-3 Package K 300C

Internal Power Dissipation (Note 1) Internally Limited TO-220 Package T 230C

Operating Temperature Range (TA) 0C to +70C

Electrical Characteristics LM78XXC (Note 2)0C TJ 125C unless otherwise noted.

Output Voltage 5V 12V 15VUnitsInput Voltage (unless otherwise noted) 10V 19V 23V

Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ MaxVO Output Voltage Tj = 25C, 5 mA IO 1A 4.8 5 5.2 11.5 12 12.5 14.4 15 15.6 V

PD 15W, 5 mA IO 1A

VMIN VIN VMAX

4.75 5.25

(7.5 VIN 20)11.4 12.6 1

(14.5 VIN

27)

4.25 15.75

(17.5 VIN

30)

V

V

VO Line Regulation IO = 500mA

Tj = 25C

VIN

3 50

(7 VIN 25)

4 120

14.5 VIN 30)

4 150

(17.5 VIN

30)

mV

V

0C Tj +125C

VIN

50

(8 VIN 20)120

(15 VIN 27)150

(18.5 VIN

30)

mV

V

IO 1A Tj = 25CVIN

50

(7.5 VIN 20)120

(14.6 VIN

27)

150

(17.7 VIN

30)

mV

V

0C Tj +125C

VIN

25

(8 VIN 12)60

(16 VIN 22)75

(20 VIN 26)mV

VVO Load Regulation Tj = 25C 5 mA IO 1.5A

250 mA IO750 mA

10 50

25

12 120

60

12 150

75

mV

mV

5 mA IO 1A, 0C Tj

+125C50 120 150 mV

IQ Quiescent Current IO 1A Tj = 25C0C Tj +125C

8

8.58

8.58

8.5mA

mAIQ Quiescent Current

Change5 mA IO 1A 0.5 0.5 0.5 mATj = 25C, IO 1A

VMIN VIN VMAX

1.0

(7.5 VIN 20)1.0

(14.8 VIN 27)1.0

(17.9 VIN

30)

mA

V

IO 500 mA, 0C Tj +125C

VMIN VIN VMAX

1.0

(7 VIN 25)1.0

(14.5 VIN 30)1.0

(17.5 VIN

30)

mA

V

VN Output Noise

VoltageTA =25C, 10 Hz f 100 kHz 40 75 90 V

Ripple Rejection

f = 120 Hz

IO 1A, Tj = 25C

or

IO 500 mA

0C Tj +125C

62 80

62

(8 VIN 18)

55 72

55

(15 VIN 25)

54 70

54

(18.5 VIN

28.5)

dB

dB

VVMIN VIN VMAX

RO Dropout Voltage

Output ResistanceTj = 25C, IOUT = 1A

f = 1 kHz2.0

82.0

182.0

19V

m


103/127

LM78XX

Electrical Characteristics LM78XXC (Note 2) (Continued)

0C TJ 125C unless otherwise noted.

Output Voltage 5V 12V 15VUnInput Voltage (unless otherwise noted) 10V 19V 23V

Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ MaxShort-Circuit

Current

Peak OutputCurrent

Average TC of

VOUT

Tj = 25C

Tj = 25C

0C Tj +125C, IO = 5 mA

2.1

2.4

0.6

1.5

2.4

1.5

1.2

2.4

1.8

mV

VIN Input Voltage

Required to

Maintain

Line Regulation

Tj = 25C, IO 1A 7.5 14.6 17.7

Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4C/Wjunction to case and 35C/Wcase to ambient. Thermal resistance of the TO-220 packa

(T) is typically 4C/Wjunction to case and 50C/W case to ambient.

Note 2: All characteristics are measured with capacitor across the input of 0.22 F, and a capacitor across the output of 0.1F. All characteristics except noise volt

and ripple rejection ratio are measured using pulse techniques (tw 10 ms, duty cycle 5%). Output voltage changes due to changes in internal temperature m

be taken into account separately.

Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and the test conditions, see E

trical Characteristics.


104/127

LM78XX

Typical Performance Characteristics

Maximum Average Power Dissipation

DS007746-5

Maximum Average Power Dissipation

DS007746-6

Peak Output Current

DS007746-7

Output Voltage (Normalized to 1V at TJ

= 25C)

DS007746-8

Ripple Rejection

DS007746-9

Ripple Rejection

DS007746-10


105/127

LM78XX

Typical Performance Characteristics (Continued)

Output Impedance

DS007746-11

Dropout Voltage

DS007746-12

Dropout Characteristics

DS007746-13

Quiescent Current

DS007746-14

Quiescent Current

DS007746-15


106/127

LM78XX

Physical Dimensions inches (millimeters) unless otherwise noted

Aluminum Metal Can Package (KC)

Order Number LM7805CK, LM7812CK or LM7815CK

NS Package Number KC02A


107/127

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

LM78XXSeriesVoltageRegulators

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

TO-220 Package (T)

Order Number LM7805CT, LM7812CT or LM7815CT

NS Package Number T03B

LIFE SUPPORT POLICY

NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National Semiconductor

Corporation

Ameri cas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: [email protected]

www.national.com


Europe

Fax: +49 (0) 180-530 85 86

Email:[email protected]

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Franais Tel: +33 (0) 1 41 91 8790


Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

Email: [email protected]


Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507
mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]


108/127

TL494PULSE-WIDTH-

MODULATIONCONTROLCIRCUITS

testingof all parameters.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

1 16

2 15

3 14

4 13

5 12

6 11

7 10

8 9

Complete PWM Power-Control Circuitry

Uncommitted Outputs for 200-mA Sink or

D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

Source Current

Output Control Selects Single-Ended or

Push-Pull OperationInternal Circuitry Prohibits Double Pulse atEither Output

Variable Dead Time Provides Control OverTotal Range

Internal Regulator Provides a Stable 5-VReference Supply With 5% Tolerance

Circuit Architecture Allows Easy

Synchronization

1IN+

1IN

FEEDBACKDTC

CT

RT

GND

C1

2IN+

2IN

REFOUTPUT CTRL

VCCC2

E2

E1

description

The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) controlcircuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor thepower-supply control circuitry to a specific application.

The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)

comparator, a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.

The error amplifiers exhibit a common-mode voltage range from0.3 V to VCC2 V. The dead-time control

comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed

by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common

circuits in synchronous multiple-rail power supplies.

The uncommitted output transistors provide either common-emitter or emitter-follower output capability. TheTL494 provides for push-pull or single-ended output operation, which can be selected through the

output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice

during push-pull operation.

The TL494C is characterized for operation from 0C to 70C. The TL494I is characterized for operation from40C to 85C.

AVAILABLE OPTIONS

TA

PACKAGED DEVICES

SMALL

OUTLINE

(D)

PLASTIC

DIP

(N)

SMALL

OUTLINE

(NS)

SHRINK

SMALL

OUTLINE

(DB)

THIN SHRINK

SMALL

OUTLINE

(PW)0C to 70C TL494CD TL494CN TL494CNS TL494CDB TL494CPW

40C to 85C TL494ID TL494IN

The D, DB, NS, and PW packages are available taped and reeled. Add the suffix R to device type (e.g.,TL494CDR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Products conformto specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include

Copyright2002, Texas Instruments Incorporated


109/127

TL494PULSE-WIDTH-


testingof all parameters.


FUNCTION TABLE

INPUT TO

OUTPUT CTRL OUTPUT FUNCTION

VI = GND Single-ended or parallel outputVI = Vref Normal push-pull operation

functional block diagram

RT 6

CT 5

DTC4

0.1 V

Oscillator

Dead-Time Control

Comparator

OUTPUT CTRL

(see Function Table)

13

1D

C1

Q18

C1

9E1

1IN+ 1

1IN2

2IN+16

2IN 15

FEEDBACK3

Error Amplifier 1

+

Error Amplifier 2

+

PWM

Comparator

0.7 mA

Pulse-Steering

Flip-Flop

Reference

Regulator

Q2 11

10

12

14

7

C2

E2

VCC

REF

GND


110/127

TL494PULSE-WIDTH-



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V

Amplifier input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 VCollector output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V

Collector output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA

Package thermal impedance, JA (see Note 2 and 3): D packageDB packageN package

NS package

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

73C/W82C/W67C/W

64C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C

Stresses beyond those listed under absolutemaximum ratingsmay cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommendedoperating conditionsis not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the network ground terminal.

2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable

ambient temperature is PD = (TJ(max)TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN MAX UNITVCC Supply voltage 7 40 VVI Amplifier input voltage 0.3 VCC2 VVO Collector output voltage 40 V

Collector output current (each transistor) 200 mACurrent into feedback terminal 0.3 mA

fosc Oscillator frequency 1 300 kHzCT Timing capacitor 0.47 10000 nFRT Timing resistor 1.8 500 k

TA Operating free-air temperatureTL494C 0 70

CTL494I 40 85


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PARAMETER TEST CONDITIONSTL494, TL494I

UNITMIN TYP MAX

Frequency 10 kHzStandard deviation of frequency All values of VCC, CT, RT, and TA constant 100 Hz/kHz

Frequency change with voltage VCC = 7 V to 40 V, TA = 25C 1 Hz/kHzFrequency change with temperature# TA = MIN to MAX 10 Hz/kHz

electrical characteristics over recommended operating free-air temperature range, VCC = 15 V,f = 10 kHz (unless otherwise noted)

reference section

PARAMETER TEST CONDITIONSTL494C, TL494I

UNITMIN TYP MAX

Output voltage (REF) IO = 1 mA 4.75 5 5.25 VInput regulation VCC = 7 V to 40 V 2 25 mVOutput regulation IO = 1 mA to 10 mA 1 15 mVOutput voltage change with temperature TA = MIN to MAX 2 10 mV/V

Short-circuit output current REF = 0 V 25 mAFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.All typical values, except for parameter changes with temperature, are at TA = 25C. Duration of the short circuit should not exceed one second.

oscillator section, CT = 0.01 F, RT = 12 k(see Figure 1)

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.All typical values, except for parameter changes with temperature, are at TA = 25C. Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:

N

n 1

(xn X)2

N 1

# Temperature coefficient of timing capacitor and timing resistor are not taken into account.

error-amplifier section (see Figure 2)

PARAMETER TEST CONDITIONSTL494, TL494I

UNITMIN TYP MAX

Input offset voltage VO (FEEDBACK) = 2.5 V 2 10 mVInput offset current VO (FEEDBACK) = 2.5 V 25 250 nAInput bias current VO (FEEDBACK) = 2.5 V 0.2 1 A

Common-mode input voltage range VCC = 7 V to 40 V0.3 to

VCC2V

Open-loop voltage amplification VO = 3 V, RL = 2 k, VO = 0.5 V to 3.5 V 70 95 dBUnity-gain bandwidth VO = 0.5 V to 3.5 V, RL = 2 k 800 kHzCommon-mode rejection ratio VO = 40 V, TA = 25C 65 80 dBOutput sink current (FEEDBACK) VID =15 mV to5 V, V (FEEDBACK) = 0.7 V 0.3 0.7 mAOutput source current (FEEDBACK) VID = 15 mV to 5 V, V (FEEDBACK) = 3.5 V 2 mA

All typical values, except for parameter changes with temperature, are at TA = 25C.


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electrical characteristics over recommended operating free-air temperature range, VCC = 15 V,f = 10 kHz (unless otherwise noted)

output section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Collector off-state current VCE = 40 V, VCC = 40 V 2 100 AEmitter off-state current VCC = VC = 40 V, VE = 0 100 A

Collector-emitter saturation voltageCommon emitter VE = 0, IC = 200 mA 1.1 1.3

VEmitter follower VO(C1 or C2) = 15 V, IE =200 mA 1.5 2.5

Output control input current VI = Vref 3.5 mAAll typical values except for temperature coefficient are at TA = 25C.

dead-time control section (see Figure 1)


Input bias current (DEAD-TIME CTRL) VI = 0 to 5.25 V 2 10 AMaximum duty cycle, each output VI (DEAD-TIME CTRL) = 0, CT = 0.01 F, RT = 12 k 45%

Input threshold voltage (DEAD-TIME CTRL)Zero duty cycle 3 3.3

VMaximum duty cycle 0

All typical values except for temperature coefficient are at TA = 25C.

PWM comparator section (see Figure 1)


Input threshold voltage (FEEDBACK) Zero duty cycle 4 4.5 VInput sink current (FEEDBACK) V (FEEDBACK) = 0.7 V 0.3 0.7 mA

All typical values except for temperature coefficient are at TA = 25C.

total device


Standby supply current RT = Vref, All other inputs and outputs openVCC = 15 V 6 10

mAVCC = 40 V 9 15

Average supply current VI (DEAD-TIME CTRL) = 2 V, See Figure 1 7.5 mAAll typical values except for temperature coefficient are at TA = 25C.

switching characteristics, TA = 25C


Rise timeCommon-emitter configuration, See Figure 3

100 200 nsFall time 25 100 nsRise time

Emitter-follower configuration, See Figure 4100 200 ns

Fall time 40 100 nsAll typical values except for temperature coefficient are at TA = 25C.


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TL494PULSE-WIDTH-


PARAMETER MEASUREMENT INFORMATION

VCC = 15 V

12

V

CC

4

150

2 W

8

150

2 W

Test DTC C1 Output 1

Inputs 3

12 k6

5

FEEDBACK

RT

CT

E19

11C2

E210

Output 2

0.01 F

1

2

16

15

1IN+

1IN

2IN+

2IN

Error

Amplifiers

50 k

13 OUTPUTCTRL

GND

7

REF 14

TEST CIRCUIT

Voltage

at C1

Voltage

at C2

Voltage

at CT

DTC

Threshold Voltage

VCC

0 V

VCC

0 V

0 V

FEEDBACK

Threshold Voltage

0.7 V

Duty Cycle 0%MAX 0%

VOLTAGE WAVEFORMS

Figure 1. Operational Test Circuit and Waveforms


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TL494PULSE-WIDTH-


PARAMETER MEASUREMENT INFORMATION

Amplifier Under Test+

VI FEEDBACK

+

Vref Other Amplifier

Figure 2. Amplifier Characteristics

15 V

Each Output

Circuit

68

2 W

Output90%

tf tr

90%

CL = 15 pF

(See Note A)10% 10%

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

NOTE A: CL includes probe and jig capacitance.

Figure 3. Common-Emitter Configuration

15 V

Each Output

Circuit

CL = 15 pF

(See Note A)

68

2 W

Output

10%

90%

tr

90%

10%

tf

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

NOTE A: CL includes probe and jig capacitance.

Figure 4. Emitter-Follower Configuration


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TL494PULSE-WIDTH-


f

OscillatorFrequencyandFrequencyVariation

Hz

A

Am

plifierVoltageAmplification

dB

TYPICAL CHARACTERISTICS

100 k

40 k

OSCILLATOR FREQUENCY AND

FREQUENCY VARIATION

vs

TIMING RESISTANCE

VCC = 15 V

TA = 25C

2%

10 k

4 k

1%

0%0.01 F

0.001 F

1 k 0.1 F

400

100

40

CT = 1 F

Df = 1%

10

1 k 4 k 10 k 40 k 100 k 400 k 1 M

RT Timing Resistance

Frequency variation (f) is the change in oscillator frequency that occurs over the full temperature range.

Figure 5

100

AMPLIFIER VOLTAGE AMPLIFICATION

vs

FREQUENCY

VCC = 15 V90 VO = 3 V

TA = 25C80

70

60

50

40

30

20

10

01 10 100 1 k 10 k 100 k 1 M

f Frequency Hz

Figure 6


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POWER ELECTRONICS LAB MANUAL 2011-2012

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