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MSM6000™Device Specification

93-V3050-1 Rev. E

February 9, 2005

Submit technical questions at:https://support.cdmatech.com

QUALCOMM Proprietary

Restricted Distribution. This document contains critical information about QUALCOMM products and may not be distributed to anyone that is not an employee of QUALCOMM, its affiliates or subsidiaries without the approval of Configuration Management.

All data and information contained in or disclosed by this document is confidential and proprietary information of QUALCOMM Incorporated and all rights therein are expressly reserved. By accepting this material, the recipient agrees that this material and the information contained therein is to be held in confidence and in trust and will not be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the express written permission of QUALCOMM Incorporated.

QUALCOMM is a registered trademark and registered service mark of QUALCOMM Incorporated. Other product and brandnames may be trademarks or registered trademarks of their respective owners. CDMA2000® is a registered certification markof the Telecommunications Industry Association. Used under license. ARM® is a registered trademark of ARM Limited.

Export of this technology may be controlled by the United States Government. Diversion contrary to U.S. law prohibited.

QUALCOMM Incorporated5775 Morehouse Drive

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Copyright © 2002-2005 QUALCOMM Incorporated. All rights reserved.

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MSM6000™ Device Specification

2 QUALCOMM Proprietary 93-V3050-1 Rev. E

Contents

Preface

1 Overview1.1 Application description ..................................................................................................... 191.2 radioOne technology ......................................................................................................... 211.3 Reductions in overall handset cost .................................................................................... 211.4 MSM6000 solution general features ................................................................................. 22

1.4.1 CDMA2000 1x Release 0 features supported by the MSM6000 solution........... 221.4.2 CDMA2000 1x Release 0 features not supported by the MSM6000 solution..... 231.4.3 MSM6000 audio processing features ................................................................... 241.4.4 MSM6000 microprocessor subsystem ................................................................. 241.4.5 MSM6000 supported interface features ............................................................... 24

2 Pin Descriptions2.1 I/O description parameters ................................................................................................ 252.2 Pin description examples................................................................................................... 262.3 Pin names and pinouts....................................................................................................... 262.4 208-ball FBGA pinout for MSM6000 device (top view).................................................. 36

3 Electrical Specifications3.1 DC electrical specifications............................................................................................... 37

3.1.1 Absolute maximum ratings .................................................................................. 373.1.2 Recommended operating conditions .................................................................... 383.1.3 DC characteristics ................................................................................................ 383.1.4 General-purpose ADC specifications................................................................... 403.1.5 Codec specifications............................................................................................. 413.1.6 Power consumption .............................................................................................. 473.1.7 Power sequencing................................................................................................. 48

3.2 Timing characteristics ....................................................................................................... 503.2.1 TCXO timing........................................................................................................ 50

93-V3050-1 Rev. E QUALCOMM Proprietary 3

Contents MSM6000™ Device Specification

3.2.2 MCLK timing ....................................................................................................... 503.2.3 PCM interface....................................................................................................... 513.2.4 Auxiliary PCM interface ...................................................................................... 533.2.5 Native mode microprocessor timing .................................................................... 553.2.6 Bus sizer timing.................................................................................................... 583.2.7 LCD timing........................................................................................................... 613.2.8 JTAG timing ......................................................................................................... 63

4 Interface Descriptions4.1 Overview ........................................................................................................................... 65

4.1.1 Organization of this chapter ................................................................................. 674.2 The MSM6000 Mobile Station Modem ASIC overview .................................................. 68

4.2.1 CDMA subsystem ................................................................................................ 684.2.2 Digital FM subsystem .......................................................................................... 684.2.3 RF interface .......................................................................................................... 684.2.4 Audio front end .................................................................................................... 694.2.5 ARM microprocessor subsystem.......................................................................... 694.2.6 UART ................................................................................................................... 694.2.7 Serial bus interface ............................................................................................... 694.2.8 User interface ....................................................................................................... 704.2.9 General-purpose interface bus.............................................................................. 704.2.10 Mode select and JTAG interfaces......................................................................... 70

4.3 RF interface ....................................................................................................................... 714.3.1 Transmit signal paths............................................................................................ 734.3.2 Receive signal paths ............................................................................................. 744.3.3 Others ................................................................................................................... 744.3.4 Digital interface.................................................................................................... 75

4.4 Audio front end.................................................................................................................. 764.4.1 Functionality......................................................................................................... 764.4.2 Codec.................................................................................................................... 794.4.3 Vocoder................................................................................................................. 87

4.5 ARM microprocessor and peripherals............................................................................... 954.5.1 Memory and peripheral interface controller......................................................... 954.5.2 ARM clock and power management .................................................................. 1024.5.3 Reset and pause .................................................................................................. 1034.5.4 Watchdog timer .................................................................................................. 1044.5.5 Interrupt controller ............................................................................................. 106

4.6 Mode select and emulation considerations...................................................................... 1104.6.1 Mode selection inputs......................................................................................... 1104.6.2 NATIVE mode.................................................................................................... 110


MSM6000™ Device Specification Contents

4.6.3 MSM ICE mode ................................................................................................. 1104.6.4 HI-Z mode .......................................................................................................... 1154.6.5 JTAG debug mode.............................................................................................. 116

4.7 General-purpose interface (GPIO_INT).......................................................................... 1184.8 UART, R-UIM................................................................................................................. 121

4.8.1 UART1 ............................................................................................................... 1214.8.2 UART2 ............................................................................................................... 1264.8.3 R-UIM ................................................................................................................ 127

4.9 User interface .................................................................................................................. 1304.9.1 Keypad interface ................................................................................................ 1304.9.2 Ringer ................................................................................................................. 1314.9.3 LCD_CS_N and LCD_E.................................................................................... 1344.9.4 M/N counter ....................................................................................................... 1354.9.5 Auxiliary PCM interface .................................................................................... 136

4.10 GPADC functional description........................................................................................ 1374.10.1 Analog input voltage range ................................................................................ 1384.10.2 GPADC dperation............................................................................................... 1394.10.3 GPADC conversion time .................................................................................... 1404.10.4 GPADC analog interface considerations ............................................................ 141

4.11 Clock regimes.................................................................................................................. 1424.11.1 TCXO................................................................................................................. 1424.11.2 SLEEP crystal circuit for 32.768 kHz................................................................ 1424.11.3 Subsystem clock regimes ................................................................................... 144

4.12 JTAG interface................................................................................................................. 1464.12.1 Test access port................................................................................................... 1474.12.2 TAP controller .................................................................................................... 1484.12.3 Data registers...................................................................................................... 1484.12.4 JTAG instructions............................................................................................... 150

5 Mechanical Dimensions5.1 208-ball FBGA package outline...................................................................................... 1555.2 208-ball FBGA land pattern ............................................................................................ 1555.3 Part marking .................................................................................................................... 156



FiguresFigure 1-1 Typical subscriber unit block diagram .....................................................................................20

Figure 3-1 Power supply current versus time in slotted paging mode .......................................................47

Figure 3-2 Power ramp up recommendation .............................................................................................48

Figure 3-3 Power ramp down recommendation ........................................................................................49

Figure 3-4 TCXO timing parameters .........................................................................................................50

Figure 3-5 PCM_SYNC timing .................................................................................................................51

Figure 3-6 PCM_CODEC to MSM6000 timing ........................................................................................51

Figure 3-7 MSM6000 to PCM_CODEC timing ........................................................................................51

Figure 3-8 AUX_PCM_SYNC timing ......................................................................................................53

Figure 3-9 CODEC to MSM6000 timing via AUX_CODEC (MSM6000 receiving ................................53

Figure 3-10 MSM6000 to CODEC timing via AUX_CODEC (MSM6000 transmitting) ..........................53

Figure 3-11 Native mode write timing ........................................................................................................55

Figure 3-12 Native mode read access, non-instruction fetch .......................................................................56

Figure 3-13 Native mode read access, instruction fetch ..............................................................................56

Figure 3-14 Bus sizer write timing with x16 sram ......................................................................................58

Figure 3-15 Bus sizer read timing non-inst with x16 sram ..........................................................................60

Figure 3-16 LCD timing ..............................................................................................................................61

Figure 3-17 JTAG interface timing .............................................................................................................63

Figure 4-1 MSM6000 functional block diagram .......................................................................................66

Figure 4-2 MSM6000 interfaces ................................................................................................................72

Figure 4-3 Functional block diagram .........................................................................................................76

Figure 4-4 Typical external filter network .................................................................................................80

Figure 4-5 Equivalent circuit for external filter network ...........................................................................80

Figure 4-6 Equivalent circuit for MICAMP2 ............................................................................................81

Figure 4-7 Slope filter ................................................................................................................................82

Figure 4-8 Highpass filter ..........................................................................................................................83

Figure 4-9 Typical handset interface .........................................................................................................85

Figure 4-10 Typical headset application ......................................................................................................85

Figure 4-11 Typical analog car kit application ............................................................................................86

Figure 4-12 Encoder packet transfer timing ................................................................................................89

Figure 4-13 Decoder packet transfer timing ................................................................................................90

Figure 4-14 Command interface flow ..........................................................................................................93

Figure 4-15 Message interface flow ............................................................................................................94

Figure 4-16 Reset generation ....................................................................................................................103

Figure 4-17 Watchdog timer configuration in NATIVE and ICE mode ...................................................104

Figure 4-18 Watchdog timer block diagram ..............................................................................................105

Figure 4-19 Interrupt controller .................................................................................................................107

Figure 4-20 Interrupt bit slice ....................................................................................................................108

Figure 4-21 GPIO_INT bit slice ................................................................................................................109

Figure 4-22 ICE mode emulation interface ...............................................................................................111

Figure 4-23 Lauterbach emulation setup ...................................................................................................114



Figure 4-24 ARM JTAG setup example ................................................................................................... 116

Figure 4-25 GPIO_INT pad structure ....................................................................................................... 120

Figure 4-26 UART block diagram ............................................................................................................ 121

Figure 4-27 Multiplexing arrangement for UART2 and AUX_PCM signals ........................................... 127

Figure 4-28 Multiplexing arrangement for UART2 and AUX_PCM signals ........................................... 128

Figure 4-29 Byte transmission diagram .................................................................................................... 129

Figure 4-30 KEYSENSE[4:0] circuits ...................................................................................................... 130

Figure 4-31 Ringer generation circuit ....................................................................................................... 131

Figure 4-32 External driver circuit example ............................................................................................. 131

Figure 4-33 LCD interface timing ............................................................................................................. 134

Figure 4-34 GP_MN block diagram .......................................................................................................... 135

Figure 4-35 Auxiliary PCM interface ....................................................................................................... 136

Figure 4-36 GPADC configuration in the MSM6000 ............................................................................... 137

Figure 4-37 General GPADC conversion process .................................................................................... 139

Figure 4-38 Equivalent circuits for GPADC input and external voltage sources ..................................... 141

Figure 4-39 SLEEP oscillator circuit with passive crystal ........................................................................ 143

Figure 4-40 MSM6000 JTAG interface .................................................................................................... 146

Figure 4-41 JTAG interface block diagram .............................................................................................. 147

Figure 4-42 Data structure for device identification register .................................................................... 149

Figure 4-43 Typical boundary scan cell .................................................................................................... 150

Figure 4-44 JTAG connections for using the MSM6000 BSDL scan chain WDOG disabled ................. 153

Figure 4-45 Connections for using the MSM6000 ARM JTAG WDOG disabled ................................... 154

Figure 5-1 Marking diagram ................................................................................................................... 156



TablesTable 1 Terms and acronyms ................................................................................................................12

Table 2 Special marks ...........................................................................................................................15

Table 3 Revision history .......................................................................................................................16

Table 2-1 I/O description parameters .......................................................................................................25

Table 2-2 Pin description examples .........................................................................................................26

Table 2-3 Pin names and pinouts ..............................................................................................................26

Table 2-4 208-ball FBGA pinout for MSM6000 device (top view) ........................................................36

Table 3-1 Absolute maximum ratings ......................................................................................................37

Table 3-2 Recommended operating conditions ........................................................................................38

Table 3-3 Thermal dissipation ..................................................................................................................38

Table 3-4 DC characteristics ....................................................................................................................38

Table 3-5 GPADC performance specification ..........................................................................................40

Table 3-6 Microphone interface ...............................................................................................................41

Table 3-7 Speaker interface ......................................................................................................................42

Table 3-8 Transmit path level translation and linearity, MIC AMP2 enabled .........................................43

Table 3-9 Transmit path level translation and linearity, MIC AMP2 bypassed .......................................43

Table 3-10 Transmit path idle channel noise and distortion ......................................................................44

Table 3-11 Receive path level translation and linearity, EAR1 and AUXO ..............................................44

Table 3-12 Receive path level translation and linearity, EAR2 selected ...................................................45

Table 3-13 Receive path idle channel noise and distortion, EAR1 and AUXO selected ...........................45

Table 3-14 Receive path idle channel noise and distortion, EAR2 selected ..............................................46

Table 3-15 Crosstalk attenuation ................................................................................................................46

Table 3-16 MSM6000 power supply current .............................................................................................47

Table 3-17 TCXO timing parameters .........................................................................................................50

Table 3-18 MCLK timing parameters ........................................................................................................50

Table 3-19 PCM_CODEC timing parameters ............................................................................................51

Table 3-20 AUX_CODEC timing parameters ...........................................................................................54

Table 3-21 Native mode write timing ........................................................................................................55

Table 3-22 Native mode read timing ..........................................................................................................57

Table 3-23 Bus sizer write timing requirements ........................................................................................59

Table 3-24 Bus sizer read timing requirements ..........................................................................................60

Table 3-25 LCD_EN timing .......................................................................................................................62

Table 3-26 JTAG interface timing ..............................................................................................................63

Table 4-1 DTMF frequencies and programmed values ............................................................................78

Table 4-2 Encoder/decoder packet buffer ................................................................................................91

Table 4-3 Commands and messages .........................................................................................................92

Table 4-4 ARM memory map ..................................................................................................................95

Table 4-5 ROM_CS1_N walt status .........................................................................................................96

Table 4-6 ROM_CS2_N walt status .........................................................................................................97

Table 4-7 RAM_CS1_N walt states .........................................................................................................98

Table 4-8 RAM_CS2_N walt status .........................................................................................................99



Table 4-9 MSM6000 X16 SRAM interface pins ................................................................................... 100

Table 4-10 X16SRAM on RAM_CS_N .................................................................................................. 101

Table 4-11 X16SRAM on RAM_CS_N, RAM_CS2_N ......................................................................... 101

Table 4-12 MODE[1:0] functions ............................................................................................................ 110

Table 4-13 MSM6000 emulation interface .............................................................................................. 111

Table 4-14 Advanced system bus ............................................................................................................ 113

Table 4-15 MSM6000 ICD (in-circuit) debugger .................................................................................... 117

Table 4-16 Alternate functions ................................................................................................................ 118

Table 4-17 Clock select register bit rates (TCXO/4 based) ..................................................................... 125

Table 4-18 Clock select register bit rates (TCXO based) ........................................................................ 126

Table 4-19 GPIO_INT pins1 .................................................................................................................... 128

Table 4-20 AUX_PCM pins2 .................................................................................................................. 128

Table 4-21 Standard DTMF frequencies and ringer programming values .............................................. 132

Table 4-22 Keypad frequencies ............................................................................................................... 133

Table 4-23 Using GP_MN as a digital output .......................................................................................... 135

Table 4-24 MSM6000 ADC transfer function ......................................................................................... 138

Table 4-25 ADC timing for TCXO/4 = 4.8 MHz (TCXO = 19.2 MHz) ................................................. 140

Table 4-26 Recommended Rs maximum values ...................................................................................... 141

Table 4-27 SLEEP oscillator inverter relative gain settings .................................................................... 142

Table 4-28 Suggested MSM_CLK_CTL4 settings of bits 11:8 ............................................................... 143

Table 4-29 Descriptions of clock origins ................................................................................................. 144

Table 4-30 MSM6000 clock regimes ....................................................................................................... 144

Table 4-31 Boundary scan cell control signals ........................................................................................ 151

Table 5-1 Marking descriptions ............................................................................................................. 156


Preface

About this technical manualThis manual provides hardware interface and programming information for the MSM6000™ Mobile Station Modem™ (MSM™). The manual is divided into the following chapters:

NOTE The software interface description will not be included in the MSM6000 Device Specification. Please refer to the separate document, MSM6000 Software Interface (80-V3050-7) for register descriptions.

Please refer to the MSM6000 Device Revision Guide (CL93-V3050-2) for any performance exceptions.

Chapter 1:Introduction

This chapter introduces users to the MSM6000 MSM basic features and functions.

Chapter 2:Pin Descriptions

This chapter lists each MSM6000 MSM pin and its function within the device. The pinout for the 208-ball FBGA package is listed by functional grouping.

Chapter 3:Electrical Specifications

This chapter specifies the recommended operating conditions, DC voltage characteristics, I/O timing, and power estimations for the MSM6000 device. Timing diagrams are also included.

Chapter 4:Interface Descriptions

This chapter details each subsystem or block within the MSM6000 device and how the subsystem or block interfaces to external peripherals.

Chapter 5:Mechanical Dimensions

This chapter provides marking information for the 208-ball FBGA.



Terms and acronyms

The following table defines terms commonly used throughout this manual.

Table 1 Terms and acronyms

Term Definition

AAGC Audio automatic gain control

ACH Access channel

ADC Analog-to-digital converter

AEC Acoustic echo cancellation

AGC Automatic gain control

AMPS Advanced Mobile Phone System (analog IS-95)

APICH Dedicated auxiliary pilot channel

ASIC Application specific integrated circuit

ATDPICH Auxiliary transmit diversity pilot channel

BCCH Broadcast control channel

BER Bit error rate

BPF Bandpass filter

Bps Bits per second

CACH Common assignment channel

CAGC CDMA AGC

CCCH Common control channel

CDMA Code Division Multiple Access

CELP Code excited linear prediction

CODEC Coder-decoder

CPCCH Common power control channel

CR Command register

CSM Cell site modem

CRC Cyclic redundancy code

DBR Data burst randomization

DCCH Dedicated control channel

DFM Digital frequency modulation

DTMF Dual-tone multiple-frequency



EACH Enhanced access channel

ESEC Ear seal echo cancellation

FBGA Fine-pitch plastic ball grid array

FCH Fundamental channel

FIFO First-in first-out

FIR Finite impulse response

FM Frequency modulation

FOCC Forward control channel

FVC Forward voice channel

GPIO General-purpose input/output

HEC Headset echo cancellation

HPF Highpass filter

ICD In-circuit debugger

ICE In-circuit emulation, or in-circuit emulator

IF Intermediate frequency

IR Instruction register

JTAG Joint Test Action Group (ANSI/ICEEE Std. 1149.1–1990)

kbps Kilobits per second

LCD Liquid crystal display

LNA Low noise amplifier

LPF Lowpass filter

LSByte or LSBit

Defines whether the LSB is the least significant bit or least significant byte. All instances of LSB used in this manual are assumed to be LSByte, unless otherwise specified.

MICE MSM in-circuit emulation (= ICE)

MSByte or MSBit

Defines whether the MSB is the most significant bit or most significant byte. All instances of MSB used in this manual are assumed to be MSByte, unless otherwise specified.

MSM Mobile Station Modem (trademarked by QUALCOMM)

NMI Non-maskable interrupt

NS Noise suppression

PA Power amplifier

Table 1 Terms and acronyms (continued)

Term Definition



PCM Pulse coded modulation

PCS Personal communications service

PCH Paging channel

PDM Pulse density modulation

PICH Pilot channel

PN Pseudo-random noise

QCELP® QUALCOMM Code Excited Linear Prediction

QPCH Quick paging channel

RC Resistance-capacitance

RF Radio frequency

RRM Reduced rate mode

RSSI Receive strength signal indicator

R-UIM Removable user identity module

Rx Receive

SAT Supervisory audio tone

SCCH Supplemental code channel

SCH Supplemental channel

SNR Signal-to-noise ratio

Sps Symbols per second, or samples per second

SER Symbol error rate

SYNCH Sync channel

TAP Test access port

TCXO Temperature-compensated crystal oscillator

TDPICH Transmit diversity pilot channel

Tx Transmit

UART Universal asynchronous receiver transmitter

UHF Ultra high frequency

VCTCXO Voltage controlled temperature-compensated crystal oscillator

WBD Wide band data

ZIF Zero intermediate frequency

Table 1 Terms and acronyms (continued)

Term Definition



Special marks

The following table defines special marks used in this manual.

Table 2 Special marks

Mark Definition

[ ] Brackets ([ ]) sometimes follow a pin, register, or bit name. These brackets enclose a range of numbers. For example, GPIO_INT [7:0] may indicate a range that is 8 bits in length, or DATA[7:0] may refer to all eight DATA pins.

_N A suffix of “_N” indicates an active low signal. For example, RESIN_N.

0x0000 Hexadecimal numbers are identified with an x in the number, for example, 0x0000. All numbers are decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the term “binary” enclosed in parentheses at the end of the number, for example, 0011 (binary).

| A vertical bar in the outside margin of the page indicates a change or revision has occurred since the last release of the document.



Revision history

The revision history of this document is described below.

Table 3 Revision history

Revision Date Description

A January 18, 2002 Initial release

B March 29, 2002 Section:

1.1 Updated echo cancellation and Fig. 1-1

1.4 Updated TTY

2.1 Updated Table 2-1



3.1 Updated Table 3-4, 3-5, 3-6, 3-16, 3-17, 3-18

Added Table 3-19

Updated Fig. 3-2

3.2 Added MCLK Timing

4.1 Updated Fig. 4-1

4.3 Added RF Interface

4.6 Added Lauterbach Emulation

4.9 Added Table 4-19

4.10 Changed all VDD* to VDD_A

Added Table 4-22

4.11 Updated Clock Regimes

Updated Table 4-27

4.12 Updated Fig. 4-42

5 Changed title

Parts marking updated 5-2

C January 15, 2003 Section:



3.1 Updated Tables 3-1, 3-3, 3-5, 3-16; Deleted former Table 3-17

3.2 Updated Tables 3-21, 3-22, 3-23, 3-24

4.4 Updated Figures 4-5, 4-6

4.5 Replaced subsection 4.5.1.3

5.3 Updated Figure 5-1 and Table 5-1 for Part Marking.



D November 2003 Section:

Added Note in Preface

Updated Table 3-5

Updated Table 3-6

Updated Section 4.11.1

Added Table 4-30

Updated Section 5.3

E February 2005 Updated digital power supply current in Table 3-16

Added Section 3.1.7, Power sequencing

Added Section 4.12.4.5, JTAG selection, including Figure 4-44 and Figure 4-45

Updated Section 5.3, Part marking

Table 3 Revision history (continued)

Revision Date Description


1 Overview

1.1 Application descriptionThe MSM6000 solution, part of the QUALCOMM CDMA Technologies (QCT) MSM6xxx Mobile Station Modem family of chipsets and system software, uses radioOne® zero intermediate frequency (ZIF), or direct conversion, architecture to support the CDMA2000 1x standard.

The MSM6000 CDMA2000 1x solution is fully backward compatible with IS-95-A/B, and is optimized to support voice and basic data capabilities.

The MSM6000 chipset, including the radioOne RF components, reduces the total number of radio components, shortens handset development and test times, and enables higher handset production yields.

QCT has developed the MSM6000 chipset and system software to support Release 0 of the CDMA IS-2000 Standard. The MSM6000 solution consists of the MSM6000 baseband processor, direct conversion RFL6000™ and RFR6000™ receive devices, direct conversion RFT6100™ transmit device, PM6000™ or PM6050™ power management device and a compatible power amplifier device. These devices perform all of the signal processing and power management in the subscriber unit, from RF to voice, for compliance with the proposed 3G CDMA release 0 of IS-2000 1x standard.

The MSM6000 device is a mixed-signal baseband chip that enables manufacturers to meet or exceed the specifications of mobile stations for worldwide cdmaOne and 3G CDMA systems, including IS-95-A, IS-95-B, IS-2000 1x Release 0.

Subsystems within the MSM6000 device include a CDMA processor, a DFM processor, QCT’s QDSP2000™ DSP for voice compression, PLL and an ARM® ARM7TDMI® microprocessor. Also integrated in the MSM6000 device are an audio voice codec and analog interfaces for the radioOne RF ASICs. Controllers for an R-UIM, GPIOs, and peripheral interfaces complete the system integration.

The subscriber unit system software is executed by an ARM7TDMI embedded microprocessor and controls most of the functionality of the subscriber unit. The user interface of the subscriber unit typically includes the keypad, LCD display, and ringer. These are under the direct control of the MSM6000 device. As the subscriber changes modes of operation, the MSM6000 device powers down unused circuits in order to dynamically minimize power consumption.


Overview MSM6000™ Device Specification

With the integrated microphone and earpiece amplifiers, the MSM6000 device interfaces directly to the microphone and earpiece and greatly reduces the audio interface into a few passive components. The integrated CODEC converts an analog audio signal, either differential or single-ended, from the microphone into digital signals for the MSM6000 device’s vocoder. The integrated CODEC also converts digital audio data from the vocoder into an analog audio signal, either differential or single-ended, for the earpiece. The internal vocoder supports EVRC, along with implementing the earseal echo cancellation (ESEC). The vocoder also supports digital FM (DFM), DTMF generation and detection, advanced noise suppression, audio AGC, and automatic volume control (AVC). The MSM6000 device has a pulse code modulation (PCM) interface and programmable Tx and Rx 13-Tap compensation filters. It also supports an auxiliary linear, mu-law, or A-law CODEC that is typically found in carkit applications.

Figure 1-1 Typical subscriber unit block diagram

1 2 3

7 8 94 5 6

* 0 #

PowerAmplifier

PeripheralCircuits

R-UIM

PLL

RFInterface

UART 1

UART 2 / R-UIM

ARM7TDMI

IntegratedVoice

CODEC

GeneralPurposeInterface

SBI

MSM6000Mobile Station Modem

Antenna

General-Purpose Interface Bus

External Mode Selection

RINGER

Keypad

19.2 MHz

Microprocessor BusAddress/Data

Digital Test Bus

MODE Select

Interface

CDMAProcessor

ANSI/IEEE 1149.1A-1993JTAG Interface

HK ADC

Voltage Regulator

PM6000PM6050

RxADCs

RFR6000

RFL6000

RFT6100

VCTCXO

RF Controls

Duplexer

TXDACs Vocoder

EVRCQDSP2000

PCConnectivity

Test/DebugSystem

DFMProcessor

089-000

AUX_

SBI


MSM6000™ Device Specification Overview

For the received data path (Rx), the RFL6000 LNA IC provides high linearity and gain with low noise figure. The RFR6000 IC provides downconversion from RF to analog baseband using radioOne ZIF technology. The MSM6000 device digitizes and then demodulates the Rx analog baseband signal.

For the transmit data path (Tx), the MSM6000 device modulates, interpolates, and converts the digital data into an analog baseband before sending it to the RFT6100. The RFT6100 upconverts the Tx analog baseband into RF using radioOne ZIF technology. The MSM6000 device communicates with the RF ICs to control signal gain in the RF Rx and Tx signal paths, reduce baseband offset errors, tune the handset’s operating frequencies, and configure the ICs.

QUALCOMM also supplies system software and development tools to minimize the development time of a subscriber unit. With the release of the MSM6000 device, a new, optimized version of Dual Mode Subscriber Software (DMSS™) is available with device driver support for the functionality of the MSM6000 device. Additionally, the subscriber unit reference design (SURF™) offers a baseline hardware platform for additional software development.

1.2 radioOne technologyThe MSM6000 device interfaces directly with QCT’s new radioOne RF ICs. radioOne is a revolutionary technology for CDMA transceivers that uses ZIF, or direct conversion, architecture for the wireless handset market. This direct conversion architecture eliminates the need for large IF surface acoustic wave (SAW) filters and additional IF circuitry, resulting in cost-effective multiband and multimode handsets that can be produced in smaller form factors.

The ZIF RF ICs also incorporate the frequency synthesis functions used in converting baseband signals to and from RF. A single external VCO is required for the transceiver, providing the ability to operate on systems around the world.

1.3 Reductions in overall handset cost! Eliminates IF SAW filters and additional IF circuitry

! Single band VCO for all applications (cellular band and PCS band)

! Flash/SRAM cost saving

" Reduced DMSS code size to enable smaller flash/SRAM memory

! Eliminates resistors, capacitors, and inductors for bypass and matching circuit

! Reduced PCB area

! Manufacturing line components placement time saving

! Increased terminal production yield



1.4 MSM6000 solution general features! radioOne ZIF/direct conversion architecture

! CDMA2000 1x Release 0

! Supports IS-95-A and IS-95-B compliant CDMA and AMPS subscriber units

! Voice centric (EVRC 8 kbps)

! 8x searcher, plus an independently controlled 16x searcher

! 2-way short message service (SMS)

! Supports peak rates of 14.4 kpbs packet data in forward and reverse links simultaneously

! Radio link protocol 3 (RLP3)

! Support for fast power control (both forward and reverse links)

! P-Rev 6 compliant

! Integrated voice CODEC

! Integrated general-purpose ADC for subscriber unit monitoring, e.g., temperature sensor, battery

! Embedded QDSP2000™ digital signal processor core

! Programmable general-purpose input/output (GPIO)

! Integrated R-UIM (CDMA SIM) Controller for direct interface to R-UIM card

! Supports low-power, low-frequency crystal to enable TCXO shutoff

! Low Vdc power consumption during operation

! Software-controlled power management features

! 208-ball FBGA packaging

! ANSI/IEEE 1149.1A-93 compliant JTAG interface for testability

! Enhanced I/O support for faster RS-232

1.4.1 CDMA2000 1x Release 0 features supported by the MSM6000 solution! Forward link

" PICH

" SYNCH

" PCH

" QPCH

" FCH


MSM6000™ Device Specification Overview

! Reverse link

" PICH

" ACH

" FCH

! Fast 800 Hz forward power control

NOTE The MSM6000 device and its system software only support Release 0 of the IS-2000 standard.

1.4.2 CDMA2000 1x Release 0 features not supported by the MSM6000 solution! Forward link

" TDPICH

" APICH

" ATDPICH

" BCH

" CPCCH

" CACH

" CCCH

" DCCH

" SCCH

" SCH

! Reverse link

" EACH

" CCCH

" DCCH

" SCCH

" SCH

! Orthogonal transmit diversity (OTD)

! Space time spreading diversity (STS)

! 5 ms, 10 ms, 40 ms, and 80 ms framing

! Simultaneous service options

! V2, V3, P3 modes

NOTE The MSM6000 device and its system software only supports Release 0 of the IS-2000 Standard.



1.4.3 MSM6000 audio processing features! Integrated CODEC with microphone and earphone amplifiers

! Three microphone inputs (analog)

! Three speaker outputs (analog)

! EarSeal Echo Cancellation (ESEC)

! Internal Vocoder supporting EVRC (8 kbps)

! Dual-tone multiple-frequency (DTMF) generation and detection

! Programmable digital filters for audio signal path compensation in both CDMA and AMPS modes

! Digital audio interface

! TTY

1.4.4 MSM6000 microprocessor subsystem! Industry standard ARM7TDMI embedded microprocessor subsystem

! Internal watchdog and sleep timers

! Full FIQ and IRQ interrupt controller support for internal interrupts and off-chip interrupt sources

! Seven chip select outputs for direct support of RAM, ROM/FLASH, EEPROM, an LCD Displays, and other devices

! Support for up to 48 MByte of external memory

! 16 bit SRAM Interface

! Microprocessor powerdown mode

! Programmable wait state generator

! Automatic access conversion of 32-bit data accesses to 16-bit devices

! The ARM7TDMI microprocessor can operate at up to 20 MHz with variable rate, software-controlled clocks to provide greater standby time.

1.4.5 MSM6000 supported interface features! Two universal asynchronous receiver transmitter (UART) serial ports with Rx and Tx FIFOs

! General-purpose I/O pins

! External keypad interface

! Parallel LCD interface

! Proprietary serial bus interface (SBI) that controls the other QUALCOMM ASICs in the subscriber unit.

! General-purpose programmable M/N counter output

! Programmable ringer output

! Integrated R-UIM (CDMA SIM) controller for direct interface to R-UIM card (share with UART2)


2 Pin Descriptions

2.1 I/O description parameters

Table 2-1 I/O description parameters

Symbol Description

Type

I CMOS input

IS Input with schmitt trigger

O Output

Z High-Z output

B Bidirectional

BS Bidirectional with schmitt trigger

V Power/Ground

Special circuitry

PU Contains an internal pull-up device

PD Contains an internal pull-down device

KP Contains an internal weak keeper device

Keepers cannot drive external buses.

A Analog pad

H Digital input where input voltage level may reach up to 3.6 V

(1, 3, 5, etc.) Values are the ± maximum current drive strength in mA for output pins.

n[m] Variable drive strength pins. The number ‘n’ is the drive strength when the PAD_CTL register bit is clear (0). The number ‘m’ is the drive strength when the PAD_CTL register bit is set (1).

For a more detailed description, see “MSM6000 Software interface (80-V3050-7)”

bit name: HDRIVE_CX8FMCLK, HDRIVE_MICRO, HDRIVE_HLWR


Pin Descriptions MSM6000™ Device Specification

2.2 Pin description examples

2.3 Pin names and pinouts

Table 2-2 Pin description examples

BS-PU3 BS-PU3 is a bidirectional, Schmitt-triggered pin with a pull-up able to source a maximum 3 mA.

ROM_CS2_N

[GPIO_INT38]

ROM_CS2_N is the secondary function of GPIO_INT38.

BS-PU2[3] BS-PU2[3] is a bidirectional, Schmitt-triggered pin with a pull-up whose drive strength is either 2 mA or 3 mA.

BS-PU3-KP BS-PU3 is a bidirectional, Schmitt-triggered pin with a pull-up able to source a maximum 3 mA.

Table 2-3 Pin names and pinouts

Signal name Type Pin description 208-ball FBGA

Clocks, Resets and Mode control

TCXO IA VCTCXO clock input. Power source is C15.Must use 19.2 MHz VCTCXO.

E17

SLEEP_XTAL_IN IA Sleep controller crystal oscillator input. Power source is VDD_C if Vreg disabled, or regulated VDD_C if Vreg enabled.

D12

SLEEP_XTAL_OUT OA Sleep controller crystal oscillator feedback output. Power source is VDD_C if Vreg disabled, or regulated VDD_C if Vreg enabled.

C12

RESIN_N IS Hardware reset input to system. C13

RESOUT_N B-3 Reset output from the microprocessor, rising edge of RESOUT_N is delayed from the rising edge of RESIN_N

L17

WDOG_EN IS-PU Watchdog timer enable M17

MODE1 IS-PU Determines operating mode of the MSM6000

MODE[1:0] Description

00 Reserved

01 HI-Z mode – All digital pins are High-Z

10 ICE mode – Disables ARM core for emulation

11 NATIVE mode – Normal operation/JTAG

B16

MODE0 IS-PU A17


MSM6000™ Device Specification Pin Descriptions

Microprocessor Interface

ROM_CS1_N O-2[3] First chip select for the ROM address space C1

ROM_CS2_N

[GPIO_INT38]

BS-PU2[3] Second chip select for the ROM address space R4

RAM_CS1_N B-2[3] First chip select for the RAM address space B1

RAM_CS2_N

[GPIO_INT37]

BS-PU2[3] Second chip select for the RAM address space D2

GP_CS_N

[GPIO_INT39]

BS-PU2[3] General-purpose chip select for the addressing range 0x2800000 to 0x2FFFFFF (when bit 5 of register CS_CTL is set to 1)

N3

LCD_CS_N

[GPIO_INT40]

BS-PU2[3] LCD chip select for the addressing range 0x2000000 to 0x27FFFFF (when bit 3 of register CS_CTL is set to 1)

G3

LCD_EN

[GPIO_INT41]

BS-PD2[3] LCD enable strobe F3

RD_N B-2[3] read strobe U2

LWR_N BS-PU3[5] low byte write strobe D3

HWR_N BS-PU3[5] high byte write strobe C2

LB_N

[RAM_CS2_N]

or

[GPIO_INT12]

BS-PU2[3]

or

BS-PU3

Lower byte Strobe for x16 SRAM interface.

Pin selection is chosen by BY16_PCS6_CS_N D2

or

D1

UB_N

[A0]

B-2[3] Upper byte Strobe for x16 SRAM interface E4

WE_N

[LWR_N]

BS-PU3[5] Write Strobe for x16 SRAM interface D3

OE_N

[RD_N]

B-2[3] Output enable strobe for x16 SRAM interface U2

A22

[GPIO_INT31]

BS-PD2[3] Line 22 of the microprocessor address bus A[22:0] T2

A21

[GPIO_INT15]

BS-PD-2[3] Line 21 of the microprocessor address bus A[22:0] U1

A20 B-2[3] Line 20 of the microprocessor address bus A[22:0] R2


A18 B-2[3] Line 18 of the microprocessor address bus A[22:0] P1


Table 2-3 Pin names and pinouts (continued)





A15 B-2[3] Line 15 of the microprocessor address bus A[22:0] N1



A12 B-2[3] Line 12 of the microprocessor address bus A[22:0] M1



A9 B-2[3] Line 9 of the microprocessor address bus A[22:0] L1


A7 B-2[3] Line 7 of the microprocessor address bus A[22:0] H3

A6 B-2[3] Line 6 of the microprocessor address bus A[22:0] F1


A4 B-2[3] Line 4 of the microprocessor address bus A[22:0] E1



A1 B-2[3] Line 1 of the microprocessor address bus A[22:0] T1


D15 B-KP2[3] Line 15 of the microprocessor data bus D[15:0] M3

D14 B-KP2[3] Line 14 of the microprocessor data bus D[15:0] L2

D13 B-KP2[3] Line 13 of the microprocessor data bus D[15:0] K1

D12 B-KP2[3] Line 12 of the microprocessor data bus D[15:0] L4


D10 B-KP2[3] Line 10 of the microprocessor data bus D[15:0] J1



D7 B-KP2[3] Line 7 of the microprocessor data bus D[15:0] H1




D3 B-KP2[3] Line 3 of the microprocessor data bus D[15:0] G1








General-purpose Interface

NC(Previously GPIO_INT50)

BS-PD3[5] This pin is configured as an NC pin. Do NOT connect Vdd or GND to this pin. This pin should be open.

C6

GPIO_INT49 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N B7

GPIO_INT48 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N A8

GPIO_INT47 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N D7

GPIO_INT46 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N C7

GPIO_INT45 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N B8

GPI_INT44 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N A9

GPI_INT43 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N D8

GPI_INT42 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N C8

GPIO_INT41 BS-PD2[3] Configured as an input, and a pull-down on assertion of RESOUT_N

Alternate function: LCD_EN

F3

GPIO_INT40 BS-PU2[3] Configured as an input, and a pull-up on assertion of RESOUT_N

Alternate function: LCD_CS_N

G3


Alternate function: GP_CS_N

N3


Alternate function: ROM_CS2_N

R4


Alternate function: RAM_CS2_N or LB_N

D2

GPIO_INT36 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N B9

GPIO_INT35 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N A10

GPIO_INT34 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N C9


GPIO_INT32 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N A11


Alternate function: A[22]

T2

GPIO_INT27 BS-PD5 Configured as an input, and a pull-down on assertion of RESOUT_N D11

GPIO_INT26 BS-PD5 Configured as an input, and a pull-down on assertion of RESOUT_N U6





GPIO_INT25 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N R5

GPIO_INT24 BS-PD1 Configured as an input, and a pull-down on assertion of RESOUT_NFor dual-band applications where both the PAs (using PA_ON0, PA_ON1 pins) are used, GPIO_INT24 pin is not available for use.

Single-band applications can use GPIO_INT24. (Must use PA_ON0).

P5

GPIO_INT23 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N P9

GPIO_INT22 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N P4

GPIO_INT21 BS-PU3 Configured as an input, and a pull-up on assertion of RESOUT_N

Alternate function: DP_TX_DATA2 or UIM_DATA

C14

GPIO_INT20 BS-PD1 Configured as an input, and a pull-down on assertion of RESOUT_N

Alternate function: DP_RX_DATA2

A15


Alternate function: RFR_N2 or UIM_CLK

U8

GPIO_INT18 BS-PD1 Configured as an input, and a pull-down on assertion of RESOUT_N

Alternate function: CTS_N2

T9

GPIO_INT17 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N C11

GPIO_INT16 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N A6


Alternate function: A[21]

U1


GPIO_INT13 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N T6


Alternate Function: LB_N

D1


GPIO_INT9 BS-PD3 Configured as an input, and a pull-down on assertion of RESOUT_N T5


GPIO_INT4 BS-PU1 Configured as an input, and a pull-up on assertion of RESOUT_N C3


Alternate function: PCM_DOUT

A5


Alternate function: PCM_DIN

D4


Alternate function: PCM_CLK

C4






Alternate function: PCM_SYNC

B5

User Interface

KEYSENSE4_N IS-PU KEYSENSE[4:0] is used to sense key contact closure when connected to an external keypad. The input signal is an active-low, level-sensitive input and is connected to the interrupt controller for the microprocessor.

D5

KEYSENSE3_N IS-PU C5

KEYSENSE2_N IS-PU B6

KEYSENSE1_N IS-PU A7

KEYSENSE0_N IS-PU D6

RINGER O-5 DTMF tone generator output. This output drives the external power transistor for the sound transducer. It is used to produce the pitch, cadence, and volume of the subscriber’s ring.

T7

PCM Interfaces

AUX_PCM_CLK O-3 PCM clock for auxiliary CODEC port

Alternate function: RFR_N2 or UIM_CLK

R9

AUX_PCM_SYNC BS-PD3 PCM data strobe for auxiliary CODEC port

Alternate function: CTS_N2

T8

AUX_PCM_DIN IS-PD PCM data input for auxiliary CODEC port

Alternate function: DP_RX_DATA2

P8

AUX_PCM_DOUT BS-PU3 PCM data output for auxiliary CODEC port

Alternate function: DP_TX_DATA2 or UIM_DATA

R8

CODEC Signal Description

MIC1P IA Mic 1 input (+) T12

MIC1N IA Mic 1 input (–) U11

MIC2P IA Mic 2 input (+) P13

MIC2N IA Mic 2 input (–) R13

AUXIP IA Auxiliary input (+) P12

AUXIN IA Auxiliary input (–) R12

MICOUTP OA Mic output to external Tx high pass filter (+) T13

MICOUTN OA Mic output to external Tx high pass filter (–) U12

MICINP IA Mic input from external Tx high pass filter (+) U13

MICINN IA Mic input from external Tx high pass filter (–) R15

MICFBP IA Mic amp feedback from external Tx high pass filter (+) R14

MICFBN IA Mic amp feedback from external Tx high pass filter (–) P14





EAR1OP OA Earphone 1 amplifier output (+) T10

EAR1ON OA Earphone 1 amplifier output (–) U9

EAR2O OA Earphone 2 amplifier output, single-ended P11

AUXOP OA Auxiliary output (+) U10

AUXON OA Auxiliary output (–) T11

MICBIAS OA Microphone bias supply output U15

CCOMP IA External decoupling capacitor input for CODEC voltage reference U16

GND_RET Ground return for bypass capacitor to CCOMP.

Connect GND_RET to GND (pin U14).

T15

UART Interfaces

DP_TX_DATA O-3 UART transmit serial data output A3

DP_RX_DATA IS-PD UART receive serial data input B3

CTS_N IS-PD UART clear-to-send signal A2

RFR_N O-3 UART ready-for-receive signal A1

DP_TX_DATA2

[GPIO_INT21]

[AUX_PCM_DOUT]

BS-PU3

or

BS-PU3

UART2 transmit serial data output

Alternate function: UIM_DATA C14

or

R8

DP_RX_DATA2

[GPIO_INT20]

[AUX_PCM_DIN]

BS-PD1

or

IS-PD

UART2 receive serial data input

A15

or

P8

RFR_N2

[GPIO_INT19]

[AUX_PCM_CLK]

BS-PU3

or

O-3

UART2 clear-to-send signal

Alternate function: UIM_CLK U8

or

R9

CTS_N2

[GPIO_INT18]

[AUX_PCM_SYNC]

BS-PD1

or

BS-PD3

UART2 ready-for-receive signal

T9

or

T8

Serial Bus Interface

SBDT B-2[5] Serial bus data J15

SBCK B-2[5] Serial bus clock K16

SBST O-1[5] Serial bus start/stop control signal J14





AUX_SBI_DT BS-PU1 Auxiliary SBI bus for RFT6100 serial bus dataGPIO_INT6 is dedicated to this function, and cannot be changed.

A4

AUX_SBI_CK BS-PU1 Auxiliary SBI bus for RFT6100 serial clockGPIO_INT7 is dedicated to this function, and cannot be changed.

U3

AUX_SBI_ST BS-PD1 Auxiliary SBI bus for RFT6100 serial bus strobeGPIO_INT8 is dedicated to this function, and cannot be changed.

T4

RF Transmit Interface

I_OUT OA I_OUT and I_OUT_N are the differential output pair of the I-channel transmit DAC.

G15

I_OUT_N OA G14

Q_OUT OA Q_OUT and Q_OUT_N are the differential output pair of the Q-channel transmit DAC.

F14

Q_OUT_N OA F15

DAC_REF IA DAC_REF is the input reference for the I and Q transmit DACs. It is used to set the full-scale of the DAC outputs.

G17

PA_ON0 O-5 When PA_ON0 is HIGH, the output of the RF power amplifier is enabled. PA_ON0 enables the subscriber unit to transmit the required data.

PA_ON0 is used for cellular band PA control.

H16

PA_ON1 O-5 Control signal for a second power amplifier.

PA_ON1 is used for PCS band PA control.

J17

TX_AGC_ADJ Z-PD1[5] TX_AGC_ADJ is a PDM output produced by the transmit AGC subsystem. It is used to control the gain of the transmit signal prior to the power amplifier.

E15

PA_R1 Z-2 PA_R[1:0] is an open-drain output, requiring an external pull-up resistor. PA_R[1:0].may be used by the PAs to change gain and/or PA’s efficiency vs Pout.

E16

PA_R0 Z-2 F17

TX_ON BS-PD5 Puncture control for TX_ON pin on RFT6100. B12

TX_PCS_LOW BS-PD5 Control SPDT (single pole double throw) switch to choose PCS low band (PCS channel < = 600). TX_PCS_LOW complements TX_PCS_HI. Active high.GPIO_INT30 is dedicated to this function.

D10

TX_PCS_HI BS-PD5 Control SPDT (single pole double throw) switch to choose PCS high band (PCS channel > 600). TX_PCS_HI complements TX_PCS_LOW. Active high.GPIO_INT29 is dedicated to this function.

B11

RF Receive Interface

I_IP IA Differential analog I signal (+) N14

I_IN IA Differential analog I signal (–) P16

Q_IP IA Differential analog Q signal (+) M14





Q_IN IA Differential analog Q signal (–) N16

FM_LNA_RANGE Z-2 FM_LNA_RANGE is an open-drain digital output produced by the receive AGC subsystem. The FM_LNA_RANGE is designed to change states at programmable thresholds of receive signal strength in FM mode. This allows the subscriber unit to alter the receive signal path by bypassing or enabling the receive RF components at these thresholds. This pin requires a pull-up resistor to be connected to RFL6000 FM_STEP input. LNA_RANGE0 is dedicated to this function.

D16

EXT_VCO_EN BS-PD5 Enable signal for external VCO.

1 = VCO enable

0 = VCO disableGPIO_INT28 is dedicated to this function.

A12

Miscellaneous RF Signals

TCXO_EN BS-PU3 Enable signal for VCTCXO

1 = VCTCXO enable

0 = VCTCXO disableGPIO_INT11 is dedicated to this function.

T3

TRK_LO_ADJ Z-1[5] TRK_LO_ADJ is a PDM output from the frequency tracking subsystem which adjusts the subscriber units VC-TCXO and RF VCO.

D15

SYNTH_LOCK IS Indicates the lock status of the Tx and Rx frequency synthesizers. SYNTH_LOCK is an input from the frequency synthesizers to indicate the current lock status. A high signal indicates a LOCK condition.

F16

General-purpose ADC Interface

HKADC6 IA Input 6 to the general-purpose ADC U17

HKADC5 IA Input 5 to the general-purpose ADC T16

HKADC4 IA Input 4 to the general-purpose ADC T17

HKADC3 IA Input 3 to the general-purpose ADC R17

HKADC2 IA Input 2 to the general-purpose ADC P15

HKADC1 IA Input 1 to the general-purpose ADC R16

HKADC0 IA Input 0 to the general-purpose ADC P17

Miscellaneous I/O

GP_MN O-1 GP_MN is the output programmable, general-purpose, M/N counter. The counter is clocked by the general clock which is TCXO/4 or SleepXtal, as selected by MSM_CLK_CTL5 bit 10.

P7

GP_PDM0 BS-PD1[5] GP_PDM1 is an 8-bit, programmable pulse density modulator and is clocked by TCXO/4.

C17

GP_PDM1 Z-PD1[5] GP_PDM1 is an 8-bit, programmable pulse density modulator and is clocked by TCXO/4.

C16





JTAG Interface

TDO Z3 JTAG data output B15

TDI BS-PU3 JTAG data input B14

TMS BS-PU3 JTAG mode select input B13

TRST_N BS-PU3 JTAG reset

TRST_N must be low at power-up for the TAP Controller to be initialized to the Test-Logic-Reset state.

A13

TCK BS-PU3 JTAG clock input A14

TMODE IS-PU TMODE determines which one of the two possible scan chains the JTAG interface will use.

TMODE Description

0 The ARM scan chain is selected.

1 The MSM6000 Pin scan chain is selected

D13

Power/Ground Pin Description

VDD_C V Supply voltage for internal digital circuits K15, L3, P6

VDD_P V Supply voltage for peripheral interface, PAD voltage E3, J16, U4

VDD_A V Supply voltage for internal analog circuits

Codec T14

Ear Amplifiers P10

HKADC, BBRX M16, N17

TXDAC G16

PLL C15

GND V GND A16, B2, C10, D9,

D14, H17, K3, K14,

L16, M15, N15, R10, R11, U5, U7, U14

NC — Do NOT connect Vdd or GND with these NC pins.

These pins should be open.

B17, D17, E14, H14, H15, K17, L14, L15,

C6





LK

2.4 208-ball FBGA pinout for MSM6000 device (top view)

Table 2-4 208-ball FBGA pinout for MSM6000 device (top view)

1 2 3 4 5 6 7 8 9

A RFR_N CTS_N DP_TX_DATA AUX_SBI_DT GPIO_INT3 GPIO_INT16 KEYSENSE1_N GPIO_INT48 GPIO_INT44

B RAM_CS1_N GND DP_RX_DATA GPIO_INT5 GPIO_INT0 KEYSENSE2_N GPIO_INT49 GPIO_INT45 GPIO_INT36

C ROM_CS1_N HWR_N GPIO_INT4 GPIO_INT1 KEYSENSE3_N NC GPIO_INT46 GPIO_INT42 GPIO_INT34

D GPIO_INT12 GPIO_INT37 LWR_N GPIO_INT2 KEYSENSE4_N KEYSENSE0_N GPIO_INT47 GPIO_INT43 GND

E A4 A2 VDD_P A0

F A6 A5 GPIO_INT41 A3

G D3 D1 GPIO_INT40 D0

H D7 D4 A7 D2

J D10 D8 D5 D6

K D13 D11 GND D9

L A9 D14 VDD_C D12

M A12 A10 D15 A8

N A15 A13 GPIO_INT39 A11

P A18 A17 A14 GPIO_INT22 GPIO_INT24 VDD_C GP_MN AUX_PCM_DIN GPIO_INT23

R A19 A20 A16 GPIO_INT38 GPIO_INT25 GPIO_INT10 GPIO_INT14 AUX_PCM_DOUT AUX_PCM_C

T A1 GPIO_INT31 TCXO_EN AUX_SBI_ST GPIO_INT9 GPIO_INT13 RINGER AUX_PCM_SYNC GPIO_INT18

U GPIO_INT15 RD_N AUX_SBI_CK VDD_P GND GPIO_INT26 GND GPIO_INT19 EAR1ON

10 11 12 13 14 15 16 17

A GPIO_INT35 GPIO_INT32 EXT_VCO_EN TRST_N TCK GPIO_INT20 GND MODE0

B GPIO_INT33 TX_PCS_HI TX_ON TMS TDI TD0 MODE1 NC

C GND GPIO_INT17 SLEEP_XTAL_OUT RESIN_N GPIO_INT21 VDD_A GP_PDM1 GP_PDM0

D TX_PCS_LOW GPIO_INT27 SLEEP_XTAL_IN TMODE GND TRK_LO_ADJ FM_LNA_RANGE NC

E NC TX_AGC_ADJ PA_R1 TCXO

F Q_OUT Q_OUT_N SYNTH_LOCK PA_R0

G I_OUT_N I_OUT VDD_A DAC_REF

H NC NC PA_ON0 GND

J SBST SBDT VDD_P PA_ON1

K GND VDD_C SBCK NC

L NC NC GND RESOUT_N

M Q_IP GND VDD_A WDOG_EN

N I_IP GND Q_IN VDD_A

P VDD_A EAR20 AUXIP MIC2P MICFBN HKADC2 I_IN HKADC0

R GND GND AUXIN MIC2N MICFBP MICINN HKADC1 HKADC3

T EAR1OP AUXON MIC1P MICOUTP VDD_A GND_RET HKADC5 HKADC4

U AUXOP MIC1N MICOUTN MICINP GND MICBIAS CCOMP HKADC6


NOT
E Specifications in this chapter are target specifications for the MSM6000, and are subject to change
3 Electrical Specifications

3.1 DC electrical specifications

3.1.1 Absolute maximum ratings

Operating the MSM6000 IC under conditions that exceed those listed in Table 3-1 may result in damage to the device. Absolute maximum ratings are limiting values, and are considered individually, while all other parameters are within their specified operating ranges. Functional operation of the MSM6000 under any of the conditions in Table 3-1 is not implied.

Table 3-1 Absolute maximum ratings

Symbol Parameter Min Max Units

TS Storage temperature –65 +150 °C

TJ Junction temperature — +150 °C

VI Voltage on any input or output pin –0.5 VDD + 0.5 V

VDD Supply voltage –0.3 +3.7 V

IIN Latchup current — 100 mA

VESD(HBM)

Electrostatic discharge voltage (Human Body Model)

JESD 22-A114-B

— 1500 V

VESD(CDM)

Electrostatic discharge voltage (Charged Device Model)

JESD 22-C101

— 500 V


without notice.

Electrical Specifications MSM6000™ Device Specification

NOTE Specifications in this chapter are target specifications for the MSM6000, and are subject to change

3.1.2 Recommended operating conditions

3.1.3 DC characteristics

Table 3-2 Recommended operating conditions

Symbol Parameter Min Typ Max Units

TC Case operating temperature –30 — 85 °C

VDD_C1 Supply voltage for internal digital circuits (Vreg enabled) 2.5 2.8 3.0 V

VDD_C2 Supply voltage for internal digital circuits (Vreg disabled) 2.3 2.6 2.7 V

VDD_P Supply voltage for peripheral interface 2.3 2.8 3.0 V

VDD_A Supply voltage for internal analog circuits 2.5 2.6 2.7 V

Table 3-3 Thermal dissipation

Parameter Description Typ Units

θJA Junction to still air 31 °C/W

θJC Junction to case 7 °C/W

Table 3-4 DC characteristics

Parameter Description Min Max Units Notes

VIH High-level input voltage, CMOS/Schmitt 0.65 • VDD_P VDD_P + 0.3 Volts —

VIL Low-level input voltage, CMOS/Schmitt –0.3 0.35 • VDD_P Volts —

VTCXOHDC High-level input voltage, TCXO DC coupled input

0.65 • VDD_A VDD_A + 0.3 Volts —

VTCXOLDC Low-level input voltage, TCXO DC coupled input

–0.3 0.35 • VDD_A Volts —

VTCXOAC Peak-to-peak input voltage, TCXO AC coupled input

0.5 VDD_A + 0.3 Volts —

IIH Input high leakage current — 2 µA a

IIL Input low leakage current –2 — µA a

IIHPD Input high leakage current with pull-down 10 60 µA a,b

IILPU Input low leakage current with pull-up –60 –10 µA b,c

IOZH High-level, three-state leakage current — 2 µA a


without notice.

MSM6000™ Device Specification Electrical Specifications

NOT
IOZL Low-level, three-state leakage current –2 — µA b

IOZHPD High-level, three-state leakage current with pull down

10 60 µA a,c

IOZLPU Low-level, three-state leakage current with pull up

–60 –10 µA b,c

IOZHKP High-level, three-state leakage current with keeper

–25 –3 µA a,c

IOZLKP Low-level, three-state leakage current with keeper

3 25 µA b,c

VOH High-level output voltage, CMOS VDD_P – 0.45 VDD_P Volts d

VOL Low-level output voltage, CMOS 0.0 0.45 Volts d

CIN Input capacitance — TBD pF —

a Pin voltage = VDD_P max. For keeper pins, pin voltage = VDD_P max – 0.45 volts.b Pin voltage = Vss and VDD_P = VDD_P max. For keeper pins, pin voltage = 0.45 volts and VDD_P = VDD_P max.c Refer toTable 2-3 for pins having pull-ups, pull-downs, and keepers.d Refer toTable 2-3 for IOH and IOL current capacity for output pins (at VDD_P = VDD_P min).

Table 3-4 DC characteristics (continued)



without notice.



3.1.4 General-purpose ADC specifications

Note:1. For an acquisition time of 3 clk periods, the CLK period > 2 • τ, τ = 2 • (input resistance + source resistance) • input

capacitance.2. integral nonlinearity (INL), differential nonlinearity (DNL).

Table 3-5 GPADC performance specification

Parameter Min Typ Max Units Comments/conditions

Resolution — 8 — BITS

DNL -0.75 — +0.75 LSB Analog Vdd = ADC reference

300KHz-1.2MHz Sample RateINL -1.5 — +1.5 LSB

Gain Error -2.5 — +2.5 %

Offset Error -3 — +3 LSB

DNL -0.75 — +0.75 LSB V2 as ADC reference

300KHz Sample RateINL -1.5 — +1.5 LSB

Gain Error -7 — +7 %


DNL -0.75 — +0.75 LSB Internal Bandgap Reference

300KHz Sample RateINL -1.5 — +1.5 LSB



DNL -0.75 — +0.75 LSB Internal Bandgap Reference Div2

300KHz Sample RateINL -2 — +2 LSB



Channel Isolation — 50 — dB @ DC

Full-Scale Input Range GND — VRT — VRT is variable 0 V to VDD_A

3 dB Input Bandwidth — 2500 — kHz Source resistance = 50 Ohms

Input Serial Resistance — 5 — kOhm Sample&Hold Switch Resistance

Input Capacitance — 12 — pF

Powerdown to Wakeup — — 5 µS

Throughput Rate 20.8 — 170.7 kHz


without notice.


NOT
3.1.5 Codec specifications

Table 3-6 Microphone interface

Parameter Test Conditions Min Typ Max Unit

VIO Input offset voltage at MIC1, MIC2 and AUX inputs

Over Recommended Ranges of Supply Voltage and Free-Air Temperature

–5 — +5 mV

CI Input capacitance at MIC1, MIC2 and AUX inputs

— 5 — pF

Input DC Common Mode Voltage

0.85 0.9 0.95 V

VMBIAS Microphone bias supply voltage

Open Circuit DC Voltage 1.69 1.8 1.91 V

MBIAS Output DC source current

1.69 kΩ 1% resistive load 1 1.07 — mA

MICMUTE attenuation +3 dBm0 analog input level 1.02 kHz sine-wave

80 — — dB

Zin Input impedance, MIC1, MIC2 and AUX inputs

fully differential 62 72 82 kΩ


without notice.



Table 3-7 Speaker interface


PO1 Earphone Amp1 output power (rms)

Differential, 32Ω load, Digital input = +3 dBm0, 1.02 kHz sine-wave

— 35 — mW

PO2 Earphone Amp2 output power (rms)

Single ended, 32Ω load, Digital input = +3 dBm0, 1.02 kHz sine-wave

— 8.8 — mW

PO3 Auxiliary Amp output power (rms)

Differential, 600Ω load, Digital input = +3 dBm0, 1.02 kHz sine-wave

— 1.87 — mW

Output DC offset voltage between EAR1OP and EAR1ON, AUXOP and AUXON

Fully differential –50 50 mV

Output common mode voltage, EAR1OP, EAR1ON, EAR2O AUXOP, AUXON

Measured at each output pin with respect to GND

1.12 1.2 1.27 V

ZOUT1 Differential Output Impedance At 1.02 kHz, for outputs EAR1O and AUXO

— — 1 Ω

ZOUT2 Single-ended output impedance At 1.02 kHz, for output EAR2 — — 0.5 Ω

IOmax Maximum output current for EAR1 (rms)

Digital input = +3 dBm0, 32Ω load, 1.02 kHz sine-wave

— 33 — mA

IOmax Maximum output current for EAR2 (rms)


— 16.6 — mA

IOmax Maximum output current for AUXO (rms)


— 1.77 — mA

THD Total harmonic distortion Digital input = +3 dBm0, 498 Hz sine-wave, 32Ω load for Ear Amps 1 & 2, 600Ω load for Aux Output.

— — 5 %

EARMUTE attenuation Digital input = +3 dBm0, 1.02 kHz sine-wave

80 — — dB

Note:+3 dBm0 level corresponds to 13-bit, 0 dB Full-Scale sine-wave.


without notice.


NOT
Table 3-8 Transmit path level translation and linearity, MIC AMP2 enabled


Transmit reference-signal level (0 dBm0) Differential analog input — 57.3 — mVRMS

Overload-signal level (+3 dBm0) Differential analog input — 229 — mVPP

Overload-signal level (+3 dBm0) at the analog modulator input (MICFBN, MICFBP)

Differential analog input — 3.626 — VPP

Absolute gain error 0 dBm0 analog input level, 1.02 kHz sine-wave –1 — 1 dB

Gain error relative to gain at –10 dBm0 Analog Input Level from +3 dBm0 to –30 dBm0 –0.5 — 0.5 dB

Gain error relative to gain at –10 dBm0 Analog Input Level from –31 dBm0 to –45 dBm0 –1 — 1 dB

Gain error relative to gain at –10 dBm0 Analog Input Level from –46 dBm0 to –55 dBm0 –1.5 — 1.5 dB

Notes:• These specifications apply to all three Tx path inputs: Mic inputs 1 & 2 and Aux In.• The total transmit channel gain in this default configuration is +24 dB (Microphone amplifier 1 is set to +6 dB. The external gain is set to

+18 dB.

Table 3-9 Transmit path level translation and linearity, MIC AMP2 bypassed


Transmit reference-signal level (0 dBm0) Differential analog input — 455 — mVRMS

Overload-signal level (+3 dBm0) Differential analog input — 1.82 — VPP

Overload-signal level (+3 dBm0) at the analog modulator input (MICFBN, MICFBP)

Differential analog input — 3.626 — VPP

Absolute gain error 0 dBm0 analog input level, 1.02 kHz sine-wave –1 — 1 dB

Gain error relative to gain at –10 dBm0 Analog Input Level from +3dBm0 to –30 dBm0 –0.5 — 0.5 dB

Gain error relative to gain at –10 dBm0 Analog Input Level from –31 dBm0 to –45 dBm0

–1 — 1 dB

Gain error relative to gain at –10 dBm0

Analog Input Level from –46 dBm0 to –55 dBm0 –1.5 — 1.5 dB

Notes:• These specifications apply to all three Tx path inputs: Mic inputs 1 & 2 and Aux In.• The total transmit channel gain in this default configuration is +6 dB (Microphone amplifier 1 is set to +6 dB).


without notice.



Table 3-10 Transmit path idle channel noise and distortion


Transmit noise, C-message weighted

External gain = +18 dB,Microphone amplifier 1 gain = +6 dB

— — 15 µVRMS

Transmit signal-to-THD+N ratio with 1020Hz sine-wave input

Analog Input Level at +3 dBm0 35 — — dB

Analog Input Level at 0 dBm0 50 — — dB

Analog Input Level at –5 dBm0 50 — — dB





Analog Input Level at +3 dBm0 to –45 dBm0

25 — — dB

Notes:• Specifications must be met without the Tx Slope Filter enabled.• Specifications must be met for all inputs MIC1, MIC2 and AUX.

Table 3-11 Receive path level translation and linearity, EAR1 and AUXO


Receive reference-signal level (0 dB)

Digital input = 0 dBm0, 1.02 kHz sine-wave

— 750 — mVRMS

Overload-signal level (+3 dB) Digital input = +3 dBm0, 1.02 kHz sine-wave

— 3 — VPP

Absolute gain error Digital input = 0 dBm0, 1.02 kHz sine-wave

–1 — +1 dB


Digital input = +3 dBm0 to –40 dBm0 –0.5 — +0.5 dB


Digital input = –41 dBm0 to –50 dBm0

–1 — +1 dB


Digital input = –51 dBm0 to –55 dBm0

–1.2 — +1.2 dB

Notes:• Output measured differentially between EAR1ON and EAR1OP• +3 dBm0 level corresponds to 13-bit, 0 dB Full-Scale sine-wave• Unloaded condition


without notice.


NOT
Table 3-12 Receive path level translation and linearity, EAR2 selected


Receive reference-signal level (0 dBm0)

Digital input = 0 dBm0, 1.02 kHz sine-wave — 375 — mVRMS

Overload-signal level (+3dBm0)

Digital input = +3 dBm0, 1.02 kHz sine-wave — 1.5 — VPP

Absolute gain error Digital input = 0 dBm0, 1.02 kHz sine-wave –1 — +1 dB


Digital input = +3 dBm0 to –40 dBm0 –0.5 — +0.5 dB


Digital input = –41 dBm0 to –50 dBm0 –1 — +1 dB


Digital input = –51 dBm0 to –55 dBm0 –1.2 — +1.2 dB

Notes:• Output measured single-ended between EAR2O and AVSS• +3 dBm0 level corresponds to 13-bit, 0 dB Full-Scale sine-wave• Unloaded condition

Table 3-13 Receive path idle channel noise and distortion, EAR1 and AUXO selected


Receive noise (A-weighted) Digital input = “0000000000000” — — 200 µVRMS

Receive signal-to-THD+N ratio with 1020 Hz sine-wave input

Digital input = +3 dBm0 29 — — dB

Digital input = 0 dBm0 50 — — dB

Digital input = –5 dBm0 47 — — dB






Intermodulation distortion (2 tone method)

Digital input = 498 Hz and 2.02 kHz equal amplitude tones, composite peak level equivalent to 0 dBm0 sine-wave.

50 — — dB

Notes:• Output measured differentially with 32Ω load for EAR1O and 600Ω load for AUXO


without notice.



Table 3-14 Receive path idle channel noise and distortion, EAR2 selected


Receive noise (A-weighted) Digital input = “0000000000000” — — 106 µVRMS

Receive signal-to-THD+N ratio with 1020 Hz sine-wave input

Output Level at +3 dBm0 26 — — dB

Output Level at 0 dBm0 45 — — dB

Output Level at –5 dBm0 44 — — dB






Intermodulation distortion (2 tone method)

PCMI = 498 Hz and 2.02 kHz equal amplitude tones, composite peak level equivalent to 0 dBm0 sine-wave.

50 — — dB

Notes: • Output measured single-ended with 32Ω load and DC blocking capacitor (33 uF or greater) connected between

EAR20 and AVSS

Table 3-15 Crosstalk attenuation


Crosstalk attenuation, transmit-to-receive (differential) with sidetone disabled

0 dBm0 Analog Input Level. Frequency = 300 – 3400 Hz. Measured differentially at Rx Path output

70 — — dB

Crosstalk attenuation, receive-to-transmit

Digital input = 0 dBm0, Frequency = 300 – 3400 Hz. Measured at PCMO, Ear1/Ear2/AUXO amp unloaded

70 — — dB

Notes:• Applies to all three Tx path inputs and all three Rx Path outputs


without notice.


NOT
3.1.6 Power consumption

These values are an estimation of operating currents for the nominal VDD_P, VDD_C and VDD_A voltages. This information should be used as a general guideline for system design. CDMA modes assume that the subscriber unit is operating in compliance with the CDMA specifications of IS-95-B. FM modes assume that the subscriber unit is operating in compliance with the AMPS specifications of IS-95-A.

Figure 3-1 Power supply current versus time in slotted paging mode

Table 3-16 MSM6000 power supply current

Operating mode Digital2.60 V

Analog2.60 V

Pad2.80 V Notes

CDMA SLEEP 31.9 µA 1.6 uA 102.2 µA a

a Values shown in the Average columns represent a time average of the observed data from recent testing conducted by QUALCOMM over a limited number of devices at Room Temperature (25 °C). See Figure 3-1 for illustrations of "Average" power supply current.

CDMA Rx 41.8 mA 7.4 mA 5.5 mA a

CDMA RxTx 56.7 mA 18.6 mA 6.0 mA a

FM IDLE 9.9 mA 5.5 mA 2.7 mA a

FM RxTx 19.6 mA 20.1 mA 3.6 mA a

Peak-peak variation ofCDMA SLEEP Current

Average ofCDMA SLEEP

Current

Average ofCDMA Rx Current

Peak-peak variation ofCDMA Rx Current

CDMA SLEEP

(500 ms/div.)

CDMA RX

089-001


without notice.



3.1.7 Power sequencing

3.1.7.1 Power up recommendations

To be sure that all pads and analog portions of the chip are in a known state, the core voltage, VDD_C, comes up first. The slew rate for the core power to reach its 90% should be 25 µsec. After the core voltage has reached its 90% (i.e., after 25 µsec from the start), the pad voltage, VDD_P, can come up. The analog voltage, VDD_A, could come up at the same time as the pad voltage.

Figure 3-2 Power ramp up recommendation

0 V

90%

10%0 V

90%

10%

25µs(min)

t

t

of V DD P, A

V DD_PVDD_A

of VDD

P, A

of V DD C

of VDD C

VDD_C


without notice.


NOT
3.1.7.2 Power down recommendations

To be sure that all pads and analog portions of the chip are in a known state, VDD_C should be powered down after the other VDD supplies.

Figure 3-3 Power ramp down recommendation

0 V

90%

10%0 V

90%

10%

1s(max)

1s(max)

t

t

400us

(max)

of VDD P, A

of VDD P, A

of V DD C

of VDD

C

V DD_PVDD_A

VDD_C


without notice.



3.2 Timing characteristics

3.2.1 TCXO timing

Figure 3-4 TCXO timing parameters

3.2.2 MCLK timing

Table 3-17 TCXO timing parameters

Symbol Parameter Min Typ Max Units Note

tXOH TCXO logic high 20 — — ns

tXOL TCXO logic low 20 — — ns

Ttcxo Clock cycle period — 52.083 — ns a

a The MSM6000 chipset solution must use 19.2MHz VCTCXO.

ftcxo Frequency (=1/Ttcxo) — 19.2 — MHz a

TCXO

XOH XOL

089-041

t t

Average(DC component)

Ttcxo

Table 3-18 MCLK timing parameters

Symbol Parameter Min Typ Max Units Note

MCLK ARM Microprocessor clock — 52.083 — ns a

a Note: MCLK clock period is equal to T. The MCLK frequency is the same as the TCXO frequency. MCLK is derived from TCXO within the MSM6000 device.


without notice.


NOT
3.2.3 PCM interface

Table 3-19 provides timing values for Figure 3-5, Figure 3-6, and Figure 3-7.

Figure 3-5 PCM_SYNC timing

Figure 3-6 PCM_CODEC to MSM6000 timing

Figure 3-7 MSM6000 to PCM_CODEC timing

PCM_SYNCtsyncd

tsync

tsynca 089-005

PCM_CLK

PCM_SYNC

PCM_DIN

tsu(sync)

tclkhtclkl

tclk

th(sync)

tsu(DIN)

LSBitMSBit

th(DIN)(from MSM)

(from MSM)

089-006

PCM_CLK

PCM_SYNC

PCM_DOUT

tsu(sync)

tclkhtclkl

tclk

th(sync)

tpdout tpdout

tzdout

LSBitMSBit

(from MSM)

(from MSM)

089-007

Table 3-19 PCM_CODEC timing parameters

Parameter Description Min Typical Max Units Notes

tsync PCM_SYNC cycle time (PCM_SYNC_DIR=1) — 125 — µs a

PCM_SYNC cycle time (PCM_SYNC_DIR=0) — 125 — µs

tsynca PCM_SYNC “asserted” time (PCM_SYNC_DIR=1) 468 488 508 ns 1

PCM_SYNC “asserted” time (PCM_SYNC_DIR=0) — — — ns


without notice.



tsyncd PCM_SYNC “deasserted” time (PCM_SYNC_DIR=1) — 124.5 — µs 1

PCM_SYNC “deasserted” time (PCM_SYNC_DIR=0) — — — µs

tclk PCM_CLK cycle time (PCM_CLK_DIR=1) 468 488 508 ns 1

PCM_CLK cycle time (PCM_CLK_DIR=0) — — — ns

tclkh PCM_CLK high time (PCM_CLK_DIR=1) 224 244 264 ns 1, b

PCM_CLK high time (PCM_CLK_DIR=0) — — — ns

tclkl PCM_CLK low time (PCM_CLK_DIR=1) 224 244 264 ns 1, 2

PCM_CLK low time (PCM_CLK_DIR=0) — — — ns

tsu(sync) PCM_SYNC setup time to PCM_CLK falling(PCM_SYNC_DIR = 1, PCM_CLK_DIR = 1)

102 122 142 ns

PCM_SYNC setup time to PCM_CLK falling(PCM_SYNC_DIR = 0, PCM_CLK_DIR = 0)

— — — ns

th(sync) PCM_SYNC hold time after PCM_CLK falling(PCM_SYNC_DIR = 1, PCM_CLK_DIR = 1)

— 350 — ns

PCM_SYNC hold time after PCM_CLK falling(PCM_SYNC_DIR = 0, PCM_CLK_DIR = 0)

— — — ns

tsu(din) PCM_DIN setup time to PCM_CLK falling 30 — — ns

th(din) PCM_DIN hold time after PCM_CLK falling 10 — — ns

tpdout Delay from PCM_CLK rising to PCM_DOUT valid — — 30 ns

tzdout Delay from PCM_CLK falling to PCM_DOUT HIGH-Z — One VocoderClock Cycle

— —

a This value assumes that CODEC_CTL is not being used to override the CDMA CODEC clock and sync operation.b tclkh and tclkl are independent of PCM_CLK_SENSE.

Table 3-19 PCM_CODEC timing parameters (continued)



without notice.


NOT
3.2.4 Auxiliary PCM interface

Figure 3-8 AUX_PCM_SYNC timing

Figure 3-9 CODEC to MSM6000 timing via AUX_CODEC (MSM6000 receiving

Figure 3-10 MSM6000 to CODEC timing via AUX_CODEC (MSM6000 transmitting)

AUX_PCM_SYNC

tAUXSYNCA tAUXSYNCD

tAUXSYNC

089-009

AUX_PCM_CLK

AUX_PCM_SYNC

AUX_PCM_DIN

tSU(AUX_SYNC)

tAUXCLKHtAUXCLKL

AUX_PCM_DIN

t AUXCLK

tH(AUX_SYNC)

tSU(AUX_DIN) tH(AUX_DIN)

MSB MSB-1 LSB

MSB MSB-1 LSBLSB MSB-8MSB-2

(Companded)

(Linear)089-010

AUX_PCM_CLK

AUX_PCM_SYNC

AUX_PCM_DOUT

tSU(AUX_SYNC)

tAUXCLKHtAUXCLKL

AUX_PCM_DOUT

tAUXCLK

th(AUX_SYNC)

tPAUXDOUT

MSB MSB-1 LSB

(Companded)

(Linear)

LSB+1

LSB MSB MSB-1 MSB-6 MSB-7 MSB-8 LSB+1 LSB

089-011


without notice.



Table 3-20 AUX_CODEC timing parameters


tAUXSYNC AUX_PCM_SYNC cycle time — 125 — µs a

a This value assumes that CODEC_CTL is not being used to override the CDMA CODEC clock and sync operation.

tAUXSYNCA AUX_PCM_SYNC “asserted” time 62.4 62.5 — µs a

tAUXSYNCD AUX_PCM_SYNC “deasserted” time 62.4 62.5 — µs a

tAUXCLK AUX_PCM_CLK cycle time — 7.8 — µs a

tAUXCLKH AUX_PCM_CLK high time 3.8 3.9 — µs a

tAUXCLKL AUX_PCM_CLK low time 3.8 3.9 — µs a

tSU(AUX_SYNC) AUX_PCM_SYNC setup time to AUX_PCM_CLK rising

1.95 — — µs

tH(AUX_SYNC) AUX_PCM_SYNC hold time after AUX_PCM_CLK rising

1.95 — — µs

tSU(AUX_DIN) AUX_PCM_DIN setup time to AUX_PCM_CLK falling

70 — — ns

tH(AUX_DIN) AUX_PCM_DIN hold time after AUX_PCM_CLK falling

20 — — ns

tPAUXDOUT Propagation delay from AUX_PCM_CLK rising to AUX_PCM_DOUT valid

— — 50 ns


without notice.


NOT
3.2.5 Native mode microprocessor timing

Figure 3-11 Native mode write timing

Table 3-21 Native mode write timing


tAVWR Address valid to address invalid 2T + WT – 1 — ns a

a For the given chip select (CS_N) the variable ‘W’ corresponds to the following control register bits.CS_N ‘W’ (write)ROM_CS1_N (ROM_HWORD_WAIT –1) + ROM_WR_CONTROM_CS2_N (ROM2_HWORD_WAIT –1) + ROM2_WR_CONTRAM_CS1_N (RAM_HWORD_WAIT –1) + RAM_WR_CONTRAM_CS2_N (RAM2_HWORD_WAIT –1) + RAM2_WR_CONT

tCSVWR Chip select active 2T + WT – 1 — ns a

tDSUWR Write data setup (0.5T – 5) + WT — ns

tDHWR Write data hold 0 T ns b

b Weak Keepers are active after the rising edge of WR_N. The external circuit must have less than Cload of 80 pF and no more than 45 uA of leakage current for tDHWR to be valid.

tAWR Address valid to write active 0.5T – 1 — ns c

c This is the minimum separation between Address valid or Chip Select valid and the start of WR_N. WR_N is clocked by the rising edge of MCLK.

tCSWR Chip select active to write active 0.5T — ns c

tWR Write active (0.5T – 4) + WT — ns a

T

tAVWR

tCSVWR

tWR

tDHWR

MCLK

A[22:0]

HWR_NLWR_N

WR_N

D[15:0]

CS_NLB_N UB_N

tDSUWR

tAWRtCSWR

089-012


without notice.



Figure 3-12 Native mode read access, non-instruction fetch

Figure 3-13 Native mode read access, instruction fetch

CS_NLB_N UB_N

T

tAVRD

tCSVRD

tRD

tACSDV

tRDDV tRDH

MCLK

A[22:0]

RD_N

D[15:0]

089-013

T

tAVRD

tCSVRD

tRD

tACSDV

tRDDV tRDH

MCLK

A[22:0]

RD_N

D[15:0]

CS_NLB_N UB_N

089-014


without notice.


NOT
Table 3-22 Native mode read timing


tAVRDI Address valid to address invalid for instruction fetch

T + WT — ns a

a For the given chip select (CS_N) the variable ‘W’ corresponds to the following control register bits.CS_N ‘W’ (read)(ROM_HWORD_WAIT –1) + ROM_RD_CONT(ROM2_HWORD_WAIT –1) + ROM2_RD_CONT(RAM_HWORD_WAIT –1) + RAM_RD_CONT(RAM2_HWORD_WAIT –1) + RAM2_RD_CONT

tAVRD Address valid to address invalid for non-instruction fetch

2T + WT — ns a

tCSVRD Chip select active (T – 1) + WT — ns a

tRDH Read data hold 0 — ns

tRD Read active 0.5T + WT — ns a

tRDDV Read Active to data valid (0.5T -15) + WT — ns

tACSDV Address and chip select active to data valid (T - 20) + WT — ns


without notice.



3.2.6 Bus sizer timing

Figure 3-14 Bus sizer write timing with x16 sram

TMCLK

A[22:2]

A1

LB_N

tABSWR

tBSWR1

tDHBSWR

HWR_NLWR_N

WR_N

D[15:0]

RAM_CS_N

tDSBSWR1

tAWR

tBSWRH

tDSBSWR2

tDHBSWR

tBSWR2

tDWHR

UB_N

089-015


without notice.


NOT
Table 3-23 Bus sizer write timing requirements


tBSWR1 Pulse width of first write active (0.5T – 3) + WT — ns a

a For the given chip select (CS_N) the variable ‘W’ corresponds to the following control register bits.CS_N ‘W’ (write)ROM_CS1_N (ROM_HWORD_WAIT –1) + ROM_WR_CONTROM_CS2_N (ROM2_HWORD_WAIT –1) + ROM2_WR_CONTRAM_CS1_N (RAM_HWORD_WAIT –1) + RAM_WR_CONTRAM_CS2_N (RAM2_HWORD_WAIT –1) + RAM2_WR_CONT

tBSWR2 Pulse width of second, and/or third, and/or fourth write active

(0.5T – 4) + VT — ns b

b For the given chip select (CS_N) the variable ‘v’ corresponds to the following control register bits.CS_N ‘v’ (read)ROM_CS1_N ROM_HWORD_WAIT –1ROM_CS2_N ROM2_HWORD_WAIT –1RAM_CS1_N RAM_HWORD_WAIT –1RAM_CS2_N RAM2_HWORD_WAIT –1

tBSWRH Pulse width of write inactive between bus-sized writes

— 1.5T ns

tAWR Address valid to first write active 0.5T – 1 — ns

tABSWR Address[1:0] valid to second, and/or third, and/or fourth write active

0.5T – 2 — ns

tDSUBSWR1 Bus-sized write data setup for first write (0.5T – 4) + WT — ns a

tDSUBSWR2 Bus-sized write data setup for second, and/or third, and/or fourth write

(0.5T – 4) + VT — ns b

tDHBSWR Bus-sized write data hold last cycle 0 — ns


without notice.



Figure 3-15 Bus sizer read timing non-inst with x16 sram

Table 3-24 Bus sizer read timing requirements


tACSDV Address and chip select active to data valid, first read

(T – 20) + WT — ns a

a For the given chip select (CS_N) the variable ‘W’ corresponds to the following control register bits.CS_N ‘W’ (write)ROM_CS1_N (ROM_HWORD_WAIT –1) + ROM_RD_CONTROM_CS2_N (ROM2_HWORD_WAIT –1) + ROM2_RD_CONTRAM_CS1_N (RAM_HWORD_WAIT –1) + RAM_RD_CONTRAM_CS2_N (RAM2_HWORD_WAIT –1) + RAM2_RD_CONT

tACSDV2 Address and chip select active to data valid, second, and/or third, and/or fourth read

(T – 20) + VT — ns b

b For the given chip select (CS_N) the variable ‘V’ corresponds to the following control register bits.CS_N ‘V’ (read)ROM_CS1_N ROM_HWORD_WAIT –1ROM_CS2_N ROM2_HWORD_WAIT –1RAM_CS1_N RAM_HWORD_WAIT –1RAM_CS2_N RAM2_HWORD_WAIT –1

tRDDV Read Active to data valid (0.5T -15) + WT — ns

089-016

TMCLK

A[22:2]

A1

LB_N

tRDDV

RD_N

D[15:0]

RAM_CS_N

tACSDV

tACSDV2 tACSDV2tACSDV2

tRDH

UB_N


without notice.


NOT
3.2.7 LCD timing

Figure 3-16 LCD timing

T

MCLK

(internal)

A[22:0]

WR_N

Write Data d[15:0]

RD_N

Read Data D[15:0]

LCD_CS_N

LCD_EN

tLCDES tLCDEHI tLCDEH

tRDS tRDH

tWRS tWRH

089-017


without notice.



Table 3-25 LCD_EN timing


tLCDES LCD_CS_N active to LCD_EN active

kT - 0 — ns a

a The variables ‘k’, ‘l’, and ‘n’ correspond to the control register bits LCD_CTL:LCD_E_SETUP, LCD_CTL:LCD_E_HIGH, and LCD_CTL:LCD_WAIT.

tLCDEHI Pulse width of LCD_EN active lT — ns

tLCDEH LCD_EN inactive to LCD_CS_N inactive, write access

2T + nT – (kT + lT) – 5 — ns

tLCDEHR LCD_EN inactive to LCD_CS_N inactive, read access

T + nT – (kT + lT) – 5 — ns

tRDS Read data setup 15 — ns

tRDH Read data hold 0 — ns

tWRS Write data setup to LCD_EN inactive

(kT + lT) – (0.5T + 5) — ns

tWRH Write data hold from LCD_EN inactive

(T + nT) – (kT + lT) – 5 — ns


without notice.


NOT
3.2.8 JTAG timing

Figure 3-17 JTAG interface timing

Table 3-26 JTAG interface timing

Parameter Description Min Typical Max Units

tTCKCY TCK period 100 — — ns

tTCKH TCK pulse width high 40 — — ns

tTCKL TCK pulse width low 40 — — ns

tSUTMS TMS Input Set-up Time 25 — — ns

tHTMS TMS Input Hold Time 25 — — ns

tSUTDI TDI Input Set-up Time 25 — — ns

tHTDI TDI Input Hold Time 25 — — ns

tDO TDO Data Output Delay — — 70 ns

TDI

TCK

TMS

t DO

t TCKH t TCKL

t TCKCY

TDO

t SUTMS t HTMS

t SUTDI t HTDI

089-019


without notice.




without notice.

4 Interface Descriptions

4.1 OverviewThis chapter covers information needed to design the MSM6000 into a subscriber unit application. In addition, this chapter describes some of the internal blocks of the device necessary for complete understanding of the various interfaces. This chapter discusses the interfaces to the major blocks of the MSM6000 as shown in Figure 4-1. These blocks include:

! ARM microprocessor and memory interface

! RF interface

! Baseband interface to CDMA and digital FM processing

! Serial bus interface

! Audio front end

! User and mode select interfaces

! JTAG interface


NOTE Specifications listed in this chapter are target specifications for the MSM6050 device and are subject to change without notice.

Interface Descriptions MSM6000™ Device Specification

Figure 4-1 MSM6000 functional block diagram

1 2 3

7 8 94 5 6

* 0 #

PowerAmplifier

PeripheralCircuits

R-UIM

PLL

RFInterface

UART 1

UART 2 / R-UIM

ARM7TDMI

IntegratedVoice

CODEC

GeneralPurposeInterface

SBI

MSM6000Mobile Station Modem

Antenna

General-Purpose Interface Bus

External Mode Selection

RINGER

Keypad

19.2 MHz

Microprocessor BusAddress/Data

Digital Test Bus

MODE Select

Interface

CDMAProcessor

ANSI/IEEE 1149.1A-1993JTAG Interface

HK ADC

Voltage Regulator

PM6000PM6050

RxADCs

RFR6000

RFL6000

RFT6100

VCTCXO

RF Controls

Duplexer

TXDACs Vocoder

EVRCQDSP2000

PCConnectivity

Test/DebugSystem

DFMProcessor

089-000

AUX_

SBI



MSM6000™ Device Specification Interface Descriptions

4.1.1 Organization of this chapter

Since the MSM6000 is the central interface device of the subscriber unit, it sends and receives information to and from most of the other internal components of the phone. This chapter discusses the interfaces to peripheral devices supported by the MSM6000. The sections of this chapter are:

! Section 4.1 Overview

! Section 4.2 The MSM6000 Mobile Station Modem ASIC overview

! Section 4.3 RF interface

! Section 4.4 Audio front end

! Section 4.5 ARM microprocessor and peripherals

! Section 4.6 Mode select and emulation considerations

! Section 4.7 General-purpose interface (GPIO_INT)

! Section 4.8 UART, R-UIM

! Section 4.9 User interface

! Section 4.10 GPADC functional description

! Section 4.11 Clock regimes

! Section 4.12 JTAG interface





4.2 The MSM6000 Mobile Station Modem ASIC overview

4.2.1 CDMA subsystem

The CDMA subsystem performs the digital IS-95A/B and IS-2000 signal processing. Its components include:

! Searcher Engine

! Demodulating Fingers

! Combining block

! Frame Deinterleaver

! Viterbi Decoder

! Reverse Link Subsystem

On the forward-link traffic channel the CDMA Subsystem searches, demodulates, decodes incoming Pilot, Sync, Paging, and Traffic Channel information. It extracts low bit-rate packet data from the forward-link traffic channel and sends the packet data to the vocoder for processing. For the reverse link, the CDMA subsystem processes the packet data from the vocoder and modulates the reverse traffic channel.

4.2.2 Digital FM subsystem

The MSM6000 also supports Advanced Mobile Phone System (AMPS) cellular operations. The Digital FM (DFM) processor performs digital signal processing operations for the Mobile Station using the AMPS cellular standard.

4.2.3 RF interface

The RF Interface communicates with the Mobile Station’s external RF, analog baseband circuits. Signals to these circuits control signal gain in the Rx and Tx signal path, control DC baseband offset errors, and maintain the system’s frequency reference.




4.2.4 Audio front end

CODEC

The MSM6000 integrates a voice band audio CODEC into the Mobile Station Modem (MSM). The CODEC supports two differential microphone inputs, one differential earphone output, one single-ended earphone output, and a differential analog auxiliary interface. The CODEC integrates the microphone and earphone amplifiers into the MSM6000, reducing the external component count to just a few passive components. The microphone (Tx) audio path consists of a two-stage amplifier with the gain of the second stage set externally. The Rx/Tx paths are designed to meet the ITU-G.712 requirements for digital transmission systems.

Vocoder subsystem

The MSM6000’s QDSP2000 supports an EVRC vocoder along with DFM baseband audio processing. In addition, the QDSP2000 has modules to support the following audio functions; DTMF tone generation, DTMF tone detection, Tx/Rx volume controls, EarSeal Echo Canceller (ESEC), Noise Suppression (NS), Supervisory Audio Tone (SAT) transponding in DFM mode, and programmable, 13-tap, Type-I, FIR, Tx/Rx compensation filters. The MSM6000’s integrated ARM7TDMI processor downloads the firmware into the QDSP2000 and configures QDSP2000 to support the desired functionality.

4.2.5 ARM microprocessor subsystem

The MSM6000 uses an embedded ARM7TDMI microprocessor. The ARM7TDMI microprocessor, through the system software, controls most of the functionality for the Mobile Station Modem, including control of the external peripherals such as the keypad, LCD display, RAM, ROM, and EEPROM devices. Through a generic Serial Bus Interface (SBI) the ARM7TDMI configures and controls the functionality of the RFT6100, RFR6000, RFL6000, and PM6000/6050 ICs.

4.2.6 UART

The MSM6000 employs two identical UARTs. UART1 has dedicated pins while UART2 shares multiplexed pins with the Auxiliary PCM CODEC interface.

4.2.7 Serial bus interface

The MSM6000’s Serial Bus interface is specifically designed to be a quick, low pin count control protocol for QUALCOMM’s RFT6100, RFR6000, RFL6000, and PM6000/6050 ICs. Using the Serial Bus Interface, these ICs can be configured for different operating modes and configured for minimum power consumption, extending battery life in standby mode.





4.2.8 User interface

The MSM6000 User Interface comprises digital connections to the subscriber unit ringer transducer, keypad, and LCD display.

4.2.9 General-purpose interface bus

The MSM6000 has general-purpose bidirectional input/output pins that double as general-purpose interrupt inputs. Some of the GPIO_INT pins have alternate functions supported on them. The alternate functions include additional RAM, ROM, general-purpose chip selects, parallel LCD interface, and a UART interface. The function of these pins is documented in the various software releases.

4.2.10 Mode select and JTAG interfaces

The MODE pins to the MSM6000 determine overall operating mode of the ASIC. The options under the control of the MODE inputs are Native mode which is the normal subscriber unit operation and ICE Mode in which the on-chip ARM microprocessor is disabled, allowing off-chip emulation by the ICE unit.

The MSM6000 complies with the ANSI/IEEE 1149.1A-1993 feature list. The JTAG interface can be used to test digital interconnects between devices within the mobile station during manufacture.




4.3 RF interfacePrecise power control of each mobile station is vital for CDMA system performance. It is the mobile station’s responsibility to accurately estimate the power spectral density within the 1.2288 MHz bandwidth of the frequency channel used for CDMA demodulation. In this section, the power spectral density measurement is called the mean Rx power estimation, or the received signal strength indication (RSSI). The mobile station needs to estimate mean Rx power because it uses the RSSI to determine its mean Tx output power. The mean Tx output power of the Reverse Traffic Channel is specified by the following equation:

mean Tx output power (dBm) = – mean Rx input power (dBm)+ offset power (–73 for cellular, –76 for PCS)+ the sum of all access probe corrections+ the sum of all closed loop power control corrections+ a few other control parameters

The CDMA Tx AGC block controls the mobile station’s mean Tx output power, as specified by the equation shown above. The mean Rx input power used by the Tx AGC block, is a filtered version of the RSSI created by the Rx AGC block. The offset power is determined by linearizer calibration procedures and corresponding software interpretation. Closed loop power control corrections are summed by the Tx AGC block circuits.

The Tx AGC block also controls the operating point of a multistate (high efficiency) power amplifier (PA) circuit. The CDMA Tx AGC block supports switching between up to four different PA operating points with programmable levels and temporal hysteresis.

Figure 4-2 shows the high-level functional block diagram for the MSM6000 RF interface pins, when used with radioOne™ RF ICs. These figures are only applicable to the functionality of the MSM6000 RF interface pins. All radioOne™ ICs are highly integrated and fulfill specific functions. The chipset includes:

" RFL6000 Dual LNA IC

" RFR6000 RF-to-Baseband Receiver IC

" RFT6100 Baseband-to-RF Transmitter IC

" PM60XX Power Management IC

" MSM6000 Digital Processor IC

The RFL6000 IC is a standalone chip with two Low Noise Amplifiers (LNAs) which serves as front end low noise amplifiers prior to the RFR6000 chip and the MSM6000. It supports all modes of operation.

The RFR6000 IC provides the Zero-IF receiver signal path, from RF to analog baseband, for multi-band, multi-mode handsets

The RFT6100 is a Baseband-to-RF transmitter IC. All radioOne™ ICs are highly integrated and fulfill specific functions. Functional requirements are partitioned between the ICs to yield complete, optimal transceiver implementations.





The PM60xx is a custom mixed signal device containing all of the circuitry required to support the battery charging/monitoring and voltage regulation for a CDMA/AMPS or other mobile standard handset. It also contains extensive support for user interface devices.

Figure 4-2 MSM6000 interfaces

MSM6000

VDD_A

TCXO_EN

RINGER

PM_INT_0

PS_HOLD

SLEEP_XTAL_IN

RESIN_N

I_OUT

I_OUT_N

severalpossible pins

T3

T7

R6

C11

D12

C13

G15

G14

Q_OUTF14

Q_OUT_NF15

TRK_LO_ADJD15

DAC_REFG17

PM6000or

PM6050

SPKR_IN/RNG_TONE

PON_RESETB

OUT

VCC

VCTL

GND

VCTCXO

RFT6100

TX_I

TX_IN

TX_QN

TX_Q

35

36

34

33

37

200pF

200pF

RFL6000

RFR6000

FM_STEP6

RX_QP

RX_QM

RX_IM

RX_IP

34

33

30

31

VTUN

VCC

RFOUT

GNDRF_VCO

EN

DAC_REF

TCXO_EN

MSM_INTERUPTB

PS_HOLD

SLEEP_CLK

100

0.68 uF

TCXO_IN

10k

VREG_MSMP

200k

TCXOE17

TCXO_OUT

KBDPWR_ON detect keypadactivity

JTAG_ON

JTAG_RESIN_N

SB

DT

SB

CK

SB

ST

SB

DT

SB

CK

SB

ST

J15K16J14

TX_AGC_ADJE15 30

VCONTROL1k

4700 pF

1k

.01 uF

SYNTH_LOCKF16 6

LOCK

TX_ONB12 2

TX_ON

10kVREG_MSMP

SB

DT

SB

CK

SB

ST

4 3 5

SB

DT

SB

CK

SB

ST

10 7 8

D16FM_LNA_RANGE

5.76k

5.76k

SB

DT

SB

CK

SB

ST

262524

N14I_IP

P16I_IN

M14Q_IP

N16Q_IN

A12EXT_VCO_EN

1k

0.1 uF

.01 uF

CellBPF

CellularPA

dualPCSBPF

PA_ON1

TX_PCS_HI

TX_PCS_LOW

J17

B11

D10

PA_R1

PA_ON0

E16

H16

RF_OUT RF_IN

VMODE

PA_ON

10k

VREG_MSMP

PCSPA

SW

CT

L1

CT

L2RF_OUT RF_IN

VMODE

PA_ON

47 pF

47 pF

T4AUX_SBI_ST

U3AUX_SBI_CK

A4AUX_SBI_DT

AUX_SBI_ST

AUX_SBI_CK

AUX_SBI_DT

100

0.01 uF

optionalsecond pole

089-040

*VREG_MSMP in the output of theMSM PAD regulator on the PM device

10k

VREG_MSMP




4.3.1 Transmit signal paths The MSM provides I and Q differential baseband signals (FM or CDMA) to the RFT6100 IC via the proprietary analog interface. The analog input signals are amplified and applied to the upconverter mixers.

Q_OUT Transmit quadrature-phase analog input, differential positive

Q_OUT_N Transmit quadrature-phase analog input, differential negative

I_OUT Transmit in-phase analog input, differential positive

I_OUT_N Transmit in-phase analog input, differential negative

DAC_REF Reference output to MSM Tx data DACs

TX_ON Puncture control from MSM: H = Tx on, L = Tx off

EXT_VCO_EN represents a pin used to control the RX power state of the VCO oscillator. If this pin is high, the VCO is enabled. If this pin is low, the VCO is disabled. The VCO must be disabled during GPS acquisition.

TX_AGC_ADJ is a PDM output pin used to control the attenuation (-gain in dB) of the Tx AGC amplifier. This signal is used as part of the CDMA and Digital FM Tx AGC loop.

PA_ON[1:0] are used to control the power state of the power amplifier (PA). PA_ON transitions high (active), a programmable amount of time before the beginning of a transmission. PA_ON remains high a short time after the end of transmission. PA_ON0 is used for cellular band, and PA_ON1 is used for PCS band.

PA_R[1:0] are pins that can be used to control the operating point of the PA circuit.

TX_PCS_HIGH is a control SPDT (single pole double throw) switch used to choose PCS high band (PCS channel > 600). TX_PCS_HI complements TX_PCS_LOW. Only used for US PCS handsets with split band TX SAWs.

TX_PCS_LOW is a control SPDT (single pole double throw) switch used to choose PCS low band (PCS channel < = 600). TX_PCS_LOW complements TX_PCS_HI. Only used for US PCS handsets with split band TX SAWs.





4.3.2 Receive signal paths

The RFL6000 outputs drive the RF ports of the quadrature RFR6000 RF-to-baseband downconverters (a dedicated downconverter for each band). The downconverted baseband outputs are multiplexed and routed to lowpass filters. The filter outputs are buffered and passed on to the MSM for further processing.

I_IN Receiver in-phase analog output (negative), a differential signal that complements I_IP.

I_IP Receiver in-phase analog output (positive), a differential signal that complements I_IN.

Q_IN Receiver quadrature analog output (negative), a differential signal that complements Q_IP.

Q_IP Receiver quadrature analog output (positive), a differential signal that complements Q_IN.

FM_LNA_RANGE is an open-drain digital output produced by the receive AGC subsystem. The LNA_RANGE_FM is designed to change states at programmable thresholds of receive signal strength in FM mode. This allows the subscriber unit to alter the receive signal path by bypassing or enabling the receive RF components at these thresholds. For the MSM6000, this pin requires a pull-up resistor to be connected to RFL6000 FM_STEP input.

TCXO is the primary 19.2MHz clock source used by various blocks of the MSM6000 device, such as the ARM7TDMI ringer, UARTs, general-purpose PDMs, and the Digital FM circuits. TCXO can be used as a Vocoder clock source for EVRC support. TCXO is also used by the MSM6000 device to produce CHIPX8, and CHIPX16.

4.3.3 Others

TCXO is the primary 19.2MHz clock source used by various blocks of the MSM6000 device, such as the ARM7TDMI, ringer, UARTs, general-purpose PDMs, and the Digital FM circuits. TCXO can be used as a Vocoder clock source for EVRC support. TCXO is also used by the MSM6000 device to produce CHIPX8 and CHIPX16.

TRK_LO_ADJ is a PDM output from the frequency tracking circuit which adjusts the subscriber frequencies. TRK_LO_ADJ is a PDM output from the frequency tracking subsystem which adjusts the subscriber units VCTCXO.

SYNTH_LOCK is an input pin that indicates the status of the Tx and Rx synthesizers. If the MSM6000 SYNTH_LOCK pin is high, Tx synthesizers must be in-lock. If a Tx synthesizer is out-of-lock, SYNTH_LOCK must be low to disable the power amplifier. LOCK is an open-drain output pin from the RFT6100, connect SYNTH_LOCK and LOCK directly together. Also connect a resistor from the SYNTH_LOCK to the MSM6000 device’s MSM PAD (VDD_P).




4.3.4 Digital interface

All control and status commands are communicated through the MSM-compatible 3-line Serial Bus Interface (SBI), allowing efficient initialization, control of device operating modes and parameters, verification of programmed parameters, and status reports. The MSM’s SBI controller is the Master while the RF ICs are the Slaves.

SBST Serial Bus Interface (SBI) Strobe

SBCK SBI Clock

SBDT SBI Data.

AUX_SBI_ST Auxiliary SBI bus for RFT6100 serial bus strobe

AUX_SBI_CKAuxiliary SBI bus for RFT6100 serial clock

AUX_SBI_DT Auxiliary SBI bus for RFT6100 serial bus data.

Please refer to the radioOne Zero-IF Chipset Design Guidelines document, 93-V2685-3, for further discussion on the MSM6000 RF Interface.





4.4 Audio front end

4.4.1 Functionality

The MSM6000’s QDSP2000 contains two main sections, an audio front end and a modem module. The modem module is responsible for the CDMA vocoders and the DFM audio processing. The audio front end provides the codec interface, Auxiliary PCM path selection, Auxiliary PCM format conversion, echo cancellation, noise suppression, Tx/Rx 13-tap FIR filters, Tx/Rx automatic gain control modules and Tx/Rx DTMF generations.

Figure 4-3 Functional block diagram

4.4.1.1 Modem functionality

4.4.1.1.1 Vocoder function

The vocoding function consists of an encoder and a decoder. The vocoder module operates in IS-127 EVRC. The interface is designed so that vocoder formats can change from mode to mode without the burden of downloading new firmware.

4.4.1.1.2 Digital FM audio processor

The DFM module implements the base-band audio processing between 8 kHz sampling domain and 20 kHz sampling domain.

Earphone

13 bit D/A

HPF &SLOPE X+ -

- +

External Gain(+18dB Typ.)

MIC

INN

MIC

INP

MIC_AMP2_BYP

MIC

FB

N

MIC

FB

P

+ -- +

Microphone

MIC1P

MIC1N

AUXIP

AUXIN

MIC2P

MIC2N

MICSEL#01 10 11

MIC

OU

TN

MIC

OU

TP

MIC_AMP1_GAIN00 -2dB01 +6dB10 +8dB11 +16dB

EAR1ON

EAR1OP

EAR2

AUXON

AUXOP+ -- +

-+

+ -- +

EAR_AMP_SEL#xx1 x1x 1xx

35mW max.*

8.8 mW max.*

1.87mW max.*

CodecTxGain**

TX_HPF_DIS_N

TX_SLOPE_FILT_DIS_N

CodecSTGain**

PCMIF

PCMIF

AUX_PCM InterfacePCM Interface

X

NS &AAGC

Rx FIRX

XEVRCDFM

Encoder

TxVolume**

RxVolume**

nsSwitch TxPcmFilt

RxPcmFiltecSwitchecMode

DTMFGeneration

DTMFDetection

DTMF_RX_GAIN

DTMF_TX_GAIN

ESECor

AEC

X

CodecRxGain**

X HPF

RX_HPF_DIS_N

Codec Rx

Codec Tx

Encoder

Decoder

EVRCDFM

odeDec r

Tx FIR

X

NES(DFMonly)

13 bit A/D

+ AAGC

AUDIOLOOPBACK++

PC

M_LO

OP

BA

CK

PACKETLOOPBACK++

* Amplifiers are powered downwhen not selected

# Setting the parameter to "000"will de-select all inputs/outputs

013-043




4.4.1.2 Audio functionality

4.4.1.2.1 CODEC control

The audio front end supports commands for configuration of the MSM6000’s Codec. Microphone and earphone selection along with the filter and gain selection can be accessed through the audio front end commands. It is recommended that the audio front end handle the Codec configuration.

4.4.1.2.2 PCM format conversion and auxiliary interface

The Audio front end supports the conversion of the incoming Auxiliary PCM data from µ-law or A-law, into linear PCM data. Outgoing linear PCM samples from the audio front end can be converted to µ-law or A-Law PCM formats. The audio front end supports optional incoming or outgoing PCM data padding.

4.4.1.2.3 Echo canceller

The MSM6000 provides an echo cancellation module to support handset and headset. An Ear-Seal Echo Canceller (ESEC) is used for the handset and headset applications. For all applications, the echo cancellers are designed to suppress the landside echo by either muting or actively filtering the Tx audio samples.

4.4.1.2.4 Noise suppressor

The Noise Suppression (NS) algorithm operates on the Tx audio path prior to the encoding stage of the vocoder. The Noise Suppressor (NS) is designed to reduce the background noise level while keeping the detected speech pattern at the nominal level.

4.4.1.2.5 TX/RX 13-tap FIR filters

A type-I 13-tap FIR (finite impulse response) filter is supported on the Tx and the Rx paths. Both filters are software programmable and can be reconfigured during vocoder or DFM operation. Each filter consists of 7 coefficients with the outside taps, h[0] and h[12], h[1] and h[11], h[2] and h[10], h[3] and h[9], h[4] and h[8], and h[5] and h[7], using the same coefficient value. The Rx and Tx filters are intended to equalize the frequency response of the microphone (Tx), the earphone (Rx), and the frequency characteristics of the mechanical housing of the subscriber unit.

4.4.1.2.6 TX/RX volume controls

The Tx and Rx audio path have separate volume controls to adjust the loudness levels on the Tx and Rx audio paths. The Rx and Tx volume controls are programmable multipliers operating in the linear domain. Unity gain on the Tx and Rx volume controls is the programmed value 0x4000.

4.4.1.2.7 TX/RX AGC

Tx and Rx Automatic Gain Control (AGC) monitor the respective audio paths and adjusts the gain to compensate for audio loudness changes that occur.





4.4.1.2.8 RX AVC

The Rx Automatic Volume Control (AVC) monitors the Tx path for changes in the microphone input and adjusts the volume of the Rx (earphone) audio path in order to compensate for background noise on the Tx (microphone) path.

4.4.1.2.9 TX/RX DTMF generation

DTMF generation is completely programmable via DTMF Tone Request command that configures the frequency, volume, and duration of the DTMF tones. The generated tones replace the audio samples on the Tx path prior to the encoder and replace the decoded audio samples on the Rx path. The Vocoder or DFM modules continue to operate while DTMF tones are being generated. This ensures that the speech is reconstructed properly when the tones are discontinued. The DTMF Tone Request command contains the DTMF_DURATION, DTMF_HIGH_FREQ, DTMF_LOW_FREQ, DTMF_TX_GAIN and DTMF_RX_GAIN parameters. The duration of the active tone pair is controlled by DTMF_DURATION, which has a 5 [msec] resolution. DTMF_HIGH_FREQ and DTMF_LOW_FREQ define high and low frequencies of the tone pairs. DTMF_RX_GAIN and DTMF_TX_GAIN control the volume or loudness of the tone pairs. Table 4-1 lists the programming values for DTMF generation. These values are used when programming DTMF_HIGH_FREQ and DTMF_Table 4-1.

4.4.1.2.10 TX/RX DTMF detection

The Tx DTMF detection occurs after the echo canceller on the Tx path. The Rx DTMF detection module occurs at the end of the Rx audio path.

4.4.1.2.11 Automatic sample slipping

When the system is configured in the automatic sample slipping mode, the QDSP2000 monitors the offset between the system clock (CDMA or DFM) and the PCM clock, from the CODEC and AUX PCM interface. When these two clocks skew, the sample slipping detection algorithm adjusts the corresponding PCM sample pointers to re-synchronize these clocks.

The sample slipping detection algorithm can be turned off during an “outside of a call” operation mode (when there is no over-the-air timing signal). The MSM6000 must generate an artificial software vocoder frame reference strobe (VFR) in this configuration.

Table 4-1 DTMF frequencies and programmed values

DTMF Low (Hz) Value (hex) DTMF High

(Hz) Value (hex)

697 0x36AE 1209 0x2546

770 0x34AE 1336 0x1FE7

852 0x323B 1477 0x1992

941 0x2F55 1633 0x1234




4.4.2 Codec

The MSM6000 integrates an audio voiceband Codec into the Mobile Station Modem. The integrated Codec contains all of the required conversion and amplification stages for the audio front end. The Codec operates as a 13-bit linear Codec with the transmit (Tx) and receive (Rx) filters designed to meet ITU-T G.712 requirements. The Codec includes a programmable sidetone path for summing a portion of the Tx audio into the Rx path.

An on-chip Voltage/Current reference is provided to generate the precise voltages and currents required by the Codec. This circuit requires a single capacitor of 0.1 uF to be connected between the CCOMP and GND_RET pins (see Figure 4-4). The on-chip Voltage reference also provides a microphone bias voltage required for electret condenser microphones typically used in handset applications. The MICBIAS output pin is designed to provide 1.8 Volts DC while delivering as much as 1 mA of current.

The Codec interface includes the amplification stages for both the microphone and earphone. The interface supports two differential microphone inputs and a differential auxiliary input, each of which can be configured as single-ended if desired. In addition, the interface supports one differential earphone output, one single-ended earphone output, and one differential auxiliary output.

The Codec is configured through the QDSP2000 Command types and is not directly controlled by the microprocessor. The Codec Configuration command is sent to the QDSP2000 and then the QDSP2000 executes the command and configures the Codec.

4.4.2.1 Transmit path processing

The microphone interface consists of two differential microphone inputs, one differential auxiliary input and a two-stage audio amplifier. The microphone input is selected by the Codec Configuration command (MIC_SEL). Only one of the inputs is active at any given time and the other inputs are powered down.

The gain for the first stage amplifier can be set to either –2 db, +6 dB, +8 dB or +16 dB by the Codec Configuration command (MIC_AMP1_GAIN). The outputs of the first stage are the output pins MICOUTP and MICOUTN.

The gain of the second stage amplifier is set externally. Additional filtering for the microphone can be designed into the external gain circuit in order to enhance the audio performance of the transmit channel. The second stage amplifier can also be bypassed internally by setting Codec Configuration command (MIC_AMP2_BYP). The MICINP and MICINN are the inputs to the second stage amplifier and MICFBN and MICFBP are the feedback outputs. Figure 4-4 shows a typical external circuit with a gain of 18 dB. In addition to the gain stage, the circuit contains a highpass filter that suppresses low frequencies.





Figure 4-5 Equivalent circuit for external filter network

The second stage mic amplifier (MICAMP2) is configured into a gain and filter stage. This is a high pass 2nd order Butterworth filter response. See Figure 4-5.

Figure 4-4 Typical external filter network

MICOUTN

MICINP

MICFBN

MICBIAS

CCOMP

GND_RET

Positive terminalof microphone

0.1 uF

GND

180K Ω

10K Ω12.3 nF

0.1 uF

MICOUTP

MICINN

MICFBP

180K Ω

12.3 nF 10K Ω

0.1 uF0.1 uF

0.1 uF

500K Ω

2.2K Ω

013-044

013-004

500K

C1=0.1uF

C1=0.1uF

MICOUTP

MICOUTN

C2=0.1uF

C2=0.1uF

MICINN

MICINP

-

+

C3=12.3nF

C3=12.3nF

MICFBP

MICFBN

R2=180K

R2=180K

R1=10K

R1=10K




Use the following equations to determine the values to R1, R2, C1, C2 and C3.

Figure 4-6 Equivalent circuit for MICAMP2

| Ho | = C1 / C3 => Eq1

R1 = | Ho | / [2*π*fn*Q*C*2* | Ho | +1] where C = C1 = C2 => Eq2

R2 = (Q*2* | Ho | +1) / (2*π*fn*C) => Eq3

For example:

If Q = 0.707

fn = 105.5 Hz

|Ho| = 8.13 = 18.2dB

C = C1 = C2 = 0.1uF

Using Eq1: C3 = 12.3nF

Using Eq2: R1 = 10K ohm

Using Eq3: R2 = 180K ohm

The transmit data from the microphone input is digitally filtered with an ITU G.712 compliant filter. The filter attenuates the input signals outside the 3400 Hz baseband and decimates the data rate to 8 kHz.

The MSM6000 has two optional digital filters on the Tx path prior to the vocoder, a slope filter and a highpass filter. The slope filter, Figure 4-7, is designed to provide pre-emphasis for the high

frequency audio prior to the vocoder.

013-005

C1=0.1uF

MICOUTP

C2=0.1uF

MICINN-

C3=12.3nF

MICFBP

R2=180K

R1=10K





Figure 4-7 Slope filter

-150 500 1000 1500 2000 2500 3000 3500 4000

-10

-5

0

5

10G

AIN

(dB

)

Frequency (Hz)013-045




The highpass filter, Figure 4-8, provides at least 30 dB of attenuation below 120 Hz.

Both filters are individually enabled by the Codec configuration command (TX_HPF_DIS_N and TX_SLOPE_FILT_DIS_N).

The Tx audio path contains a programmable gain stage, with a range of +12 dB to –84 dB, after the Analog-to-Digital conversion and prior to the QDSP2000. The QDSP2000 DMA parameter CodecTxGain sets the Tx gain. A programmed value of 0x4000 is unity gain and programmed value of 0x0000 mutes the Tx audio data. The gain calculation for CodecTxGain is:

Gain = 20*LOG(CodecTxGain/16384)

Figure 4-8 Highpass filter

-20

100

-10

0

10

GA

IN (

dB)

Frequency (Hz) 013-046

-30

-40

-50

-60

-70101 102 103 104





4.4.2.2 Receive path processing

The MSM6000 includes the capability of adding a portion of the Tx audio into the receive path. This sidetone is added with a programmable gain stage, with a range of +0 dB to –96 dB, controlled by the QDSP2000 DMA parameter CodecSTGain. A programmed value of 0xFFFF is unity gain and programmed value of 0x0000 mutes the sidetone. The gain calculation for CodecSTGain is:

Gain = 20*LOG(CodecSTGain /16384) -12

A user selectable highpass filter is available for rejection of low frequency noise. This filter provides at least 30 dB of attenuation below 120 Hz. This filter is identical to the Tx highpass filter with the frequency response shown in Figure 4-8. Selection of this filter is accomplished by sending the Codec configuration command (RX_HPF_DIS_N).

The Rx audio path contains a programmable gain stage, with a range of +15 dB to –81 dB, before the audio front end of the QDSP2000 and after to the Digital-to-Analog conversion. The QDSP2000 DMA parameter CodecRxGain sets the Rx gain. A programmed value of 0x2D4F is unity gain and programmed value of 0x0000 mutes the Rx audio data. The gain calculation for CodecRxGain is:

Gain = 20*LOG(CodecRxGain /16384) +3

The receive path is digitally filtered with an ITU G.712 compliant filter. The filter response has a flat passband out to 3400 Hz and offers attenuation of at least 14 dB at 3.98 kHz to allow adequate image rejection.

The receive path can be directed to either one of two earphone amplifiers or the auxiliary output. The outputs earphone1 (EAR1OP, EAR1ON) and Auxiliary out (AUXOP, AUXON) are differential outputs. Earphone2 (EAR2O) is a single-ended output stage designed to drive a headset speaker. Selection of the active amplifier is accomplished by sending the QDSP2000 Codec configuration command (AMP_SEL). The earphone amplifiers that are not selected are disabled and the output is in a high-Z state.




4.4.2.3 Microphone and earphone interface

The MSM6000’s microphone and earphone is designed to interface directly to the handsets microphone and earphone or to the connector of a headset. Figure 4-9 illustrates a typical differential interface used in handset applications. The MICBIAS output pin is designed to provide 1 mA of current at 1.8 Volts DC. The output power for the differential EAR1 output is typically 35 mW for a full-scale +3 dBm0 sine wave into a 32 ohm speaker.

Figure 4-10 is an example of a single-ended microphone and earphone application found in typical headset applications. The output power for the single-ended EAR2 output is typically 8.8 mW for a full-scale +3 dBm0 sine wave into a 32 ohm speaker.

Figure 4-9 Typical handset interface

Figure 4-10 Typical headset application

MIC1PMIC1N

MBIAS

EAR1OPEAR1ON

Differentialmicrophone & earphonefor handset applications

2.2K Ω

0.022 uF

0.022 uF

2.2K Ω

013-047

MIC2P

MIC2N

MBIAS

EAR2

Single-ended microphone &earphone for headset

applications

GND

2.2K Ω

33 uF

+

0.022 uF

0.022 uF

013-048





4.4.2.4 Auxiliary I/O interface

The MSM6000 also provides an analog auxiliary interface for car-kit applications. The output power for the auxiliary output is typically 1.87 mW for a full-scale +3 dBm0 sine wave into a 600 OHM load.

Figure 4-11 Typical analog car kit application

AUXIPAUXINAUXOPAUXON

Differential auxiliary I/Ofor carkit applications

013-049




4.4.3 Vocoder

4.4.3.1 QDSP2000 operation

4.4.3.1.1 Powerup initialization/code downloading

The microprocessor downloads the desired QDSP2000 firmware into the QDSP2000 internal program and data memory through the DMA interface. After the program has been successfully downloaded, the QDSP2000 is initialized into the RESET state by setting (1) DSP_RESET register. The QDSP2000 starts executing.

The QDSP2000 executes the initialization portion of code to set up internal data memory, pointers and states. After the QDSP2000 has finished initializing the internal resources, it stays in the INIT state and waits for the Codec configuration command.

The microprocessor must turn on the Codec clock source prior to the QDSP2000 enabling the Codec. The microprocessor is responsible for enabling the CDMA system clock and/or the DFM clock. The Codec clock and CDMA system clock are required for the EVRC Vocoder operations and the Codec clock and the DFM clock are required for the DFM operation.

4.4.3.1.2 Codec configuration command

The codec configuration command is required to put the QDSP2000 into the IDLE state from the INIT state. The Codec configuration command configures the PCM DMA ports, selects the Codec audio path, initializes the data, and enables the clock to the Codec.

While the QDSP2000 is in the IDLE, DFM or VOCODER state, the Codec is active. Therefore, the microprocessor can request that DTMF generation or detection take place in these states.

4.4.3.1.3 Modem configuration command and timing reacquisition

Once the QDSP2000 is in the IDLE state, the microprocessor must configure the QDSP2000 into either the VOCODER or DFM state. The microprocessor must make sure the firmware is properly downloaded before the modem configuration command is sent. The different modem modes require different configuration offsets due to the different timing requirements.

For the Vocoder modes, the microprocessor sends the vocoder timing command when the QDSP2000 is in IDLE state. After the microprocessor sends the configuration command for the specific vocoder mode, the QDSP2000 initializes the vocoder and other related timing offsets. The vocoding process starts at the next available vocoder frame reference strobe. In the event that there is no over-the-air interface, the microprocessor must generate a fake vocoder frame reference strobe.

For DFM operation, the microprocessor sends the DFM configuration command to put the QDSP2000 into the DFM state from the IDLE state. After the QDSP2000 initializes the DFM module, it looks for the DFM frame reference strobe to initialize sample slipping state machine. After the frame reference strobe is received, the QDSP2000 begins the DFM audio.





4.4.3.1.4 Modem mode switching

Switching from CDMA to FM or FM to CDMA requires the QDSP2000 firmware to conduct modem mode switching.

Mode switching is conducted by stopping the QDSP2000 from executing by changing the modem state to IDLE, then the new modem function command is sent.

Service routines must be written to mute the Rx and Tx paths prior to termination and clearing the encoder and decoder packet buffers prior to initiation. This eliminates the audio pops and clicks that can be generated by incorrect termination or initialization.

4.4.3.1.5 System timing acquisition

A system timing strobe is provided through the QDSP2000 interrupt input. During CDMA operation, this 20 mSec interrupt signal is derived from the CDMA system timing. During DFM operation, this 20 mSec interrupt signal is derived from the DFM interface.

If the QDSP2000 system is operating without the external vocoder frame reference (VFR), the microprocessor is required to generate an artificial vocoder frame reference strobe to set the system timing acquisition.

4.4.3.2 QDSP2000 packet interface

The QDSP2000’s CDMA timing is based on an external 50 Hz, or 20 mSec, vocoder frame reference strobe (VFR) that is provided to the QDSP2000. The QDSP2000 uses the VFR for timing reacquisition and for automatic sample slipping detection. As part of the initialization process, the Vocoder timing command is written. The Vocoder timing command contains three parameters, ENC_FRAME_OFFSET, DEC_FRAME_OFFSET and DEC_INT_ADVANCE. These parameters determine the offsets from the VFR. The encoder and decoder packets are sent to and read from the packet buffers at these offsets. The offset values must be chosen carefully to match the processing time required by the microprocessor, excessive offsets adversely effects the encoding and decoding propagation delays.

4.4.3.2.1 Encoder packet interface

The parameter ENC_FRAME_OFFSET sets the number of PCM samples (0.125 mSec) after the vocoder frame reference strobe (VFR) that the encoded packet is written into the encPacketBuf. The QDSP2000 increments the encPacketReg by 0x0001 to indicate that a new, valid encoder packet is in the encPacketBuf. The QDSP2000 executes a QDSP2000-to-microprocessor interrupt. The interrupt service routine must read the data from encPacketBuf and clear the encPacketReg within the 19 mSec transaction window. If the microprocessor has not completed reading the entire encPacketBuf when the QDSP2000 is ready to send the next encoder packet, the QDSP2000 increments the count in encPacketReg by 0x0001. This mechanism notifies the microprocessor that at least one encoded packet has been overwritten.




ENC_FRAME_OFFSET is the offset, in PCM samples, from the VFR that the ENC_FRAME_TICK is generated. ENC_FRAME_OFFSET represents the earliest time that the service routine can request the encoder packet from the QDSP2000. The QDSP2000 aligns its internal frame and processing so that it finishes encoding the packet before the ENC_FRAME_TICK.

In Figure 4-12, the QDSP_txMargin is the internal processing time required by QDSP2000 for the encoding operation. QDSP_txMargin is a fixed firmware parameter and equals 160 PCM samples minus the processing time (in PCM samples) required to encode a frame. With a faster QDSP2000 clock the processing time goes down and the QDSP_txMargin increases. The parameter Tx_Margin is stored in the DMSS source file “qdspdma.h” as a reference.

From the ENC_FRAME_TICK, the QDSP2000 waits QDSP_txMargin PCM samples before beginning the encoding process allowing the encoder to finish encoding the frame at the ENC_FRAME_TICK. The PCM framing is defined by specifying this timing. The 60/80 samples immediately preceding the ENC_FRAME_TICK + QDSP_txMargin represents the 60/80 sample look-ahead buffer and the 160 samples preceding ENC_FRAME_TICK + QDSP_txMargin are the encoder frame. The EVRC encoder uses 80 samples as the look-ahead buffer. The encoding delay is (160+160+60(80)- QDSP_txMargin) PCM samples plus the delay added by the audio front-end module.

Figure 4-12 Encoder packet transfer timing

VocoderFrame

ReferenceStrobe

ENCFRAMETICK

EncoderInterrupt

QDSP_txMargin

60/80lookahead

Frame A (160 samples)

60/80lookaheadFrame B (160 samples)

60/80lookaheadFrame C (160 samples)

Encoder encodesFrame A

Encoder encodesFrame B

Encoder Delay= (160+160+60/80)-QDSP_txMargin013-050

1 mSec window for the encoder to write andsend the packet. Encoder interrupt isgenerated after the packet data is ready.

Encoder transaction window where CPU can read encoder packet. It is almost 19 mSec wide.

Encoder must finish encoding and send the encoder packet rightbefore the ENC FRAME TICK

ENCFRAMEOFFSET





4.4.3.2.2 Decoder packet interface

The decoder interrupt is an advanced version of the internal frame boundary DEC_FRAME_TICK. The parameter DEC_INT_ADVANCE sets number of PCM samples (0.125 mSec) before the decoder frame boundary that the decoder interrupt is triggered. The DEC_INT_ADVANCE is part of the Vocoder Timing command. The QDSP2000 increments the command register, decPacketReg, by 0x0001 to notify the microprocessor of the decoder interrupt. Microprocessor must write the decoder packet into the decoder packet buffer, and clear decPacketReg. If the decPacketReg is other than 0x0000, the QDSP2000 executes an erasure process and increments decPacketReg to notify the microprocessor that a transaction window is missed.

The QDSP2000 decoder uses DEC_FRAME_OFFSET as the offset from the VFR (in PCM samples) for the DEC_FRAME_TICK, as shown in Figure 4-13. The DEC_FRAME_OFFSET is set so that it minimizes the decoder propagation delay. The decoder frames are aligned so that the decoder finishes processing the current packet right before it sends the last PCM sample from the previous packet to the audio front end. The QDSP_rxBudget is the worst-case processing time required to finish the decoding process. The parameter QDSP_rxBudget, is stored in the DMSS source file “qdspdma.h” and is set by the firmware. The difference (DEC_INT_ADVANCE – QDSP_rxBudget) is the transaction window for the microprocessor to prepare the decoder packet.

Figure 4-13 Decoder packet transfer timing

VocoderFrameReferenceStrobe

DEC_FRAMETICK

DECFRAMEOFFSET

DecoderInterrupt

DEC

ADVANCE

QDSP_rxBudget

INT

013-051

Decoder must finishdecoding the packet andsend the 1st PCMsample out

Decoder transactionwindow where CPU canwrite decoder packet




4.4.3.3 Software interface

The microprocessor communicates with the QDSP2000 by one of the following methods: encoder and decoder packet buffers, commands and messages, and Direct Memory Access (DMA).

4.4.3.3.1 Encoder and decoder packet buffers

The encoder and decoder packet buffers are 18 words with one word, encPacketRate or decPacketRate, holding the rate information and 17-word array holding the associated packet data.

The addresses for encPacketRate, encPacketBuf, decPacketRate, and decPacketBuf are stored in the DMSS source file qdspdma.h.

Table 4-2 Encoder/decoder packet buffer

Packet Buffer Words Description

encPacketRate 1 Encoder Rate

0x4: Full 0x2: Quarter 0x0: Blank

0x3: Half 0x1: Eighth

encPacketBuf 17 Encoder Packet, 11 for EVRC

decPacketRate 1 Decoder Rate

0x4: Full 0x2: Quarter 0x0: Blank

0x3: Half 0x1: Eighth 0xe: Erasure

decPacketBuf 17 Decoder Packet, 11 for EVRC





4.4.3.3.2 Commands and messages

When command message is sent to the QDSP2000 the address is used for a semaphore handshaking mechanism between the microprocessor and QDSP2000. The microprocessor sends an interrupt to the QDSP2000 after a complete command packet is sent to the uPCommandBuf. The QDSP2000 processes the command and clear the uPCommandReg to indicate the completion of the command. If the command can not be serviced by the QDSP2000 (e.g., a FM configuration command is sent while the QDSP2000 in operating in the Vocoder state) then the QDSP2000 sets the uPCommandReg to –1.

Table 4-3 Commands and messages

Buffer Name Words Description

uPCommandReg 1 Command header

The ARM7TDMI writes the command type into this register.

uPCommandBuf 6 Command buffer

The ARM7TDMI writes the command data into this buffer.

dspMessageReg 1 Message header.

QDSP2000 writes message type into this register.

dspMessageBuf 2 Message buffer

QDSP2000 writes the message data into this buffer




Figure 4-14 shows the interaction for the Command transfer method.

When messages are passed back to the microprocessor a similar semaphore mechanism is used. The QDSP2000 sends an interrupt to the microprocessor after a message is placed in the dspMessageBuf and the dspMessageReg contains the message type. The microprocessor must clear the message header after responding to the interrupt notifying the QDSP2000 that the message was received. Figure 4-15 shows the interactions for message transfer method.

Figure 4-14 Command interface flow

Microprocessor DSP

Clear Header

Send Command andHeader

Send Interrupt

DSP Responds

Clear Header

Command Process

Send 2nd Command andHeader

013-052





4.4.3.4 DMA access

The microprocessor and QDSP2000 can exchange commands and messages through the QDSP2000’s internal memory. All of the QDSP2000, 16-bit wide, data memory is accessible to the microprocessor. Using the direct memory access interface allows the microprocessor to read or write certain parameters directly without sending or receiving an interrupt. Service routines must use the variable names found in the “qdspdma.h” file supplied with the DMSS source code. The absolute address for each DMA-accessible parameter is calculated by adding 0x3000000 to the offset stored in “qdspdma.h.” It is the service routine’s responsibility to ensure that the user/supervisor mode bit is set in supervisor mode prior to accessing the memory space of the QDSP2000. User mode accesses to the QDSP2000 memory space will result in a microprocessor abort.

Figure 4-15 Message interface flow

Microprocessor DSP

Clear Header

Prepare Message andHeader

Send Interrupt

ARM Responds

Clear Header

Read Message

Send 2nd Message andHeader

013-053




4.5 ARM microprocessor and peripheralsThe MSM6000 contains an embedded ARM7TDMI microprocessor and supporting peripherals. The support peripherals include the Memory and Peripheral Interface Controller, Sleep Controller, Clock Controller, Watchdog Controller, and Watchdog circuit.

The ARM7TDMI used in the MSM6000 is a high performance, low power microprocessor. Some of the features of the ARM microprocessor include a 3 stage pipelined RISC architecture, both 32-bit ARM and 16-bit THUMB instruction sets, a 32-bit address bus, and a 32-bit internal data bus. For more information on using the ARM7TDMI please refer to the Advanced RISC Machines publication ARM7TDMI Data Sheet (document number ARM DDI 0029E.) The ARM processor is configured for little-endian mode and supports a 16-bit external data bus.

4.5.1 Memory and peripheral interface controller

The Memory and Peripheral Interface Controller (MPIC) is used to configure the interface between the ARM microprocessor and external peripherals. The Memory and Peripheral Interface Controller contains the chip select generator, wait state generator, and bus-sizer circuits for the external memory and peripheral devices selected by the chip selects. The six chip selects are ROM_CS1_N, ROM_CS2_N, RAM_CS1_N, RAM_CS2_N, LCD_CS_N, and GP_CS_N which are memory mapped into the ARM address space. Table 4-4 shows the ARM system memory map. Each chip select has a set of programmable features. These features are described for each chip select, or pair of chip selects, in the following sections.

Upon reset or watchdog timeout, ROM_CS1_N is the only chip select that is enabled and defaults to maximum wait states. All other chip selects are disabled. After reset or watchdog timeout, the ARM begins executing 32-bit code starting at the first address of ROM_CS1_N (0x0000000).

When the ARM attempts to access either a 32- or 16-bit data segment that is misaligned, the MPIC generates an ABORT.

Table 4-4 ARM memory map

Start Address End Address Memory Block Size

0x0000000 0x0FFFFFF ROM_CS1_N, ROM_CS2_N

16 Mbytes

0x1000000 0x1FFFFFF RAM_CS1_N, RAM_CS2_N

16 Mbytes

0x2000000 0x27FFFFF LCD_CS_N 8 Mbytes

0x2800000 0x2FFFFFF GP_CS_N 8 Mbytes

0x3000000 0x37FFFFF CDMA Engine (Internal) 8 Mbytes

0x3800000 0x3FFFFFF Reserved 8 Mbytes

0x4000000 0x47FFFFF Reserved 8 Mbytes

0x4800000 0x4FFFFFF ARM Peripherals (Internal) 8 Mbytes





4.5.1.1 ROM_CS1_N and ROM_CS2_N

ROM_CS1_N and ROM_CS2_N are mapped to the first 16 Mbytes of address space. Two memory devices can be supported by programming the starting address of the second device into the ROM2_BASE bit field of the MEMORY_WAIT1 register. When using two devices of unequal size, the larger device must be selected by ROM_CS1_N and the size of that device must be programmed into ROM2_BASE. This enables a contiguous address space to be assigned for the two devices.

The MSM6000 requires 16-bit devices on ROM_CS1_N and ROM_CS2_N. 8-bit bus sizing is not available for these chip selects. The maximum wait states (63) are inserted on 8-bit accesses to ROM addressing space. There is bus sizing for 32-bit accesses to ROM_CS1_N and ROM_CS2_N. When a 32-bit accesses is performed to these chip selects, it is converted to two 16-bit accesses transparently by the ARM.

The number of MCLK cycles it takes for ROM_CS1_N memory accesses are programmable from 1 to 15 through the ROM_HWORD_WAIT bit field of the MEMORY_WAIT1 register. Additional wait states, MCLK cycles, can be inserted for the first access of sequential bus sizer accesses by programming the ROM1_RD_CNT or the ROM1_WR_CNT bit fields of the BSIZER_CTL1 register. For ARM accesses that are 8 or 16 bits, each read access has ROM_HWORD_WAIT + ROM1_RD_CNT wait states, and each write access has ROM_HWORD_WAIT + ROM1_WR_CNT wait states. For ARM accesses that are 32 bits, the first memory access of a read has ROM_HWORD_WAIT + ROM1_RD_CNT wait states, and the first memory access of a write has ROM_HWORD_WAIT + ROM1_WR_CNT wait states. The remaining read or write memory accesses necessary to complete the ARM access have only ROM_HWORD_WAIT wait states. Table 4-5 shows the wait states for every type of access to ROM_CS1_N.

Table 4-5 ROM_CS1_N walt status

ROM_CS1_N Width

ARM Access Type 1st Access Wait States 2nd Access Wait States

16 bits 32-bit Read ROM_HWORD_WAIT + ROM1_RD_CNT ROM_HWORD_WAIT

16 bits 32-bit Write ROM_HWORD_WAIT + ROM1_WR_CNT ROM_HWORD_WAIT

16 bits 16-bit Read ROM_HWORD_WAIT + ROM1_RD_CNT

16 bits 16-bit Write ROM_HWORD_WAIT + ROM1_WR_CNT




The number of MCLK cycles it takes for ROM_CS2_N memory accesses are programmable from 1 to 15 through the ROM2_HWORD_WAIT bit field of the MEMORY_WAIT1 register. Additional wait states, MCLK cycles, can be inserted for the first access of a sequential bus sizer accesses by programming the ROM1_RD_CNT or the ROM2_WR_CNT bit fields of the BSIZER_CTL1 register. For ARM accesses that are 8 or 16 bits, a read has ROM2_HWORD_WAIT + ROM2_RD_CNT wait states, and a write has ROM2_HWORD_WAIT + ROM2_WR_CNT wait states. For ARM accesses that are 32 bits, the first memory access of a read has ROM2_HWORD_WAIT + ROM1_RD_CNT wait states, and the first memory access of a write has ROM2_HWORD_WAIT + ROM2_WR_CNT wait states. The remaining read or write memory accesses necessary to complete the ARM access have only ROM2_HWORD_WAIT wait states. Table 4-6 shows the wait states for every type of access to ROM_CS2_N.

The ROM_CS1_N chip select is always enabled. ROM_CS2_N can be enabled or disabled through the ROM2_CS_EN bit of the CS_CTL register.

Any write performed to ROM_CS1_N or ROM_CS2_N generates an ABORT to the ARM unless the ARM is in supervisor mode. This provides some memory protection for ROM_CS1_N and ROM_CS2_N.

Upon reset or watchdog timeout ROM_CS1_N is enabled, ROM_CS2_N is disabled, ROM2_BASE is set to 8 Mbytes, ROM_HWORD_WAIT is set to 15 wait states, ROM1_WR_CNT is set to 0 wait states, and ROM1_RD_CNT is set to 0 wait states.

4.5.1.2 RAM_CS1_N and RAM_CS2_N

RAM_CS1_N and RAM_CS2_N are mapped to the second 16 Mbytes of address space. Two memory devices can be supported by programming the starting address of the second device into the RAM2_BASE bit field of the MEMORY_WAIT2 register. When using two devices of unequal size, the larger device must be selected by RAM_CS1_N and the size of that device must be programmed into RAM2_BASE. This enables a contiguous address space to be assigned for the two devices.

Table 4-6 ROM_CS2_N walt status

ROM_CS2_N Width

ARM Access Type 1st Access Wait States 2nd Access Wait States

16 bits 32-bit Read ROM2_HWORD_WAIT + ROM2_RD_CNT ROM2_HWORD_WAIT

16 bits 32-bit Write ROM2_HWORD_WAIT + ROM2_WR_CNT ROM2_HWORD_WAIT

16 bits 16-bit Read ROM2_HWORD_WAIT + ROM2_RD_CNT

16 bits 16-bit Write ROM2_HWORD_WAIT + ROM2_WR_CNT





RAM_CS1_N and RAM_CS2_N can independently support 8- or 16-bit devices. The bit size of RAM_CS1_N and RAM_CS2_N must be programmed into the RAM1_BSIZE_EN and RAM2_BSIZE_EN bits of the BSIZER_CTL2 register. When configured for 16 bits, the bus sizer splits 32-bit accesses into two 16-bit accesses. When configured for 8-bits, the bus sizer splits 32-bit accesses into four 8-bit accesses, and 16-bit accesses are split into two 8-bit accesses.

The number of MCLK cycles for RAM_CS1_N memory accesses are programmable from 1 to 15 through the RAM1_MIN_WAIT bit field of the MEMORY_WAIT2 register. Additional wait states, MLCK cycles, can be inserted for the first accesses of sequential bus sizer accesses by programming the RAM1_RD_CNT or RAM1_WR_CNT bit fields of the BSIZER_CTL2 register. For ARM accesses that are the same size or smaller than RAM_CS1_N width, a read has RAM1_MIN_WAIT + RAM1_RD_CNT wait states, and a write has RAM1_MIN_WAIT + RAM1_WR_CNT wait states. For ARM accesses that are larger than the RAM width, the first memory access of a read has RAM1_MIN_WAIT + RAM1_RD_CNT wait states, and the first memory access of a write has RAM1_MIN_WAIT + RAM1_WR_CNT wait states. The remaining read or write memory accesses necessary to complete the ARM access have only RAM1_MIN_WAIT MCLK cycles. Table 4-7 shows the wait states for every type of access to RAM_CS1_N.

Table 4-7 RAM_CS1_N walt states

RAM_CS1_ N Width

ARM Access

Type1st Access Wait States 2nd Access

Wait States3rd Access Wait States

4th Access Wait States

16 bits 32-bitRead RAM_MIN_WAIT + RAM1_RD_CNT RAM_MIN_WAIT

16 bits 32-bit Write RAM_MIN_WAIT + RAM1_WR_CNT RAM_MIN_WAIT

16 bits 16-bit Read RAM_MIN_WAIT + RAM1_RD_CNT

16 bits 16-bit Write RAM_MIN_WAIT + RAM1_WR_CNT



8 bits 32-bit Read RAM_MIN_WAIT + RAM1_RD_CNT RAM_MIN_WAIT RAM_MIN_WAIT RAM_MIN_WAIT

8 bits 32-bit Write RAM_MIN_WAIT + RAM1_WR_CNT RAM_MIN_WAIT RAM_MIN_WAIT RAM_MIN_WAIT

8 bits 16-bit Read RAM_MIN_WAIT + RAM1_RD_CNT RAM_MIN_WAIT

8 bits 16-bit Write RAM_MIN_WAIT + RAM1_WR_CNT RAM_MIN_WAIT






The MCLK cycles for RAM_CS2_N memory accesses are programmable from 1 to 15 through the RAM2_MIN_WAIT bit field of the MEMORY_WAIT2 register. Additional wait states can be inserted for the first accesses of sequential bus sizer accesses by programming the RAM2_RD_CNT or RAM2_WR_CNT bit fields of the BSIZER_CTL2 register. For ARM accesses that are the same size or smaller than the RAM_CS2_N width, a read has RAM2_MIN_WAIT + RAM2_RD_CNT wait states, and a write has RAM2_MIN_WAIT + RAM2_WR_CNT wait states. For ARM accesses that are larger than the RAM width, the first memory access of a read has RAM2_MIN_WAIT + RAM2_RD_CNT wait states, and the first memory access of a write has RAM2_MIN_WAIT + RAM2_WR_CNT wait states. The remaining read or write memory accesses necessary to complete the ARM access have only RAM2_MIN_WAIT MCLK cycles. Table 4-8 shows the wait states for every type of access to RAM_CS2_N.

RAM_CS1_N and RAM_CS2_N are both disabled upon reset or watchdog timeout. They can be enabled or disabled by programming the RAM1_CS_EN and RAM2_CS_EN bits of the CS_CTL register.

Table 4-8 RAM_CS2_N walt status

RAM_CS2_N Width

ARM Access

Type1st Access Wait States 2nd Access

Wait States3rd Access Wait States

4th Access Wait States

16 bits 32-bit Read RAM2_MIN_WAIT + RAM2_RD_CNT RAM2_MIN_WAIT

16 bits 32-bit Write RAM2_MIN_WAIT + RAM2_WR_CNT RAM2_MIN_WAIT

16 bits 16-bit Read RAM2_MIN_WAIT + RAM2_RD_CNT

16 bits 16-bit Write RAM2_MIN_WAIT + RAM2_WR_CNT



8 bits 32-bit Read RAM2_MIN_WAIT + RAM2_RD_CNT RAM2_MIN_WAIT RAM2_MIN_WAIT RAM2_MIN_WAIT

8 bits 32-bit Write RAM2_MIN_WAIT + RAM2_WR_CNT RAM2_MIN_WAIT RAM2_MIN_WAIT RAM2_MIN_WAIT

8 bits 16-bit Read RAM2_MIN_WAIT + RAM2_RD_CNT RAM2_MIN_WAIT

8 bits 16-bit Write RAM2_MIN_WAIT + RAM2_WR_CNT RAM2_MIN_WAIT







4.5.1.3 X16 SRAM interface

The MSM6000 supports the common 16-bit interface to industry standard SRAM devices. This is illustrated in Table 4-9.

*: GPIO_INT37 can be used to output LB_N or RAM_CS2_N.

The X16SRAM interface is enabled via the control register CS_CTL:BY16SRAM_ONLY (bit 12). When this bit is set (1) and the microprocessor executes a RAM access, the pins LWR_N, A0 and GPIO_INT37 or GPIO_INT12 are replaced with the new signals WE_N, UB_N and LB_N respectively. For all other accesses, the pins LWR_N, A0 and RD_N perform their standard function.

WE_N is the SRAM write enable strobe, UB_N is the SRAM upper byte enable strobe, and LB_N is the SRAM lower byte enable strobe. Figure 3-9 provides the timing diagram of the X16SRAM interface.

Note that LB_N is available on GPIO_INT37 as well as on GPIO_INT12. This allows GPIO_INT37 to output RAM_CS2_N (alternate function) for external accesses.

When the X16SRAM interface is enabled and GPIO_INT37 is used for LB_N, RAM_CS2_N is automatically disabled and any access to RAM_CS2_N will result in a microprocessor abort.

At power-up or the rising edge of RESOUT_N, CS_CTL:BY16SRAM_ONLY is clear (0) and the X16SRAM interface is disabled.

The software values and the pins used to output the X16SRAM signals are summarized below:

! X16 SRAM for RAM_CS_N

" LB_N is output on GPIO_INT37 pin (D2)

" UB_N is output on A0 pin (E4)

" WE_N is output on LWR_N pin (D3)

" Program the following registers as shown in Table 4-10.

Table 4-9 MSM6000 X16 SRAM interface pins

MSM6000 Pin X16SRAM Enabled 16-bit SRAM pin

LWR_N WE_N WE_N

A0 UB_N UB_N

RAM_CS_N RAM_CS_N CS_N

GPIO_INT37* or GPIO_INT12 LB_N LB_N

RD_N RD_N RD_N




! X16 SRAM for RAM_CS_N, RAM_CS2_N

" LB_N is output on GPIO_INT12 pin (D1)

" UB_N is output on A0 pin (E4)

" WE_N is output on LWR_N pin (D3)

" RAM_CS2_N is output on GPIO_INT37 pin (D2)

" Program the following registers as shown in Table 4-11.

4.5.1.4 LCD_CS_N

LCD_CS_N, along with the LCD_E pin, can be used to interface to certain parallel style LCD controllers. LCD_CS_N always covers an 8 Mbyte address range starting at 0x2000000. The LCD chip select can be enabled or disabled by programming the LCD_CS _EN bit of the CS_CTL register. Upon reset or watchdog timeout, the LCD chip select is disabled.

The number of MCLK cycles for LCD_CS_N accesses is programmable from 0 to 15 through the LCD_ACCESS bit field of the LCD_CTL register. This defines the LOW period for LCD_CS_N. The rise and fall times of the LCD_E pin during an LCD_CS_N access can be programmed through the LCD_E_SETUP and LCD_E_HIGH bit fields of the LCD_CTL register and must be less than LCD_ACCESS. There is no bus-sizing available for this Chip Select.

Table 4-10 X16SRAM on RAM_CS_N

Register Bits Value

CS_CTL 12 1

10:9 11

1 1

GPIO_INT_FUNCTION_SEL_0 4 1

Table 4-11 X16SRAM on RAM_CS_N, RAM_CS2_N

Register Bits Value

CS_CTL 12 0

10:9 11

2:1 11







4.5.1.5 GP_CS_N

GP_CS_N covers an 8 Mbyte address range starting at 0x2800000. GP_CS_N can be enabled or disabled by programming the GP_CS_EN bit of the CS_CTL register. Upon reset or watchdog timeout, the GP_CS_N is disabled. The number of MCLK cycles for a GP_CS_N access is programmable through the GP_WAIT bit field of the GP_CS_WAIT register. There is no bus- sizing available for this Chip Select.

4.5.2 ARM clock and power managementThe MSM6000 provides three ways of managing clock and power for the ARM microprocessor. The MSM6000 has a powerdown control unit, a clock scale control unit, and a clock source select circuit.

The sleep controller clock clocks the powerdown circuit since it is always running in the system. The function of this timer is to gate the clock input to the microprocessor while the external VCTCXO circuit warms up. The registers that are used for clock and power management are uP_CLK_CTL1, uP_CLK_CTL2.

Entry to powerdown mode is specified by two successive writes to the powerdown bit of the uP_CLK_CTL1 register (write a 1 followed by a 0). This prevents accidental entry to powerdown mode. Upon entering powerdown the clock to the microprocessor is gated off and the ARM retains its state. The microprocessor remains in powerdown state until an unmasked interrupt is asserted on nIRQ or nFIQ.

Wakeup is initiated by any unmasked interrupt to the microprocessor (nFIQ, nIRQ) from the interrupt controller. The warmup time (programmable) of the oscillator is accounted for before waking up the processor. Bits [3:1] of the uP_CLK_CTL1 register are used to program a warmup time, XTAL_WU_DURATION. This allows the VCTCXO to have a warmup period of a certain number of sleep controller clock cycles before its output is allowed to clock the processor. This suppresses non-uniform and unstable clocks from reaching the microprocessor, which can then send the processor to an undesirable state as it powers up. MSM6000 supports three different warmup durations.

On initial powerup, RESIN_N is asserted. The warmup timer defaults to a minimum duration time interval. The microprocessor starts on de-assertion of RESOUT_N. On initial powerup, RESIN_N must be of sufficient duration for the external VCTCXO to stabilize. The same is true for the Watchdog timeout duration.

The clock scale unit allows software to change the clock rate of the processor. Clock rates can be scaled down by factors of 1, 2, or 3 to allow for reduced power consumption. When exiting power down, the clock rate specified by uP_CLK_CTL2 is used. After reset, a divide-by-1 rate is used. The clock rate is not changed upon an interrupt assertion. Therefore clock rates must not be set to a low rate when waiting for a critical interrupt. Setting the clock scale unit for slow clock rates results in long latencies for the interrupt service routines.

In slotted-paging mode, software shuts down the TCXO when the MSM6000 enters SLEEP mode. During the SLEEP interval, the SLEEP oscillator remains active and drives the MSM6000’s internal SLEEP controller. The microprocessor is restarted at the end of the SLEEP interval as the phone wakes up.




4.5.3 Reset and pause

The Reset Pause block is responsible for:

! Generating a synchronous reset for the ARM as well as the other AMBA (Advance Microcontroller Bus Architecture) peripherals

! Providing status information concerning the source of the last reset (pin or watchdog generated)

! Providing a software-controllable mechanism for stalling the ARM for a specified amount of time.

This block generates reset signals for the ARM and the system. It also controls the clock to the ARM microprocessor providing the ability to reset or pause the ARM. Software can use the pause mechanism to halt the microprocessor for a specified amount of time.

This block combines the two reset signals, power-on reset (RESIN_N) and watchdog reset, and provides a synchronously deasserting reset pulse to the rest of the chip. BnRES is guaranteed to be asserted for a minimum of 2 BCLK pulses regardless of the duration of the RESIN_N pulse. The source of the last reset is stored in bit 0 of register RESET_STATUS.

This block also contains the circuits for controlling the clock for the ARM. This can be done by asserting BWAIT which stalls the microprocessor until BWAIT deasserts. To make the timer behavior consistent, this block also takes into account whether the microprocessor clock has been divided down in power saving modes and scales the delay accordingly.

Figure 4-16 Reset generation

Reset/Pause

ControlWatchdog

To otherMSM6000Blocks

RESIN/

RESOUT/ ARM7TDMI

089-025





Software pauses the processor by writing to a 10-bit counter through register PAUSE_TIMER. This action immediately asserts BWAIT for 1 cycle. BWAIT remains asserted for 64*PAUSE_TIMER/clock scale periods. For example, TCXO is a 19.2 MHz clock (52 ns period) and the value 0 was written to uP_CLK_CTL2 (requesting no clock divide) so the period is 52 ns, then writing the value 10 to PAUSE_TIMER pauses the microprocessor for 52 ns + 10*64*(52 ns) = 33.3 µs. If the value 1 is written to uP_CLK_CTL2 (requesting a divide by 2 on MCLK) the period is 104 ns, then writing the value 10 to PAUSE_TIMER pauses the microprocessor for 104 ns + 10*64*(104 ns)/2 = 33.3 us. The discrepancy in the time is a result of the single waitstate that is asserted in addition to the requested delay. To reduce the possibility of very lengthy pauses, the maximum delay is (1023*64/clock scale)+1 periods (including the single added waitstate).

This timer is meant for introducing small delays in the system software. Note that if the microprocessor clock frequency is sufficiently low and/or a large clock divide value is used, delays introduced by this timer can exceed the watchdog timer duration resulting in a watchdog reset of the system.

4.5.4 Watchdog timer

The watchdog timer is a 21-bit counter running on the sleep controller clock regime that enables the Mobile Station to recover from unexpected hardware or software anomalies. Unless the microprocessor periodically resets the watchdog timer, the watchdog timer resets the Mobile Station. The watchdog timer is disabled and reset by grounding the WDOG_EN pin. Asserting the RESIN_N pin also resets the watchdog timer. The watchdog timer is enabled by leaving the WDOG_EN pin unconnected (it has an internal pull-up) or by connecting it to VDD. The watchdog timer is disabled by hardware as soon as the ARM processor enters debug mode (indicated by the DBGACK pin of the processor transitioning from low to high). To re-enable the watchdog timer, apply a system reset to clear the state of the internal signal wdog_disable.

The watchdog circuit pulses the signal WATCHDOG_EXPIRED when the watchdog timer has expired. In NATIVE and ICE mode, this signal is combined with the RESIN_N pin to generate RESOUT_N and the internal reset for the MSM.

Figure 4-17 Watchdog timer configuration in NATIVE and ICE mode

WDOG_STB

RESOUT_N

wdog_expired

wdog_disable

013-055

WatchdogTimer

micro_clk

WDOG_EN

RESIN_N synccircuit

reset/to MSM




4.5.4.1 Sleep mode

In sleep mode, the microprocessor cannot reset the watchdog timer. The sleep controller contains an auto-kicker that resets the Watchdog Timer every 1024 TCXO/4 clock cycles (~200 µs) when SLEEP_XTAL_EN = 0. When the sleep crystal is used (SLEEP_XTAL_EN =1), the auto-kicker resets the watchdog every 976.5 µs (32 sleep controller clock cycles). The output of the sleep controller auto-kicker is also routed to output via the WDOGSTB pin. To enable the auto-kicker, the microprocessor must write a sequence of 1, 0 to the SLEEP_CTL:AUTO_KICK_ARM bit. When the sleep counter reaches its terminal count, the auto-kicker circuit is disabled.

4.5.4.2 Non-sleep mode

In non-sleep mode, the microprocessor must reset the watchdog timer at least once every 213 ms. If the microprocessor does not reset the watchdog timer in this time, the watchdog timer expires and asserts an internal RESIN_N signal to the system. The WDOG_EXPIRED signal lasts between 53.3 ms to 106 ms. To reset the watchdog timer, the microprocessor must write a sequence of 1, 0, 1 to the SLEEP_CTL:WATCH_DOG bit.

4.5.4.3 General-purpose timer operation

When the microprocessor is powered down after programming a general-purpose timer delay that exceeds the watchdog timer interval, the general-purpose timer autokicker must be enabled to prevent the watchdog from resetting the ARM microprocessor. The autokicker is disabled when the general-purpose timer reaches its terminal count.

Figure 4-18 Watchdog timer block diagram

wdog_disable

start

reset

AUTO_KICK_ARM(sequence of 1,0)

WAKEUP_INT CNTR

clk clk

wdog_stb_gptimer

sleep controller clk

sleep_xtal_en

013-056

WATCH_DOG (sequence of 1,0)

Autokicker

NonAutokicker

21-bitWDOG_EXPIRED

WDOGSTB

enable

reset

reset

start

18-bit

CNTR

WDOG_EN

RESIN/





4.5.5 Interrupt controller

The MSM6000 device’s Interrupt Controller interfaces the ARM microprocessors nFIQ and nIRQ interrupt sources. The Interrupt Controller consists of first-level interrupt sources. There are second-level interrupt sources for the GPIO_INT pins and grouped together as the first-level interrupt, GPIO_GROUP_INT. Each of the first interrupt sources has a separate nFIQ and nIRQ interrupt mask that is logically ANDed with the interrupt prior to the first-level interrupt sources being logically NORed to the nFIQ and the nIRQ.




Figure 4-19 Interrupt controller

089-035

Interrupt Bit Slice

GPIO_INT[50:0]GPIO_INT Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

Interrupt Bit Slice

QDSP2_INT

GPIO_INT[50:0]

FM_RF_SLEEP_INT

TIME_TICK2_INT

DP_RX_DATA2_INT

DP_RX_DATA

UART2_INT

SEARCH_DMA_REQUEST

SLEEP_FEE_INT

SBI_INT

DEM_DSP/RX_QP

AUX_PCM_DIN_INT

KEYSENSE_INT

TX_WBD_INT

RX_WBD_INT

UART_INT

TIME_TICK_INT

26MS_INT

SEARCH_DONE_INT

SYS_TIME_INT2

TX_1.25MS_INT

WAKEUP_INT

GPTIMER_INT

DEC_INT

TX_FR_INT

IRQ-masked QDSP2_INTO

OR_RED

IRQ-masked FM_RF_SLEEP_INT

IRQ-masked TIME_TICK2_INT

IRQ-masked DP_RX_DATA2_INT

IRQ-masked DP_RX_DATA_INT

IRQ-masked UART2_INT

IRQ-masked SEARCH_DMA_REQUEST

IRQ-masked SLEEP_FEE_INT

IRQ-masked SBI_INT

IRQ-masked DEM_DSP_INT

IRQ-masked AUX_PCM_DIN_INT

IRQ-masked KEYSENSE_INT

IRQ-masked TX_WBD_INT

IRQ-masked RX_WBD_INT

IRQ-masked UART_INT

IRQ-masked TIME_TICK_INT

IRQ-masked 26MS_INT

IRQ-masked SEARCH_DONE_INT

IRQ-masked SYS_TIME_INT2

IRQ-masked SYS_TIME_INT1

IRQ-masked TX_1.25MS_INT

IRQ-masked TX_WAKEUP_INT

IRQ-masked GPTIMER_INT

IRQ-masked DEC_INT

IRQ-masked TX_FR_INT

FIQ-masked FM_RF_SLEEP_INT

FIQ-masked TIME_TICK2_INT

FIQ-masked DP_RX_DATA2_INT

FIQ-masked DP_RX_DATA_INT

FIQ-masked UART2_INT

FIQ-masked SEARCH_DMA_REQUEST

FIQ-masked SLEEP_FEE_INT

FIQ-masked SBI_INT

FIQ-masked DEM_DSP_INT

FIQ-masked AUX_PCM_DIN_INT

FIQ-masked KEYSENSE_INT

FIQ-masked TX_WBD_INT

FIQ-masked RX_WBD_INT

FIQ-masked UART_INT

FIQ-masked TIME_TICK_INT

FIQ-masked 26MS_INT

FIQ-masked SEARCH_DONE_INT

FIQ-masked SYS_TIME_INT2

FIQ-masked SYS_TIME_INT1

FIQ-masked TX_1.25MS_INT

FIQ-masked TX_WAKEUP_INT

FIQ-masked GPTIMER_INT

FIQ-masked DEC_INT

FIQ-masked TX_FR_INT

(bit-wise OR)

FIQ-masked QDSP2_INTOGPIO_GROUP_INT

Interrupt Bit SliceIRQ-masked GPIO_GROUP_INT

FIQ-masked GPIO_GROUP_INT

IRQ-masked INTs nIRQ

FIQ-masked INTs nFIQ

151

SYS_TIME_INT1





Dynamic interrupt prioritizing is achieved by programming the IRQ_MASK and FIQ_MASK registers to a different mask pattern. High-priority interrupts can be assigned to the nFIQ interrupt source to the ARM microprocessor by unmasking the corresponding bit in the FIQ_MASK register. Low priority interrupts are assigned to the nIRQ interrupt source by unmasking the corresponding bit in the IRQ_MASK register.

Identification of the interrupt source is achieved by reading the INT_STATUS register and logically ANDing it with the FIQ_MASK or IRQ_MASK.

The first-level interrupt sources are shown in Figure 4-20.

Figure 4-20 Interrupt bit slice

INT

FIQ

_MA

SK

IRQ

_MA

SK

FF

R

S

INT

_STA

TU

S

INT

_CLE

AR

FIQ-masked INT

IRQ-masked INT

013-058




Each GPIO_INT pin of the MSM6000’s General Purpose interface is an interrupt source in addition to its normal function. The pins, GPIO_INT[50:0] are all second- level interrupt sources. The second-level interrupt sources are masked by GPIO_INT_MASK and then logically ORed to create the first-level interrupt source, GPIO_GROUP_INT. Second-level interrupt sources require the additional register polling of GPIO_INT_STATUS in order to identify which interrupt has been triggered.

Figure 4-21 GPIO_INT bit slice

0

1

GP

IO_I

NT_

CLE

AR

R

S

FF

GP

IO_I

NT_

STA

TUS

GPIO_INT_MASKGPIO_MASKED_INT[m]

(m=0,1,...50)

GPIO_INT[m](m=0,1,...50)

Edge detect

GPIO_INT_CTL_x[n]089-036





4.6 Mode select and emulation considerations

4.6.1 Mode selection inputs

The MSM6000 can be put into three different operating modes The mode is selected by the MODE[1:0] inputs. MODE[1:0] are internally pulled high, causing MODE[1:0] = 11 to be the default mode (NATIVE). The different modes are listed in Table 4-12 below along with the binary value applied to MODE[1:0].

4.6.2 NATIVE mode

NATIVE mode is default operating mode for the MSM6000. When the MSM6000 operates in NATIVE mode, it uses the internal microprocessor. NATIVE mode is the default mode when MODE[1:0] pins are left unconnected. The MSM device supports JTAG in this mode.

4.6.3 MSM ICE mode

MSM in-circuit emulation (ICE) mode is used for Mobile Station development and system software testing and debugging. In ICE mode, the internal microprocessor is disabled and all the necessary signals are brought to pins, so an external emulator can be used. In this mode, all of the peripheral circuits and features of the MSM6000 remain active.

Active emulation provides the best software development and debug environment. This is because all the CPU signals are available for the ICE analyzer and trigger. The Lauterbach system is an ICE emulation environment with the TRACE32/TRACE32 FIRE ICE pod. The MSM6000 operates in ICE mode and an FPGA configures the bus for the Lauterbach pod.

In ICE mode, the MSM6000 becomes a peripheral which contains the CDMA processor, the vocoder, digital FM, UARTs, and the SBI controller with a generic ASB bus interface. The bus interface is the minimum interface as required by the MSM6000 (with minimum address and data lines).

Table 4-12 MODE[1:0] functions

MODE[1:0] Operating Mode

10 ICE Mode

11 NATIVE/JTAG

01 HI-Z

00 Reserved. DO NOT USE.




The emulation interface for the MSM6000 consists of an emulation FPGA and the MSM6000 connected in parallel to the ICE unit. This eliminates latency and speed issues associated with external memory accesses. The interface is Advanced System Bus compliant.

Figure 4-22 ICE mode emulation interface

By using this approach the interface can run at TCXO frequencies. If it is a requirement that all the debug features run, then the DIV/2 mode can be used. When the ICE is running from its internal memory and there is no requirement for the GPIO_INTs in the FPGA, then the ICE mode can operate without the FPGA. For example stand alone tests of internal peripherals such as the UARTs can operate without the FPGA in the circuit.

4.6.3.1 Emulator interface

The Emulation FPGA contains a portion of the memory map decoder, a copy of the bus sizer for external memory reads and writes, and a bridge to the duplicated GPIO and interrupt control circuits. All GPIO_INT signals go through the FPGA in ICE mode The alternate function chip selects on the GPIO pins are from the FPGA in ICE mode, the remaining alternate functions are from the MSM6000. All the memory timing wait states remain in the MSM6000.

MSM6000

089-032

Emulation FPGA

32-bit interface

Emulator

Ext

erna

l Mem

ory

Inte

rfac

e

ASB bus

Table 4-13 MSM6000 emulation interface

Pin SURF6000 Function

ICE Mode Function

GPIO_INT4 KYPD_MEMO BERROR

GPIO_INT5 HEADSET_DET_N ICE_A [23]

GPIO_INT6 AUX_SBI_DT ICE_A [24]

GPIO_INT7 AUX_SBI_CK ICE_A [25]

GPIO_INT8 AUX_SBI_SB ICE_A [26]

GPIO_INT9 UIM_RESET ICE_D [16]

GPIO_INT10 PM_INT_0 ICE_D [17]

GPIO_INT11 TCXO_EN ICE_D [18]





GPIO_INT12 BACKLIGHT ICE_D [19]

GPIO_INT14 CALL_LED ICE_D [21]

GPIO_INT15 A21 ICE_D [22]

GPIO_INT16 UART1_DCD_N ICE_D [23]

GPIO_INT17 PS_HOLD_LED ICE_D [24]

GPIO_INT22 I2C_DATA ICE_D [25]

GPIO_INT23 I2C_CLK ICE_D [26]

GPIO_INT25 UART1_RI_N ICE_D [20]

GPIO_INT27 ICE_A [21]

GPIO_INT29 TX_PCS_HI MCLK_SRC

GPIO_INT31 ICE_A [22]

GPIO_INT32 KYPD_17 ICE_D [27]





KEYSENSE0_N KYPD_1 BPROT [0]

KEYSENSE1_N KYPD_3 BPROT [1]

KEYSENSE2_N KYPD_5 BSIZE [0]

KEYSENSE3_N KYPD_7 BSIZE [1]

KEYSENSE4_N ON_SW_SENSE BTRAN [1]

LWR_N nIRQ

HWR_N nFIQ

RD_N BWRITE

A[20:0] ICE_A[20:0]

D[15:0] D[15:0]

ROM_CS_N BWAIT

RAM_CS_N DBACK

Table 4-13 MSM6000 emulation interface (continued)

Pin SURF6000 Function

ICE Mode Function




4.6.3.2 Pin configuration

The ICE unit drives the ASB signals BA[31:0], BTRAN[1:0], BSIZE[2:0], BPROT[1:0], and BWRITE, to the MSM6000 and the FPGA. The MSM6000 requires the address lines BA[26:0] of the address bus BA[31:0]. The signals BA[31:27] need to be tied low when in ICE mode. The DBGACK is driven from the ICE to the MSM6000.

The BWAIT, BCLK, BnRES signals are outputs from the MSM6000 and inputs to the ICE and FPGA. nIRQ and nFIQ are open drain bidirectional pins from the MSM6000 and open drain outputs on the FPGA. These signals must be wire-ORed and driven to the ICE, with a pull-up resistor on the signal. The signals from each device are mutually exclusive. When the FPGA is driving the nIRQ and nFIQ lines they are inputs to the MSM6000. The BD(data) lines are bidirectional and are driven from the ICE, the MSM6000 and the FPGA.

Table 4-14 Advanced system bus

Signal Name Description

BA[31:0] System address bus driven by the ice

BD[31:0] Bidirectional system data bus

BCLK System clock

BERROR When high indicates a transfer error has occurred

BPROT[1:0] These signals indicate if the transfer is an op-code fetch or data access and if the transfer is in user or supervisor mode

BRES[1:0] These signals indicate the reset status

BSIZE[2:0] These signals indicate the size of the current transfer either a byte, half-word or word

BTRAN[1:0] These signals indicate the type of the next transaction. The types are address only, sequential access or non-sequential access.

BWAIT Driven by the selected slave to indicate if the current transfer is complete. If high the transfer is complete.

BWRITE This signal indicates direction of the data. When high it is a write cycle





4.6.3.3 Lauterbach emulation

Active emulation provides the best software development and debug environment. The Lauterbach emulation system with their TRACE32 ICE pod enables full active emulation of the ARM microprocessor. The MSM6000 is put into MICE mode and an FPGA is used to configure the bus for the Lauterbach pod.

Figure 4-23 Lauterbach emulation setup

The following is a listing of the specific Lauterbach equipment necessary for the interconnection of the MSM6000 to an external Lauterbach Emulation System. This list is presented as a suggestion for the MSM6000 user. Details and specifications of equipment shown on this list are not supplied by QUALCOMM. Contact Lauterbach Incorporated for technical information.

Lauterbach In-circuit Emulator equipment:

! LA-6037 System Controller Unit / 30 MHz / Ethernet / 32 MB.System Controller Unit with 32 Mbyte RAM, 15 MIPS, 80 VA power supply. Ethernet interface to AUI (download 400kB/sec). For all PC and workstation based applications.

! LA-6103 ECU32/15 Emulation Controller UnitCompatible with all emulation probes, 32-bit emulation bus, mapper 15 ns, dual-port access controller, real-time emulation controller, trigger system, event trigger, asynchronous trigger input, strobe output, counter, glitch detector, VCO, PODBUS, pulse generator, slot for SDIL modules.

ARM7

Lauterbach Pod

MSM6000

ARM7

SURF Reference Design

Mic

ropr

oces

sor

Inte

rfac

e P

ins

LauterbachTRACE32

System

Bus ConverterFPGA

ICE Mode(ARM Disabled)

Network

089-037




! LA-6410 High-speed State Analyzer120 trace channels, 32 k depth, 50 ns cycle time, time-stamp unit, performance analyzer, trigger unit, 16 external trigger inputs, 3 trigger outputs

! LA-6263 Static Emulation Memory Module 2M+2M 15 ns.2 MB emulation RAM, 2 MB break RAM (15 ns)

! LA-7230 ICE-RAM Base ModuleSupports ARM7TDMI with and without AMBA

! LA-7232 Module ARM7T with AMBAPassive and active module for ARM7TDMI with AMBA

! LA-7235 Adaptor ARM7T TrackingAdaptor for tracking emulation with and without AMBA

! LA-8602 Driver Package for Ethernet PC LAN on CDHost driver package for PC includes driver for PC-NFS, NOVELL LAN Workplace, LanManager, DEC-NET Pathworks, WindowsSocket on CD (ISO-9960)

! LA-8200 TRACE32 Operating System

! LA-8202 Symbolic HLL Debuggerfor C, C++, PASCAL, PL/M, ADA, Modulia2

! LA-6461 Input probeCMOS probe with 9 inputs

For questions and more specific details please contact:

Lauterbach Inc.13256 SW Hillshire DriveTigard, Oregon, U.S.A. 97223Phone: 503-524-2222FAX: 503-524-2223

4.6.4 HI-Z mode

In the HI-Z mode (01), all digital outputs are put into a high impedance state. This mode is used for board-level interconnect testing.





4.6.5 JTAG debug mode

For a more detailed description of this topic please refer to the ARM Application Note 28: “The ARM7TDMI Debug Architecture” (ARM DAI 0028A). A few important points from that document are reproduced here for a quick overview.

EmbeddedICE is a JTAG-based debugging environment for ARM microprocessors which provides an interface between the source-level symbolic debugger on a host and an ARM microprocessor deeply embedded in any ASIC. The ARM Debug Architecture uses a protocol converter box to allow the debugger to talk via a JTAG port directly to the microprocessor. In effect the scan chains in the microprocessor that are required for test are re-used for debugging.

Figure 4-24 ARM JTAG setup example

There are effectively two scan chains around the ARM microprocessor: a scan chain around the whole periphery of the microprocessor and a subset of the first scan chain, covering only the databus and the breakpoint.

The shorter scan chain on the databus allows instructions and data to be inserted into the microprocessor without the overhead of clocking the data around the entire periphery of the ARM7TDMI processor. In addition to the scan chains, the ARM7TDMI Debug Architecture uses a macrocell called the EmbeddedICE macrocell. The EmbeddedICE macrocell provides on-chip debug support for the ARM7TDMI. The EmbeddedICE macrocell consists of two real time watchpoint register, together with a control and status register. Execution is halted when a match occurs between the values programmed into the EmbeddedICE macrocell and the values currently appearing on the address bus, databus and some control signals.

Native mode debugging uses the ARM JTAG port and the embedded ICE BREAKER unit to control the operation of the ARM processor. This unit contains two hardware break points, if more break points are required then the FLASH must be replaced (shadowed) with SRAM. The JTAG interface consists of the following pins.

MSM6000

JTAGport

ARM7

SURF Reference Design

TMS, TDI, TDOTCK, TRST_INTMODE=0

ARM JTAG Mode

ICDPC

089-038




Table 4-15 MSM6000 ICD (in-circuit) debugger

Pin Description

TCK JTAG – clock input

TRST_N JTAG – reset

TDO JTAG – data out

TDI JTAG – data in

TMS JTAG – This pin enables the ARM TAP controller. Mode select.

TMODE This pin selects either the ARM TAP controller or a second TAP controller used by the CDMA portion of the device.





4.7 General-purpose interface (GPIO_INT)Each GPIO pin can be configured as an interrupt source. Some pins have alternate functions (e.g. chip selects, extended addressing,…) that can be selected by the GPIO_INT_FUNCTION_SEL_x registers. The interrupt configuration and operation is covered in more detail in the Interrupt Controller section (Section 4.5.5) of this document. The alternate functions of the general-purpose interface are selected by the GPIO_FUNCTION_SEL_x registers (0 and 1). Table 4-16 identifies which pins have an alternate function.

Table 4-16 Alternate functions

Pin Alternate Function Register and Bit(s)

Microprocessor Interface

GPIO_INT41 LCD_EN GPIO_INT _FUNCTION_SEL_0:LCD_EN_SEL

GPIO_INT40 LCD_CS_N GPIO_INT _FUNCTION_SEL_0:LCD_CS_SEL

GPIO_INT39 GP_CS_N GPIO_INT _FUNCTION_SEL_0:GP_CS_SEL

GPIO_INT38 ROM_CS2_N GPIO_INT _FUNCTION_SEL_0:ROM_CS2_SEL

GPIO_INT37 RAM_CS2_N GPIO_INT _FUNCTION_SEL_0:RAM_CS2_SEL

GPIO_INT31 A[22] GPIO_INT_ADDR_SEL: ADDRESS_22_EN

GPIO_INT15 A[21] GPIO_INT_ADDR_SEL: ADDRESS_21_EN

UART2 Interface – Option 1

GPIO_INT21 DP_TX_DATA2 GPIO_INT_FUNCTION_SEL_1:GPIO_UART2_SEL

GPIO_INT20 DP_RX_DATA2

GPIO_INT19 RFR_N2

GPIO_INT18 CTS_N2

UART2 Interface – Option 2

GPIO_INT21 DP_TX_DATA2 CODEC_CTL:UART2_SEL

GPIO_INT20 DP_RX_DATA2

GPIO_INT19 RFR_N2

GPIO_INT18 CTS_N2




GPIO_INT_TSEN, GPIO_INT_IN, and GPIO_INT_OUT control the basic read and write access for the GPIO_INT pins. The GPIO_INTs are separated into three groups where the pins GPIO_INT[15:0] GPIO_INT[31:16] and GPIO_INT[47:45], GPI_INT[44:42], and GPIO_INT[41:33]. Each bank of GPIO_INTs has a corresponding GPIO_INT_TSEN, GPIO_INT_IN, and GPIO_INT_OUT. Clearing (0) the register bit in GPIO_INT_TSEN sets the GPIO_INT pin as an input and setting (1) GPIO_INT_TSEN sets the respective pin as an output. Bits 12:10 of GPIO_INT_TSEN_2 are reserved and cannot be set (1) since these bits are mapped to the GPI_INT[44:42] pins. The microprocessor registers GPIO_INT_IN and GPIO_INT_OUT are used for read and write operations for the general-purpose interface. Bits 12:10 of GPIO_INT_OUT_2 are reserved, values written to these bits have no effect on the GPI_INT[44:42] pins. The basic GPIO_INT pin structure is shown in Figure 4-25.

R-UIM Interface – Option 1

GPIO_INT19 UIM_CLK UART2_UIM_CFG:UIM_GPIO_SEL

UART2_UIM_CFG:UIM_SEL GPIO_INT21 UIM_DATA

R-UIM Interface – Option 2

AUX_PCM_CLK UIM_CLK CODEC_CTL:UART2_SEL

UART2_UIM_CFG:UIM_SELAUX_PCM_DOUT UIM_DATA

Table 4-16 Alternate functions (continued)





At the rising edge of RESOUT_N, the general-purpose interface pins are configured as inputs with the pull structures active. For a detailed listing of the pull configuration and drive strength refer to Chapter 2.

Figure 4-25 GPIO_INT pad structure

d

>

q DATA_BUSGPIO_INT_OUT

write GPIO_INT_OUT

d

>

q DATA_BUSGPIO_INT_TSEN

res RESOUT

write GPIO_INT_TSENd

>

q

GPIO_INT_POLARITY

write GPIO_INT_POLARITY

= InterruptController

read GPIO_INT_IN

DATA_BUSGPIO_INT_IN

GPIO_INT

DATA_BUS

GPIO_INT PAD

013-061




4.8 UART, R-UIM

4.8.1 UART1

The Universal Asynchronous Receiver Transmitter (UART) communicates with serial data that conforms to RS-232 interface protocol. The UART (Figure 4-26) can be used as a serial data port in Mobile Station testing and debugging with an properly written, user-defined download program. If the Mobile Station uses EEPROM or Flash memory, the serial data port can be used to load and/or upgrade the system software. The serial data port can also be used to run Mobile Station diagnostic tests during the manufacturing process.

The serial data port is a UART channel. The UART processes both the transmit and the receive data, and interrupt control circuits, a clock generator, a bit-rate generator (BRG), and a microprocessor interface.

The UART1 has a 64-byte transmit (Tx) FIFO and a 64-byte receive (Rx) FIFO. The UART features hardware handshaking, programmable data sizes (5, 6, 7, or 8 bits), programmable stop bits (0.563, 1.000, 1.563, and 2.000), and odd, even, space, or no parity. The UART operates at a 230.4 kbps maximum bit rate.

Figure 4-26 UART block diagram

Tx FIFO

Tx ControlModule

Rx FIFO

Rx ControlModule

Receive Channel

Transmit Channel

ChannelControl

CTS_N

DP_TX_DATA

DP_RX_DATA

RFR_N

FIFOControl

FIFOControl

8

10

InterruptControl

ControlSignals

Status Data

ControlSignals

Status Data

Data

Data

UART_INTMicroprocessorInterface

Tx Data

8

108

2

BRG

ClockGenerator

andM/N Counter

TCXO/4(SLEEP_XTAL)

InternalMicroprocessor

Bus

Rx Data

Error

Bits

013-062





4.8.1.1 UART transmit cycle

The UART Tx channel contains a 64-byte Tx FIFO and a Tx control module. The Tx FIFO accepts parallel data from the microprocessor. The Tx control module reads data from the Tx FIFO and sends it out serially, adding a start bit, optional parity bits, and stop bit(s).

The Tx FIFO accepts characters from the microprocessor. The TXRDY bit in the Status Register (SR) sets (1) whenever the Tx FIFO has space available. The Tx channel asserts an interrupt (TXLEV) when the Tx FIFO has fewer than the number of characters programmed in the Transmit FIFO Watermark Register (TFWR).

Idling or disabling the Tx channel holds the DP_TX_DATA pin in a marking state (high). Enabling the Tx channel, with a character waiting in the Tx FIFO, loads that character into the Tx shift register. Next, a start bit is transmitted (Tx low) for one bit time, followed by each bit in the character, LSBit first, then the optional parity bit followed by stop bits (Tx high). The number of stop bits is programmable.

If after the previous transmission the Tx FIFO is not empty, the Tx control module begins another transmission by loading the next Tx FIFO character into the Tx shift register. If after the previous transmission the Tx FIFO is empty, the Status Register’s (SR) TXEMT (Tx empty) bit is set (1). Setting TXEMT indicates an underrun in the Tx channel. The TXEMT bit clears (0) once the transmit shift register has a new character from the Tx FIFO.

Setting (1) Command Register, CR:UART_TX_DIS, disables the Tx channel. When disabled, the Tx channel continues transmitting any character in the Tx shift register until the register is empty. When transmission ends, the DP_TX_DATA pin goes into a marking state (high). Setting (1) CR:UART_TX_EN re-enables the Tx channel.

Setting (1) MR1:CTS_CTC enables the Clear-To-Send (CTS_N) control signal. The Tx channel checks the CTS_N input before transmitting a character. If CTS_N is high, the waiting character is sent and the Tx channel continues marking. If CTS_N is low, transmission begins or continues. If CTS_N goes high in the middle of character transmission, the Tx channel waits for a completed transmission before entering the marking state. The Tx channel can generate a programmable interrupt whenever CTS_N changes states.

If the CR issues a ‘Start Break’ command, after the Tx channel transmits all the characters in the Tx FIFO and shift register; the Tx channel forces the DP_TX_DATA pin low. Until the CR issues a ‘Stop Break’ command, the DP_TX_DATA pin remains low.

When the CR issues a ‘Reset Transmitter’ command, it causes the Tx channel to cease transmitting. The DP_TX_DATA pin enters a marking state and flushes the Tx FIFO.




4.8.1.2 UART receive cycle

The receive channel contains a 64-byte Rx FIFO and a receive (Rx) control module. Each byte in the Rx FIFO has two bits of corresponding status information. The DP_RX_DATA pin inputs the serial data. The Rx control module converts the serial data into parallel data and loads it into the Rx FIFO.

If the Rx FIFO is not full, the control module writes the received character to the Rx FIFO. When the Rx control module writes a received character to an empty Rx FIFO, the RXRDY bit in the status register (SR) is set (1). If the Rx FIFO becomes full, the RXFULL bit sets (1). The RXFULL bit clears (0), when a character is read from the Rx FIFO. The RXRDY bit clears (0) when the Rx FIFO becomes empty once again. When the Rx FIFO has more characters than what was programmed in the Receive FIFO Watermark Register (RFWR), the Rx channel asserts a RXLEV interrupt. If a character is waiting in the Rx FIFO for a programmed time period (STALE_TIMEOUT), a RXSTALE interrupt occurs. The Rx channel asserts an RXHUNT interrupt whenever the Rx channel receives a character that matches the value found in the Hunt Character Register (HCR).

Two status bits are associated with each 8-bit data word in the Rx FIFO. One status bit defines the received break condition, the other status bit is the logical-OR of a parity error or framing error. MR2:ERROR_MODE determines the character error mode or the block error mode. In character error mode, the SR’s error bits apply only to the byte waiting to be read from the Rx FIFO. In block mode, the SR’s error bits are the logical-OR of all incoming error bits, since the Command Register (CR) last issued a ‘Reset Error Status’ command. Whether in character error mode or block mode, reading the status register has no effect on the Rx FIFO.

If the Rx FIFO is full and the Rx channel receives a new character, that character remains in the Rx shift register until a position becomes available in the Rx FIFO. Any additional incoming characters are lost, until space becomes available in the Rx FIFO. When characters are lost, an overrun error occurs and SR:OVERRUN is set (1). Once SR:OVERRUN is set (1), it remains set until the CR issues a ‘Reset Error Status’ command. An overrun error does not affect the Rx FIFO’s contents.

Setting CRUART_RX_DIS disables the receive channel. Incoming characters are now ignored, but characters already in the Rx FIFO remain unchanged and can be read by the microprocessor. Having the CR issue a ‘Reset Receiver’ command flushes the Rx FIFO and clears (0) the status bits. The receive channel remains disabled until it is re-enabled by setting (1) CR:UART_RX_EN.

Setting MR1:RFR_CTL enables the ‘Automatic Ready-For-Receiving’ (RFR_N) mode. In this mode, the RFR_N pin goes high when the Rx FIFO level is the same or greater than the value programmed in MR1AUTO_RFR_LEVEL. When the Rx FIFO level falls below the programmed RFR_N level, the RFR_N pin returns to a low state. This feature prevents overruns by connecting the channel’s RFR_N pin to a transmitting device’s CTS_N pin.





4.8.1.3 UART interrupt control

The Tx channel asserts DELTA_CTS and TXLEV interrupts while the Rx channel asserts the RXLEV, RXSTALE, RXBREAK and RXHUNT. The Interrupt Status Register (ISR) shows each interrupt’s status bit independent of the Interrupt Mask Register’s IMR bit state. The Mask Interrupt Status Register (MISR) returns the Bitwise AND of the ISR and IMR registers. The six UART interrupts generated by the ISR and IMR registers are described below. IMR bit 6 indicates the current state of the CTS input.

1. DELTA_CTS indicates that the CTS_N pin has changed state from high to low, or from low to high. The CURRENT_CTS (bit 6 in the ISR register) holds the actual value of the CTS_N pin. Setting (1) DELTA_CTS (bit 5 in the IMR register) enables the interrupt. The CR channel command Reset CTS_N clears (0) the DELTA_CTS interrupt status bit.

2. RXLEV indicates that the Rx FIFO has more characters than the programmed watermark threshold. To enable this interrupt, the RXLEV (IMR, bit 4) must be set (1) and an appropriate watermark threshold must be written to the RFWR. If the amount of characters read from the Rx FIFO is less than or equal to the programmed RFWR value, the RXLEV interrupt clears (0).

3. RXSTALE (IMR register, bit 3) shows that there are one or more characters in the Rx FIFO (but less than the level defined in RFWR) and they have been there longer than the timeout value specified by the IPR register. To enable RXSTALE, RXSTALE (IMR bit 3) must be set (1) and an appropriate timeout value must be written to the IPR register. This timeout value is determined by programming STALE_TIMEOUT, bits [7, 4:0]. The STALE_TIME_OUT value specifies how many character times must elapse before a Stale Character timeout is generated. In this instance, a character time is defined as 10 times the bit duration. The RXSTALE interrupt status bit clears each time a character is read from the Rx FIFO. The stale character interrupt duration is measured from either the first or the last arriving character in the Rx FIFO as programmed by the RXSTALE_LAST, bit 5 in IPR. Clearing (0) the RXSTALE_LAST bit measures the Rx Stale Character Timeout duration from the first arriving character in the Rx FIFO. Setting (1) this bit measures the duration from the last arriving character in the Rx FIFO. When RXSTALE_LAST is cleared (0), the value programmed in STALE_TIMEOUT is usually greater than the value programmed in RFWR; if the value is not greater, then STALE_TIMEOUT expires before the RFWR setpoint.

RXBREAK indicates that the Rx break-detect circuit detected the beginning of a new break condition, or the end of an existing break condition. Setting (1) the RXBREAK (IMR register, bit 2) enables the interrupt. The CR channel command “Reset Break” Change clears the RXBREAK interrupt status bit. A detected break is an all-zeros character with an invalid stop bit. The end of a break is a marking condition (1) at least 1/2 bit width. A detected break occupies one position in the Rx FIFO1.

1 The DP_RX_DATA pin has an internal pull-down. As such, a “no connect” on this pin is perceived as a break.




4. RXHUNT indicates that the RX FIFO has detected the special hunt character. To enable the RXHUNT interrupt, an appropriate hunt character must be written to the Hunt Character Register (HCR) and the RXHUNT (IMR register, bit 1) must be set (1). The CR channel command Reset Error Status clears the RXHUNT interrupt status bit.

5. TXLEV shows that the Tx FIFO has the same or fewer number of characters than the number programmed in the Tx watermark threshold. To enable this interrupt, TXLEV (IMR register, bit 0) must be set (1) and an appropriate number must be written to the Transmit FIFO Watermark Register (TFWR). The TXLEV interrupt status bit clears (0) after enough characters have been written into the Tx FIFO to bring the amount of characters equal to or more than the TFWR value.

4.8.1.4 Clock generator

The clock generator generates the UART clock. The clock comes from a dedicated M/N counter running off TCXO. This counter, defined by the MREG_MSB, NREG_MSB, DREG_MSB and MND_LSB registers, must be initialized before using the UART. Using the recommend M/N value, the clock runs at 1.8432 MHz. Writing the value 0 (zero) to the M registers cause the M/N counter to output a 0 Hz clock, effectively turning off the clock. This puts the UART into its power save mode. When the clock is disabled, none of the UART registers are accessible except for the M/N counter registers.

4.8.1.5 Bit-rate generator

The Bit-Rate Generator (BRG) generates enables to the Tx and Rx channels that are 16X the nominal bit rate. The BRG selects one of 16 possible bit rates defined in Clock Select Register and sends the selected bit rate to the Tx channel (CSR bits [3:0]) and Rx channel (CSR bits [7:4]). Table 4-17 assumes a system clock frequency of 1.8432 MHz. The bit rates are generated by dividing the UART system clock.

Table 4-17 Clock select register bit rates (TCXO/4 based)

CSR[7:4]CSR[3:0]

Bit Rate(bit/sec)

CSR[7:4] CSR[3:0]

Bit Rate (bit/sec)

0000 75 1000 7.2 k

0001 150 1001 9.6 k

0010 300 1010 14.4 k

0011 600 1011 19.2 k

0100 1.2 k 1100 28.8 k

0101 2.4 k 1101 38.4 k

0110 3.6 k 1110 57.6 k

0111 4.8 k 1111 115.2 k





4.8.1.6 Microprocessor interface

All communication between the microprocessor and the UART goes through the microprocessor interface. The microprocessor interface synchronizes the data and command signals to the UART. This interface runs off the TCXO/4 (4.8 MHz) as shown in Figure 4-26, to minimize wait states. After data aligns with the UART clock, the microprocessor interface presents the data on an internal bus to the other related circuits.

4.8.2 UART2

A second UART has been added to the MSM6000 which is available at the Auxiliary PCM CODEC Interface pins. A control bit determines the function of the AUX_PCM pins of the MSM6000. The multiplexing scheme is shown in Figure 4-27.

Table 4-18 Clock select register bit rates (TCXO based)

CSR[7:4]CSR[3:0]

Bit Rate(bit/sec)

CSR[7:4] CSR[3:0]

Bit Rate (bit/sec)

0000 300 1000 28.8 k

0001 600 1001 38.4 k

0010 1.2 k 1010 57.6 k

0011 2.4 k 1011 76.8 k

0100 4.8 k 1100 115.2 k

0101 9.6 k 1101 153.6 k

0110 14.4 k 1110 230.4 k

0111 19.2 k 1111 -




Figure 4-27 Multiplexing arrangement for UART2 and AUX_PCM signals

UART2_SEL, bit 5 of the CODEC_CTL2 write register, and bit 7 of the CODEC_CTL2 register are used in part to control the second UART.

A set of Control Registers control UART2. The Control Registers are identical to the control registers for the primary UART except for their addresses. The Control Registers functions for the primary UART are described in Chapter 4. For UART2, the register addresses are different but the function is identical to those for the primary UART, with the exception that the primary UART has 64-byte RX/TX FIFOs and the secondary UARTs FIFOs are 64 byte.

An Interrupt Status bit for UART2 is in the bit 9 position of the INT_STATUS_1 register.

Clock selection and enabling for UART2 as well as the UART2 system reset are subject to the same control bits as the primary UART. If only the primary UART is used, MSM6000 power consumption is reduced by turning off the M/N clock generator M/N counters via the UART2_MREG_MSB, UART2_NREG_MSB, UART2_DREG_MSB, and UART_MND_LSB registers.

4.8.3 R-UIM

The R-UIM is a smart card for CDMA cellular application. R-UIM provides personal authentication information that allows the MS or handset, to be connected with the network. The R-UIM card enables handset independence for the user. The R-UIM card can be inserted into any CDMA R-UIM equipped handset, allowing the user to receive or make calls and receive other subscribed services from any R-UIM equipped handset. For the MSM6000 to support UIM card reader, 3 pins are required: UIM_CLK, UIM_IO, and UIM_RESET. UIM_RESET can be implemented by using a GPIO_INT bit under software control. UIM_CLK and UIM_IO are hidden behind UART2 interface, which in turn is hidden behind either GPIO_INT or AUX_PCM interface. Table 4-19 and Table 4-20 describe the R-UIM pin configurations.

GPIO_UART2_SEL

GPIO_INT21

GPIO_INT21

GPIO_INT20

GPIO_INT19

GPIO_INT18

UART2

AUX_PCM_DOUT

AUX_PCM_DIN

AUX_PCM_CLK

AUX_PCM_SYNC

GPIO_INT20GPIO_INT19GPIO_INT18

DP Rx Data2

CTS_N2

Data inData outClockSync

UART2_SEL

089-034

AUX. PCMInterface

(RFR_N2)UIM_DATR_UIM

UIM_SEL

(DP Tx Data2)UIM_CLK p





1: When the R-UIM function is selected as alternate functions for GPIO_INT(18:21) pin group, GPIO_INT18 and GPIO_INT20 are not available as independent GPIO_INTs.

2: R-UIM and UART2 cannot be used simultaneously. When R-UIM is enabled and assigned to AUX_PCM pins, the UART2 cannot be used from the GPIO_INT(18:21).

Table 4-19 GPIO_INT pins1

Primary Pin R-UIM UART2

GPIO_INT_18 --1 CTS_N2

GPIO_INT_19 UIM_CLK RFR_N2

GPIO_INT_20 --1 DP_RX_DATA2

GPIO_INT_21 UIM_IO DP_TX_DATA2

Table 4-20 AUX_PCM pins2

Primary Pin R-UIM UART2

AUX_PCM_SYNC --2 CTS_N2

AUX_PCM_CLK UIM_CLK RFR_N2

AUX_PCM_DIN --2 DP_RX_DATA2

AUX_PCM_DOUT UIM_DATA DP_TX_DATA2

Figure 4-28 Multiplexing arrangement for UART2 and AUX_PCM signals

GPIO_UART2_SEL

GPIO_INT21

GPIO_INT21

GPIO_INT20

GPIO_INT19

GPIO_INT18

UART2

AUX_PCM_DOUT

AUX_PCM_DIN

AUX_PCM_CLK

AUX_PCM_SYNC

GPIO_INT20GPIO_INT19GPIO_INT18

DP RX DATA2

CTS_N2


UART2_SEL

013-022

AUX. PCMInterface

RFR_N2 or UIM_CLKR_UIM

UIM_SEL

DP_TX_DATA2 or UIM_DATA




4.8.3.1 UIM_GLUE block

The UIM_GLUE block is responsible for the following three tasks:

1. Informing the transmitter that parity error has occurred.

2. Re-transmit of the corrupted data.

3. Inverting and/or swapping the order of data bits

4.8.3.2 Receive error

The receiver pulls the data line to indicate to the transmitting side that parity error had occurred during transmission of the character. The receiver pulls the data line low for 1 etu minimum and 2 etu maximum (see Figure 4-29). When the R-UIM interface is not used, the receive error detection is disabled.

4.8.3.3 Retransmit data

According to ISO/IEC-7813-3 requirements, the transmitting side has to sample the data line at the (11±0.2) etu after the leading edge. If the data line is HIGH, the correct transmission is assumed; if, however, the line is LOW, the transmission is assumed to have been incorrect, and the disputed character has to be retransmitted after a delay of at least 2 etu after detection of the error signal (see Figure 4-29).

Figure 4-29 Byte transmission diagram

istart parity Guardtime start i+1

0etu 1etu 2etu 3etu 4etu 5etu 6etu 7etu 8etu 9etu 10etu 11etu 12etu 13etu 14etu 15etu 16etu

istart parity ErrorSignal

start i

0etu 1etu 2etu 3etu 4etu 5etu 6etu 7etu 8etu 9etu 10etu 11etu 12etu 13etu 14etu 15etu 16etu

Transmitter

b) parity error

Transmitter

a) no parity error

byte byte

bytebyte

013-063





4.8.3.4 Swap-invert data

Depending on the initial character received by the UIM interface, direct or inverse convention will be applied to the received data characters. The data byte, stripped of framing and parity, can be inverted, read in the inverse order, or both; and passed back to the Control block to be read by the microprocessor.

4.9 User interfaceThe User Interface of the MSM6000 consists of:

! Keypad[4:0]

! Ringer

! LCD interface

! Auxiliary CODEC Interface

4.9.1 Keypad interface

The KEYSENSE[4:0] pins can be used to connect a matrix keypad to the MSM6000. The KEYSENSE[4:0] inputs assert a KEYSENSE_INT if any of the pins are pulled low. Figure 4-30 shows the circuits associated with KEYSENSE[4:0].

Figure 4-30 KEYSENSE[4:0] circuits

KEYSENSE4 KEYSENSE_READ[4]

VDD_P

(Internal Pullups)





KEYSENSE_INT(to Interrupt Control)

089-042




4.9.2 Ringer

The Ringer generation circuit is programmed to output single tones or DTMF tone pairs on the RINGER pin. The Ringer generation circuit produces and sums two different user-programmable frequencies. Single tones can be generated by programming two tones of the same frequency. The Ringer function is disabled when RESOUT is asserted.

Figure 4-31 is the Ringer generation circuit block diagram. Each M/N counter is clocked by a 300 kHz clock derived from a 19.2 MHz TCXO. The Ringer generation circuit also controls the envelope for the ring output waveform. The signal on the RINGER pin is a digital pulse stream. The RINGER output generally requires an external booster circuit, such as the one shown in Figure 4-32, to drive a sound transducer. The equivalent circuit is integrated into the PM6000/PM6050.

Figure 4-31 Ringer generation circuit

Figure 4-32 External driver circuit example

M/N Counter Aclk

300 kHz

M/N Counter Bclk

RINGERoff TCXO/4

out

089-039

From RINGERPin of MSM6000

VDD_P

10k

2.2k

4.7k

4.7k

4.7 Ohms

0.01 µF Current-operatedSound Transducer

089-026





To generate DTMF tones on the RINGER output, M, N, and D values must be written into the two identical M/N counters. M is a 6-bit value, N is a 13-bit value, and D is a 12-bit value. The 6-bit M value (RINGER_MN_A_MDIV:RINGER_MN_A_MDIV) is written along with the enable for the counter (RINGER_MN_A_MDIV:RINGER_MN_A_EN) to the A counter M value register. RINGER_MN_A_NDIV is written to the A counter N-value register as the one’s-complement of the N minus M value. The D value in RINGER_MN_A_DUTY is written to the A counter D value register. These register allocations are identical for the B counter. Table 4-21 lists the decimal values for M and N which are used to program the M/N counters for DTMF tones. The frequencies produced are accurate to better than 1.5% of their specified values for a TCXO/4 of 4.8 MHz.

The DTMF frequency is found by multiplying the ratio M/N (decimal equivalent values) by the clock frequency of 300 kHz. The one’s-complement of (N minus M) value is the actual value for programming the N register to get the desired N value. The D value acts as a loudness control. Maximum RINGER loudness is set by using a D value which is 50% of the value in the N column. Softer ringing is achieved by decreasing or increasing the D value.

Table 4-21 Standard DTMF frequencies and ringer programming values

DTMF Frequency (Hz)

M/N(dec)

M(hex)

N (hex)

1’s complement of(N minus M) (hex)

D Duty-Cycle (50% of N) (hex)

350 7 / 6000 07 1770 0896 BB8

440 7 /4772 07 12A4 0D62 952

480 8 /5000 08 1388 0C7F 9C4

620 16 / 7742 10 1E3E 01D1 F1F

697 17 / 7317 11 1C95 037B E4A

770 20 / 7792 14 1E70 01A3 F38

852 12 / 4225 0C 1081 0F8A 840

941 9 / 2869 09 0B35 14D3 5A9

1209 32 / 7940 20 1F04 011B F82

1336 6 / 1347 06 0543 0AC2 2A1

1477 26 / 5281 1A 14A1 0B78 A50

1633 23 / 4225 17 1081 0F95 840




Each counter (A and B) is enabled by setting (1) bit 6 of the M register. For counter A, this is RINGER_MN_A_EN in the RINGER_MN_A_MDIV register, for counter B it is RINGER_MN_B_EN in the RINGER_MN_B_MDIV register. Setting bit 6 of the M register, resets both counters (CNTR_A and CNTR_B) to start counting at the same time. Both counters can be programmed to generate the same or different frequencies. Clearing (0) bit 6 disables both counters. These M register bits have an edge detect for a zero-to-one transition. To generate a single tone, the counters are phase-locked by clearing bit 6 of both M registers every time the counters are programmed. Bit 6 must be cleared (0) before the N and D registers are programmed and remain cleared for at least 1 ms. The last step of the programming sequence is to set each bit 6 along with its corresponding M value. This triggers the synchronization mechanisms. The standard DTMF keypad tone combinations are listed in Table 4-22.

Table 4-22 Keypad frequencies

Keypad Counter A Frequency (Hz)

Counter B Frequency (Hz)

1 697 1209

2 697 1336

3 697 1477

4 770 1209

5 770 1336

6 770 1477

7 852 1209

8 852 1336

9 852 1477

* 941 1209

0 941 1336

# 941 1477

A 697 1633

B 770 1633

C 852 1633

D 941 1633





4.9.3 LCD_CS_N and LCD_E

LCD data is valid when LCD_E is asserted while LCD_CS_N is low. LCD_E pin behavior depends on the wait states programmed into the LCD_CTL register (0x09C). When LCD_E_SETUP expires, LCD_E asserts high and remain high until LCD_E_HIGH expires. LCD_E then de-asserts low. Figure 4-33 illustrates the relationship of LCD_CS_N and LCD_E.

Figure 4-33 LCD interface timing

tLCDES

tLCDEH

tLCDEHI

D[15:0]

T

MCLK

ADDR[20:0]

LCD_CS/

LCD_E

Data[15:0]

WAIT[n]

LCD_E_SETUP[n]

LCD_E_HIGH[n]

LCDES: minimum of (0.5T – 15 + nTW) nanoseconds (time period determined by value of LCD_E_SETUP).

LCDEHI: maximum of (T + nTW) nanoseconds (time period determined by value of LCD_E_HIGH).

LCDEH: maximum of (T + nTW + TW) nanoseconds.013-067




4.9.4 M/N counter

Figure 4-34 shows the block diagram of the GP_MN M/N counter.

Figure 4-34 GP_MN block diagram

To create an output frequency, _, with a given duty cycle, D, the following sequence must be used to initialize the GP_MN M/N counter:

1. Solve for decimal values for M and N. The value of M cannot exceed the value of N.

2. Convert the decimal values for M and N into a 9-bit value for M and an 13-bit value for N.

3. Write the 9-bit M value into GP_MN_CLK_MDIV.

4. Write the 13-bit result of the one’s complement value of N minus M into GP_MN_CLK_NDIV. In other words, GP_MN_CLK_NDIV = 0x1FFF – (N – M).

5. Write the desired 13-bit duty cycle value, D, into GP_MN_CLK_DUTY. A 50% duty cycle output waveform is generated when: GP_MN_CLK_DUTY = N/2.

GP_MN can also be used as a programmable digital output. Table 4-23 shows a set of values and the resulting GP_MN output state.

Table 4-23 Using GP_MN as a digital output

GP_MN Output State GP_MN_CLK_MDIV GP_MN_CLK_NDIV GP_MN_CLK_DUTY

LOW 0x00 0x1000 0x1FFF

HIGH 0x00 0x1000 0

GP_MN_CLK_DUTY

GP_MN_CLK_MDIV

GP_MN_CLK_NDIV(programmed with the1's complement of N - M)

Counter

Count Value

LoadValue

CountLoad/

Full Adder

Carry-in (1)

UnsignedComparator

BA A B

Sum

MSB of Sum

TCXO/4

13

13

139

13

GP_MN

13089-027





4.9.5 Auxiliary PCM interface

The Auxiliary PCM Interface enables communication with an external Codec that provides the hardware support for hands free applications. Both mu-law and A-law Codecs are supported by the Aux PCM interface. The interface does not support linear Codecs.

The auxiliary Codec port operates with standard long-sync timing and a 128 kHz clock. The AUX_PCM_SYNC runs at 8 kHz with 50% duty cycle. Most mu-law and A-law CODEC’s support the 128 kHz AUX_PCM_CLK bit clock.

The ONES_DETECT state machine is clocked by CLKOUT of the internal ARM7TDMI microprocessor. The logic is controlled by CODEC_CTL:ONES_POLARITY with a single output of WEB_MISC_RD:ONES_DETECT. In addition, this logic can also generate an AUX_PCM_DIN_INT interrupt. This interrupt is asserted when the value on the AUX_PCM_DIN pin matches that of the ONES_POLARITY bit. To enable or disable this interrupt, respectively set (1) or clear (0) AUX_PCM_DIN_INT_EN in either IRQ_MASK_0 or FIQ_MASK_0. If ONES_POLARITY=0, then a high on AUX_DIN guarantees ONES_DETECT=0. If ONES_POLARITY=1, then a low on AUX_DIN guarantees ONES_DETECT=1.

The Auxiliary PCM Interface and the UART2 interface are multiplexed on the same four pins of the MSM6000. CODEC_CTL_:UART2_SEL selects which block of the MSM6000 drives these pins. Setting (1) this bit select the AUX_PCM_DIN, AUX_PCM_CLK, AUX_PCM_SYNC, and AUX_PCM_DOUT. Clearing (0) this bit select the DP_RX_DATA2, RFR_N2, CTS_N2, DP_TX_DATA2.

Figure 4-35 Auxiliary PCM interface

AUX_PCM_DOUT (DP_TX_DATA2)

AUX_PCM_DIN (DP_RX_DATA2)

AUX_PCM_CLK (RFR_N2)

AUX_PCM_SYNC (CTS_N2)

Dp Tx Data2Dp Rx Data2RFR_N2CTS_N2


UART2_SEL

MCLKONES_POLARITY

ONES_DETECT

AUX_PCM_DIN_INT013-069

UART2

AUX. PCMInterface

ONES DETECT




4.10 GPADC functional descriptionThe MSM6000 has an on-chip 8-bit analog-to-digital converter (GPADC) which is intended to digitize DC signals corresponding to analog parameters such as battery voltage, temperature, and RF power levels. The general functional diagram of the MSM6000’s GPADC is shown in Figure 4-36.

The MSM6000 has 7 analog input pins (HKADC[6:0]) which are multiplexed to the input of the internal GPADC. An eighth analog input is connected to an internally generated 1.86 Volt source. The analog multiplexer is switched by three control bits, ADC_MUXSEL[2:0] found in the HK_CONFIG register. The multiplexer select bits are read from the RD_SEL[2:0] bits in the ADC_STAT Register.

Figure 4-36 GPADC configuration in the MSM6000

000

001

010

011

100

101

110

111

HKADC0

HKADC1

HKADC2

HKADC3

HKADC4

HKADC5

HKADC6

8-bit

ADC

3SEL[2:0]

000

001

010

011

1xxVDD_A (MSM6000 pin M16,N17)

Vin

Vref

GP ADC Clk

ADC_MUXSEL[2:0]

3

2

8

RD_SEL[2:0]

DIV/M

TCXO/4

DIV[1:0]

1 0

SLEEP CLK

Dout HK_DATA[7:0]

EOC ADC_EOC

Vext

UART_SBI_CLK_SEL

1.86 V

1.24 V

0.62 V

Vref

Gen

089-028





4.10.1 Analog input voltage range

The input voltage range of the ADC on the MSM6000 is programmable to three fixed ranges as well as two other ranges determined by off-chip voltage sources. The analog input range is set by selecting the voltage reference of the ADC (Vref) via the SEL[2:0] control bits found in the HK_CONFIG Register (see Figure 4-36).

In the case of SEL[2:0] = 011, the reference voltage to the GPADC is input on the HKADC6 pin. The maximum voltage that can be applied to the HKADC6 pin is VDD_A [V]. The minimum voltage that can be applied is 0.62 Volts. In the case of SEL[2:0] = 1xx, the reference voltage to the GPADC is VDD_A (the voltage on pin M16, N17 of the 208-ball FBGA package).

Table 4-24 shows the transfer function of the ADC under 5 different Vref conditions.

Table 4-24 MSM6000 ADC transfer function

Input Voltage Range and Vref set by SEL[2:0] =8-bit Digital

Output Result (HK_DATA[7:0]

000 001 010 011 1xx

Vref = 1.86 V Vref = 1.24 V Vref = 0.62 V Vref = Vext Vref = VDD_A

>1.860 >1.240 >0.620 >Vext >VDD_A 0xFF

1.860 1.240 0.620 (255/255)Vext (255/255)VDD_A 0xFF

1.853 1.235 0.618 (254/255)Vext (254/255)VDD_A 0xFE

1.408 0.939 0.469 (193/255)Vext (193/255)VDD_A 0xC1

1.400 0.934 0.467 (192/255)Vext (192/255)VDD_A 0xC0

1.393 0.929 0.464 (191/255)Vext (191/255)VDD_A 0xBF

0.941 0.627 0.314 (129/255)Vext (129/255)VDD_A 0x81

0.934 0.622 0.311 (128/255)Vext (128/255)VDD_A 0x80

0.926 0.618 0.309 (127/255)Vext (127/255)VDD_A 0x7F

0.474 0.316 0.158 (65/255)Vext (65/255)VDD_A 0x41

0.467 0.311 0.156 (64/255)Vext (64/255)VDD_A 0x40

0.460 0.306 0.153 (63/255)Vext (63/255)VDD_A 0x3F

0.007 0.005 0.002 (1/255)Vext (1/255)VDD_A 0x01

0.000 0.000 0.000 0.000 0.000 0x00




4.10.2 GPADC dperation

The analog-to-digital conversion process of the GPADC requires 16 cycles of the GPADC Clk. The general GPADC conversion process is shown in Figure 4-37. The GPADC must be enabled and powered up for at least 5 microseconds prior to the beginning of any conversion. Once the power-up requirement has been met, the first step in the conversion process is to switch the analog input multiplexer to the desired channel by writing the ADC_MUXSEL[2:0] bits in the HK_CONFIG register. This takes one GPADC clock cycle to accomplish before a conversion is initiated.

A conversion is initiated by writing to the ADC_DATA_WR register. The analog signal level to be converted is acquired during the next three GPADC Clk cycles. This time is required to charge the internal sampling capacitor which holds the DC level for the remainder of the conversion process. Eight clock cycles are required after signal acquisition to determine the 8-bit final result. There are 4 clock cycles of latency at the end of the conversion process to allow the result to propagate to the ADC_DATA[7:0] register. When ADC_EOC sets (1), the 8-bit result is available for reading from the ADC_DATA[7:0] register.

Figure 4-37 General GPADC conversion process

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

GP ADC Conversion Cycle

GP ADC Clk

Change Input Mux

Analog channel

Initiate Conversion

Conversion Process

ADC_EOC

ADC_DATA[7:0]

Acquisition Conversion

Data from previous conversion New Data

ADC_MUXSEL[2:0] for new conversion

Latency

013-070





4.10.3 GPADC conversion time

The conversion time of the GPADC is directly related to the frequency of the GPADC Clk which depends upon the frequency of the clock source selected and the divide factor programmed. Since the MSM6000 device is designed for TCXO frequency of 19.2 MHz, Table 4-25 is arranged to show the conversion time of the GPADC as it relates to the TCXO frequency.

When one of the internally generated Vref sources (1.86, 1.24, or 0.62 Volts) is selected for the GPADC, the maximum frequency for the GPADC Clk signal is 300 kHz. To limit the GPADC Clk to 300 kHz when using the TCXO/4 as the clock source, the divide ratio must be set to 16 (DIV[1:0] = 11).

When one of the off-chip Vref sources (VDD_A or Vext) is selected for the GPADC, the maximum frequency for the GPADC Clk is 1.2 MHz. Table 4-25 shows the settings of DIV[1:0] which is used when VDD_A or Vext are used for the Vref of the GPADC. (VDD_A and Vext must have source resistances of 50 Ohms or less).

NOTE For DIV[1:0] = 10 or 01, the GPADC Vref must be input on HKADC6 or VDD_A from a voltage source with source resistance no greater than 50 Ohms.

Table 4-25 ADC timing for TCXO/4 = 4.8 MHz (TCXO = 19.2 MHz)

ADC Clock Divider TCXO = 19.20 MHz

DIV[1:0] Divide Ratio

ADC Clock Frequency

Conversion Time

11 16 300 kHz 53.33 µs

10 8 600 kHz 26.67 µs

01 4 1.2 MHz 13.33 µs

00 2 — —




4.10.4 GPADC analog interface considerations

For HKADC[6:0] input pins that are not selected by the GPADC input multiplexer, the impedance is very high and the MSM6000 pins present essentially no load to external circuits connected to these pins. Figure 4-38 illustrates the equivalent circuit of the GPADC input and the circuits that are designed to drive the HKADC[6:0] pins. The input multiplexer selects an input pin by closing S1. When a conversion is initiated, S2 stays closed until the end of the acquisition interval (3 GPADC Clk cycles). After acquisition, S2 opens and the DC voltage to be converted is held on the sampling capacitor, Cs. The GPADC requires a dummy acquisition after reset in order for the mux selection to be valid. The HKADC[6:0] pins are all active after reset.

Figure 4-38 Equivalent circuits for GPADC input and external voltage sources

During the acquisition interval, the external circuit connected to the selected HKADC pin must supply enough current to charge Cs through the 5 kOhm (maximum) on-resistance of the input multiplexer. For accurate conversion results, the voltage on Cs must settle to within 0.25% of its final value (~1/2 LSB) in acquisition interval.

The relationship that must be met is given by:

7 x (Rs + Rin) x Cs < 3 / fADC Clk

This relationship is used to determine the maximum source resistance of the external circuits driving the HKADC input pin. Examples of this relationship are shown in Table 4-26.

Table 4-26 Recommended Rs maximum values

fADC Clk Rs max. CLK Conditions Vref Conditions

300 kHz 50 Ohm TCXO = 19.2 MHz Internal 1.86, 1.24, or 0.62 Vref is selected.

300 kHz 100 kOhms TCXO = 19.2 MHz VDD_A or Vext selected for Vref. (Source resistance of VDD_A or Vext is < 50 Ohms)

600 kHz 50 kOhms TCXO = 19.2 MHz VDD_A or Vext selected for Vref. (Source resistance of VDD_A or Vext is < 50 Ohms)

1.2 MHz 25 kOhms TCXO = 19.2 MHz VDD_A or Vext selected for Vref. (Source resistance of VDD_A or Vext is < 50 Ohms)

V

MSM6000

HKADCxRs

RinVADC

Battery orTemperaturetransducer circuit

Input Mux

S1Cs

ACQ

S2HKADCx

HKADCx

089-029





4.11 Clock regimesThe MSM6000 derives all of its internal clock sources from two clock inputs, TCXO and SLEEP_XTAL. The TCXO clock input supports the frequency 19.2 MHz. An integrated PLL and digital divider are used to create the required clock sources when the TCXO frequency is 19.2 MHz. The SLEEP_XTAL can support a 32.768 kHz clock source to drive the sleep controller during periods when most of the MSM6000 is powered down and the TCXO is disabled.

4.11.1 TCXO

The MSM6000 device integrates a phase-locked loop and an M/N counter to derive CHIPX16 and CHIPX8 from the TCXO clock input.

4.11.2 SLEEP crystal circuit for 32.768 kHz

The MSM6000 contains a SLEEP oscillator circuit used as a clock source when other clocks are disabled to conserve power.

Bits 11:10 of MSM_CLK_CTL4 (address 74C) control the gain of the internal inverter in the MSM6000’s SLEEP oscillator circuit. Bits 11:10 are collectively called SLEEP_OSC_GAIN. Table 4-27 shows the gain settings of the inverter.

Bit 9 of MSM_CLK_CTL4, called SLEEP_OSC_RF_BYPASS controls the feedback resistance between the input and output of the internal inverter. Set (1) SLEEP_OSC_RF_BYPASS to disable the feedback path. Clear (0) SLEEP_OSC_RF_BYPASS to enable the feedback path.

Bit 8 of MSM_CLK_CTL4, called SLEEP_OSC_RD_BYPASS controls the series resistance between the output of the internal inverter, and the SLEEP_XTAL_OUT pin. Set (1) this bit to disable series resistance between the inverter’s output and the SLEEP_XTAL_OUT pin. Clear (0) this bit to enable series resistance between the inverter’s output and the SLEEP_XTAL_OUT pin

Table 4-28 summarizes the suggested settings of bits 11:8 of MSM_CLK_CTL4. Switches S1 and S2 refer to the switches in the figures shown below in the next section. MSM_CLK_CTL4 is a write-once register, the register values can only be changed on the first write after system reset. Subsequent writes to MSM_CLK_CTL4 have no effect.

Table 4-27 SLEEP oscillator inverter relative gain settings

SLEEP_OSC_GAIN:MSM_CLK_CTL4 (bits 11:10 of MSM_CLK_CTL_4)

Relative Gain (dB)

00 Reference

01 16

10 24

11 30




Figure 4-39 shows an example 32.768 kHz SLEEP passive crystal circuit configuration with load capacitors. The inverter’s gain is at its lowest setting. S1 is closed, enabling the inverter feedback path. S2 is open, enabling the series resistance between the inverter’s output and SLEEP_XTAL_OUT.

The SLEEP oscillator circuit also supports an external, active oscillator circuit. To configure the SLEEP oscillator circuit for an external active oscillator, set the gain of the inverter is at it’s maximum, producing fast transitions at the input of the output of the inverter. Open S1, disabling the inverter’s feedback path, thus reducing power consumption. Open S2, enabling the series resistance between the output of the inverter and the SLEEP_XTAL_OUT pin. Leave the SLEEP_XTAL_OUT pin unconnected.

Table 4-28 Suggested MSM_CLK_CTL4 settings of bits 11:8

Sleep Crystal Frequency and Configuration

Switch and Gain Settings

MSM_CLK_CTL4, bits 11:8

32.768 kHz, Passive Crystal S1 closed, S2 open

Gain: reference

0000

32.768 kHz, External, Active Oscillator Circuit

S1 open, S2 open

Gain 24

1010

Figure 4-39 SLEEP oscillator circuit with passive crystal

C L

C L

SLEEP_XTAL_IN

MSM6000

SLEEP_XTAL_OUT

S1R f

Rd

S2

InternalDivide-by-64

089-030





If the active oscillator has an open-drain output, care must be taken in choosing the pull-up resistor. QUALCOMM has found in tested configurations, the pull-up resistor must be less than 20 kOhms. If the output of the external oscillator circuit drives both high and low, the pull-up resistor is not required.

4.11.3 Subsystem clock regimes

Each clock regime is separately enabled, initialized and reset by the MSM_CLK_CTL registers. Table 4-30 lists the register bit selection for MSM_CLK_CTL[3:1], the subsystem that it controls and the clock source options. Table 4-29 defines the clock origins.

Table 4-29 Descriptions of clock origins

Clock Description

CHIPX16 Output of the PLL divided by 5

CHIPX8 Output of the CHIPX16 divided by 2

PLLOUT Output of the TCXO PLL

TCXO/4 TCXO input divided by 4

TCXO TCXO input

SLEEP Sleep Oscillator Output

Table 4-30 MSM6000 clock regimes

NameBit n of

MSM_CLK_CTL (1,2,&3)

MSM6000 Subsystem Clock Source(s)

CDMA_PDM 15 (in CDMA mode) TX_AGC_ADJ

CHIPX16

CDMA_AGC 14 TRK_LO_ADJ CHIPX8

RESERVED 13 — —

CODEC 12 CODEC cpll_out, pllout_div*

RESERVED 11 — —

RESERVED 10 — —

CDMA_RXDSP 9 Decoder Demodulator

TCXO, CHIPX8

SBI 8 SBI Controller TCXO/4, SLEEP

RESERVED 7 — —

VOC 6 Vocoder TCXO, PLLOUT, SLEEP_PLL




CODECIF 5 PCM Interface CPLL_OUT

DFM 4 (in DFM mode) TX_AGC_ADJ TRK_LO_ADJ

TCXO

CDMA_RX 3 Searcher Combiner FFE

CHIPX8

CDMA_TX 2 Modulator Interleaver

CHIPX8

UART 1 UART1 UART2 GPADC

TCXO/4, SLEEP

GENERAL 0 Ringer, Timetick, PDM1, PDM2, YAMN1

TCXO/4, SLEEP

ARM NA ARM microprocessor TCXO, PLLOUT, SLEEP_PLL

SLEEP NA Sleep Controller TCXO/4, SLEEP

Table 4-30 MSM6000 clock regimes (continued)

NameBit n of

MSM_CLK_CTL (1,2,&3)

MSM6000 Subsystem Clock Source(s)





4.12 JTAG interfaceThe JTAG Interface on the MSM6000 aids in Mobile Station board-level testing, and debugging.

Referring to the IEEE 1149.1A-93 manual: IEEE Standard Test Access Port and Boundary-Scan Architecture, the compliance clause defines how compliance with this standard is “switched on” or “switched off.”

TMODE is used as the compliance-enable input. This pin has a pull-up so that in the normal mode MSM6000 is JTAG specification compliant and the MSM Tap controller is active in this mode. If TMODE is driven low then the ARM JTAG port is selected.

NOTE This implementation does not conform to the IEEE 1149.1-90 standard. This implementation conforms to the IEEE 1149.1A-93.

It is important to note that the tap controller which is not selected is held in the TEST_LOGIC_RESET state. This is because the de-multiplexed TMS pin is held at a logic level of ‘1’ and since TCK is continuously provided to both, it holds it in a RESET state. This also meets the requirement that it is not required to apply TRST_N in order to reset the tap controllers.

The JTAG interface allows test instructions and test data to be shifted into the MSM6000, and the test results shifted out in a serial format.

There are four main functional elements in the JTAG Interface: a Test Access Port (TAP), a TAP controller, an Instruction Register, and a group of Test Data Registers. Figure 4-41 is a block diagram of the JTAG Interface.

Figure 4-40 MSM6000 JTAG interface

ARM7TDMIJTAG Interface

TDOTMS

TDI TCK TRST_N OE

MSM6000JTAG Interface

TDOTMS

TDI TCK TRST_N OE

TDITCK

TRST_N

TMS TDO

TMODE

0

1

0

1

0

1

089-031




4.12.1 Test access port

The JTAG Interface is accessed through the Test Access Port (TAP). The TAP includes the following input and output (I/O) pins:

! TCK (test clock input)

! TMS (test mode select input)

! TDI (test data input)

! TDO (test data output)

! TRST_N (test reset input)

The TAP dedicates all its I/O pins to the JTAG interface, these pins have no other use on the MSM6000.

TCK is a user defined clock input for the JTAG Interface. TCK is independent of the system clock, it supplies a clock input to the serial test path between TDI and TDO. TCK also permits shifting of test data concurrent with MSM6000 system operation. The independent TCK clock ensures that test data is shifted into and out of the TAP without changing the state of the MSM6000.

The TAP controller decodes the TMS input to set up test operations. TMS is sampled on the rising edge of TCK. When unconnected, the TMS input is a logic high (via an internal pull-up) to ensure that the MSM6000 continues operating without interference from the test logic.

Figure 4-41 JTAG interface block diagram

TAP Controller

Instruction Decode

Instruction Register (IR)

Bypass Register

Device Identification Register

Boundary Scan Register

Mux TDO

TAP Control SignalsTMS

TRST_N

TCK

TDI

013-074





TDI is the TAP input for serial test instructions or test data. TDI is sampled on the rising edge of TCK. TDI and TDO are the input and output ports for serial test data through the MSM6000. Data propagates from TDI to TDO without inversion. When unconnected, the TDI input is a logic high (via an internal pull-up). This ensures that open-circuit faults in the board-level, and the serial test data path forces a defined logic value to be shifted into the TAP.

TDO outputs the TAP serial test data. To ensure race-free operation, changes on TDO occur on the falling edge of TCK, while changes on the TAP inputs (TMS and TDI) occur on the rising edge of TCK. TDO is three-stated unless the data scanning is in progress.

The TRST_N input asynchronously resets the TAP controller when driven to a logic low. When TRST_N is low, all other test logic is asynchronously initialized. When unconnected, the TRST_N input is a logic high (via an internal pull-up).

4.12.2 TAP controller

The TAP controller is a synchronous finite state machine that responds to changes in the TMS and TCK signals The TAP controller controls a sequence of operations. Its TAP state machine has 16 states, allowing both data and instructions to be shifted. There are states for capturing, shifting, and updating data and instructions, a state for running tests, and a reset state.

The TAP Controller initializes when it is in the Test-Logic-Reset state. There are two ways to get the TAP Controller into the Test-Logic-Reset state:

! Applying a logic low to TRST_N brings the TAP Controller asynchronously into the Test Logic Reset state.

! Holding the TMS high, while allowing at least five rising edges of TCK to occur, brings the TAP Controller synchronously into the Test Logic Reset state. This is the worst case time to reach the Test Logic Reset state from any other state in the TAP controller.

Once in the Test-Logic-Reset state, all test logic disables and normal MSM6000 operations occur.

For board-level designs where JTAG testing is not used, TRST_N must be a logic low (externally pulled low by a low value resistor or tied to VSS). Before using the MSM6000 in a Mobile Station application, TRST_N must be low at power-up; or the TAP Controller must be in the Test-Logic- Reset state.

4.12.3 Data registers

There are three Data Register types included in the MSM6000 JTAG Interface: Device Identification Register, Bypass Register, and Boundary Scan Register.




4.12.3.1 Device identification register

The Device Identification Register is a 32-bit register holding the device’s Manufacturer Identity Code, Part Number, and Version data. The upper nibble of the Device ID register (the “version” field) is supplied by the lower nibble of the HARDWARE_REVISION_NUMBER register. The LSBit is the Device ID register’s start bit and is set to a logic 1. The Manufacturer Identity Code (bits [11:1]) is a manufacturer coding scheme administered by JEDEC (Joint Electron Device Engineering Council). QUALCOMM’s manufacturing code is 0x70. The Part Number (Bits [27:12]) is a QUALCOMM-generated number (0x2F for the MSM6000). The Version number (Bits [31:28]) is a QUALCOMM-generated number 0x0. Selecting the Device Identification register, loads its value into the shift register on the rising edge of TCK in the Capture-DR state. The Device Identification register does not have a parallel output. Figure 4-42 shows the structure of the Device Identification Register.

Figure 4-42 Data structure for device identification register

4.12.3.2 Bypass register

The Bypass Register is a single-shift register stage located between TDI and TDO. The Bypass Register is used to route boundary scan data directly from TDI to TDO without going through the entire Boundary Scan Register. Bypassing the Boundary Scan Register allows more rapid movement of test data to and from other components on a board. Selecting the Bypass Register, loads the shift register with a logic low on the rising edge of TCK; following entry into the Capture-DR state. The Bypass Register does not have a parallel output.

4.12.3.3 Boundary scan register

The Boundary Scan Register allows board interconnection testing to detect typical defects, like opens and shorts. The Boundary Scan Register connects between each digital I/O pin and the MSM6000 internal circuits; to allow I/O access when testing system logic, or to sample system I/O signals. The Boundary Scan Register also handles parallel input and outputs.

31 28 27 12 11 1 0

(4 bits) (16 bits) (11 bits)

1Part NumberVersion Mfg. ID Code

LSBMSB

089-033

HEX

BIN

(0 0 2 F)H

0000 0000 0010 1111

(0 E 1)H

0000 1110 000 1

(0)H

0000

(1 bits)





4.12.3.4 Boundary scan cells

The Boundary Scan Register contains cells that access digital signals (Table 4-31) at the MSM6000. Figure 4-43 shows a typical schematic diagram of a single boundary scan cell and its control signals.

4.12.4 JTAG instructions

The Instruction Register (IR) holds JTAG instructions that were shifted into the JTAG Interface. A JTAG instruction shifts though TDI, LSB first. In the IR, the JTAG instruction is used to select the test to be performed and/or the test data register to be accessed.

The IR is a 7-bit shift register having a serial input and parallel latched output. The parallel output holds the current instruction and is updated on the falling edge of TCK (when in the Update-IR state) or asynchronously upon entry into the Test-Logic-Reset state.

The instruction register allows instructions to be serially entered into the test logic during a instruction register scan cycle. Instructions loaded in the instruction register are decoded so that each instruction selects a test data register that operates during the current instruction. All other test data registers are controlled, so that they do not interfere with MSM6000 operation, or with the selected test data register operations.

Figure 4-43 Typical boundary scan cell

CAPTURESPH2 UPDATE

SCAN IN

DATA IN

SHIFT

MODE

1

0DATA OUT

SCAN OUT

013-076




The supported instructions and their corresponding codes are listed in Table 4-31.

4.12.4.1 BYPASS

The BYPASS instruction selects the Bypass Register to connect between TDI and TDO. Selecting the Bypass Register, loads the 1-bit shift register with a logic low on the rising edge of TCK, following entry into the Capture-DR state. Holding TDI high, and completing an instruction scan cycle, executes the BYPASS instruction and sets up the Bypass Register. When the TDI input is unconnected, it is pulled to a logic high. If there was an open circuit fault condition in the serial board level test data path, the Bypass Register is selected following an instruction scan cycle. The BYPASS instruction has no effect on any other test data register.

4.12.4.2 SAMPLE/PRELOAD

The SAMPLE/PRELOAD instruction selects the Boundary Scan Register. This register connects between TDI and TDO in the Shift-DR state. The SAMPLE/PRELOAD instruction has no effect on any other test data register. Using SAMPLE/PRELOAD allows two functions to be performed:

SAMPLE allows a snapshot of the normal MSM6000 I/O operation to be taken and examined without causing interference. The snapshot is taken on the rising edge of TCK in the Capture-DR state. The data is viewed by shifting the snapshot data out via the TDO output during the Shift-DR state.

Table 4-31 Boundary scan cell control signals

Cell Signal Description

DATA IN Data input coming from either MSM6000 circuits (pin_OUT or pin_OE cells) or from the pin (pin_IN cell).

DATA OUT An output going to either MSM6000 circuits (pin_IN cell) or to the pin (pin_OUT or pin_OE cells).

SCAN IN SCAN IN from previous cell’s SCAN OUT or the TDI pin if it is the first cell in the sequence.

SCAN OUT SCAN OUT to the SCAN IN of the next cell or the TDO pin if it is the last cell in the sequence.

MODE The MODE signal from the TAP Controller. A logic low selects the Boundary Scan test logic and a logic high selects normal MSM6000 data flow.

CAPTURE, UPDATE, SHIFT

Control signals from the TAP Controller.

SPH2 A clock signal generated from TCK.





PRELOAD allows data values to be loaded onto the Boundary Scan Register’s latched parallel outputs, before selecting other Boundary Scan instructions. The shift register’s value latches on the falling edge of TCK in the Update-DR state. For example, before selecting the EXTEST instruction, data loads onto the latched parallel outputs using PRELOAD. As soon as EXTEST becomes the current instruction, the pre-loaded data updates through the system output pins.

4.12.4.3 EXTEST

The EXTEST instruction selects only the Boundary Scan Register to connect TDI and TDO in the Shift-DR state. The EXTEST instruction has no effect on any other test data register. EXTEST allows circuits that is external to the MSM6000 to be tested (typically the board interconnect). Boundary Scan Register cells at the output pins apply the test stimulus, while those at input pins capture test results. The EXTEST instruction also tests components that cannot do a Boundary Scan. Holding TDI low, and completing an instruction scan cycle, executes the EXTEST instruction and sets up the Boundary Scan Register.

Executing the EXTEST instruction (falling edge of TCK in the Update-DR state), updates the Boundary Scan Register’s latched parallel output into the MSM6000 and then out (via the normal system output pins). The update operation is done using the input and output Boundary Scan Register cells. Data is captured into the Boundary Scan Register on the TCK rising edge during the Capture-DR state. When the Shift-DR state is initiated, on the TCK rising edge, the data shifts from the Boundary Scan Register out via TDO.

4.12.4.4 IDCODE

This instruction selects only the Device Identification Register to connect between TDI and TDO. Selecting the IDCODE instruction, loads the manufacturer’s identification code into the Device Identification Register on the rising edge of TCK, following entry into the Capture-DR state.

The IDCODE instruction loads into the IR parallel outputs during the Test Logic Reset state, on the falling edge of TCK. This loading occurs during normal TAP controller clocking. The IDCODE also loads into the IR parallel outputs on the falling edge of TRST_N.

The JTAG ID for MSM6000 is 0x0 002F 0E1.




4.12.4.5 JTAG selection

The following diagrams show the pin configurations on the MSM6000 device for using the mode pins to select between the ARM TAP controller and the MSM6000 TAP controller. When configured to use the ARM interface, an ICD is expected to be connected and when selected for the MSM6000 device, a BSDL test can be performed.

Figure 4-44 JTAG connections for using the MSM6000 BSDL scan chain WDOG disabled

PCB

MSM6000

ICD TCK

TDO

TDI

TMS

TRST_N

RESOUT_N

TCK

TDO

TDI

TMS

TRST_N

RESIN_N

PS_HOLD

VDD_P

PM6XXX

PS_HOLD

R110K

D1

R210K

Mode 0

Mode1

WDOG_EN

GND

TMODE

10K





Figure 4-45 Connections for using the MSM6000 ARM JTAG WDOG disabled

PCB

MSM6000

ICD TCK

TDO

TDI

TMS

TRST_N

RESOUT_N

TCK

TDO

TDI

TMS

TRST_N

RESIN_N

PS_HOLD

VDD_P

PM6XXX

PS_HOLD

R110K

D1

R210K

Mode 0

Mode1

WDOG_EN

GND

TMODE

10K

10K



5 Mechanical Dimensions

5.1 208-ball FBGA package outlineThe 208-ball FBGA package outline is specified in QUALCOMM document BGA User Guide, (80-V2560-1).

5.2 208-ball FBGA land pattern

The 208-ball FBGA land pattern is specified in QUALCOMM document BGA User Guide, (80-V2560-1).


Mechanical Dimensions MSM6000™ Device Specification

5.3 Part markingThe part marking for the MSM6000 is described in Figure 5-1 and Table 5-1 below.

Figure 5-1 Marking diagram

NOTE Engineering samples are distinguished by M = 1.Tin-lead production samples are distinguished by M = 2.Lead-free production samples are distinguished by M = 3.

Table 5-1 Marking descriptions

Line Description

1 QUALCOMM logo

2 QUALCOMM product number:

MSM6000

3 QUALCOMM internal part number:

CD90-V3050-Mn (n = device version)

4 Traceability number = XXXXXXXXX

5 Traceability number = XXXXXXXX

6 Assembly encapsulation date and site codes:

YY = Year (last 2 digits)

WW = Workweek (based upon calendar year)

a = Assembly site code: (a = A for ASE in Kaohsiung, Taiwan)

(a = R for ChipPac in Ichon, Korea)

03-168a

MnXXXXXXXXXXXXXXXXXYYWW a


msm6000™ device specificationread.pudn.com/.../730164/msm6000_device_specification.pdf93-v3050-1...

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