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Lab 12: ALU Ian Callahan (ipc8@pitt.edu)

Purpose The goal of this lab was to design and build an arithmetic logic unit (ALU). An ALU is a

circuit that is utilized to perform arithmetic and logic functions to desired input signals. ALU’s

are at the heart of every computer system. They are the building blocks for many of a computer’s

components. They are used to create central processing units (CUPs), floating-point units

(FPUs), and in graphics processing units (GPUs) (Wikipedia).

An ALU operates by converting two input signals to a desired output. It will perform

only one of the limited operations to the input signals. The ALU will then perform the operation

and output the signal to be used as the user sees fit. The ALU is able to do these operations

through a complicated array of transistors.

For this lab, we used the ALU to compute two four-bit inputs into a single four-bit output

through various operations. The operation that was performed was determined by six input lines.

To determine the inputs, we used a register file that was created in Lab 11, D Flip-Flops to

temporarily store data, and a multiplexer to determine the data input. All of the data was

displayed through two LEDs.

Procedure The procedure for the lab was as follows:

1. We began by creating a schematic in Quartus II. Whenever possible, we used busses for

inputs and outputs of the schematic. The schematic consisted of the following parts:

a. We used one 74AC157 quad 2-input multiplexer to determine whether the data

into the register was a selected data value or a result.

b. We used one 74LS670 4x4 register file chip to store and read the given data. We

set the Read Enable to ground so that it would continuously read the data.

c. We used two 74LS193 4 bit synchronous up/down counters for the write and read

inputs of the register file chip. The counter would be triggered by the user input

and would not operate on a clock signal. We set the DN and LDN inputs to high.

We did not use inputs A through D and outputs CON and BON. The CLR was set

to low. The lowest order output bits were used to determine the write/read state.

d. We used two 74ABT74 dual D-type flip-flops to function as a latch for the data to

allow the ALU to process two different signals. Preset and Set were both forced

high. Clock was wired to an input that was normally low. D was connected to the

data from the register file.

e. We used one 74F181 arithmetic logic unit to perform operations to the data. The

data input B is taken directly from the register files. Data input A is taken from

the latch described previously. Cn, M, and S0-S3 are all inputs to determine the

operation. The Fs are the output of the ALU. G, P, Cn+4, and A=B were not used

for this lab.

f. We used two 74LS247 7-segment display drivers to convert the data into a signal

that can be processed by the LED display. One was connected to the file register

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to display the value of the register. The other was connected to the ALU to

display of the result. We forced BIN, RBIN, and LTN inputs to high.

g. We used two 7-segment LED display to illuminate the data. One was connected to

the file register to display the value of the register. The other was connected to the

ALU to display of the result. We connected the COMMON+ to +5V. We had to

connect the DUMMY output to an output pin in order for the device to work

properly in the simulation.

2. We wired the schematic to follow an example structure given in Figure 1.

Figure 1: This is an illustration of the structure for an ALU design.

3. After the schematic was complete with all of the desired inputs and outputs, we created a

waveform to simulate the circuit. The waveform contained all of the inputs and outputs of

the circuit.

4. With the nodes of the waveform inputted, we generated two different waveforms. The

first waveform created to perform four different operations to four different sets of input

data. Each input data set was stored in registers 0 and 1, and each output data was stored

in register 2. The first operation was XOR. The second operation was OR. The third

operation was A+1. The last operation was AB’-1.

5. The second waveform was used to add four different hexadecimal numbers together.

First, we stored a value to each of the registers. Then we added each of the registers

together and stored the value in the first register without overwriting the other registers.

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6. Next, we created the schematic on the Proto-Board. For choosing the write, read, and

write enable states, we used de-bounce switches. We used the R-S flip-flop circuit from

Lab 7 to construct the switches. We connected the data inputs and the ALU control inputs

to DIP switches. We used switches to determine the clock of the latch and the input of the

multiplexer. We also connected 4 LED’s to the outputs of the counters to determine their

states.

7. After the circuit was tested to ensure functionality, we connected the inputs and outputs

of the circuit possible to a Logic Analyzer. We had the analyzer trigger based off the

Write Enable activation. We then replicated our waveforms previously stated and

recorded the results.

Results

For the lab, we had to implement many different circuit elements. The first circuit

element that we used was the 74LS670 4x4 register file chip. The circuit diagram is shown in

Figure 2. The second circuit element we used was the 74LS193 4 bit synchronous up/down

counter. The circuit diagram is shown in Figure 3. The third circuit element we used was the 7-

segment LED display. The circuit diagram is shown in Figure 4. The fourth circuit element we

used was the 74LS247 7-segment display driver. The circuit diagram is shown in Figure 5. The

fifth circuit element we used was the de-bounce switch. The circuit diagram is shown in Figure

6. The sixth circuit element we used was the 74AC157 quad 2-input multiplexer. The circuit

diagram is shown in Figure 7. The seventh circuit element that we used was a four-bit latch. The

latch is composed of two 74ABT74 dual D-type flip-flops. The circuit diagram for a D flip-flop

is shown in Figure 8. The final circuit element used was a 74F181 arithmetic logic unit. The

circuit diagram is shown in Figure 9.

Figure 1: This figure demonstrates the pin configuration for a 74LS670 4x4 register file chip.

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Figure 3: This figure illustrates the pin configuration for the 74LS193 4 bit synchronous up/down

counter.

Figure 4: This figure illustrates the pin configuration for the 7-segment LED display.

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Figure 5: This figure illustrates the pin configuration and logic diagram for the 74LS247 7-

segment display driver.

Figure 6: This figure illustrates the circuitry for the de-bounce switch.

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Figure 7: This figure illustrates the pin configuration and logic symbols for the 74AC157 quad 2-

input multiplexer.

Figure 8: This figure illustrates the pin configuration and logic diagram for the 74ACT74 dual D-

type flip-flop.

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Figure 9: This figure illustrates the pin configuration for the 74F181 arithmetic logic unit.

For the creation of the schematic, we followed the layout given in Figure 1. We had a

counter go to each of the write and read addresses. We had the data going into the 74AC157

chip, which was controlled by an input switch. The multiplexer fed into the 74LS670 chip. We

had the 74LS247 connected to the data output of the 74LS670. We had the LED display

connected to the 74LS247. We also had the output wired to the latch, which its clock signal was

triggered by a switch. The output of the 74LS670 and the latch were wired to the 74F181, which

was controlled by six input signals. The result was wired to the 74AC157 as well. The result was

also wired to a 74LS247 and an LED display. The schematic is illustrated in Figure 10.

Figure 10: This figure illustrates the schematic created in Quartus II.

After we created the schematic, we formed waveforms to test the capability and

functionality of the circuit. We included all of the nodes illustrated from the circuit. We tested

the circuit to ensure functionality. The waveform is shown in Figure 11 and Figure 12. They are

broken up into three pages each because of size.

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Figure 11: These illustrates the circuit performing four different operations.

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Figure 12: These illustrates the circuit adding four hexadecimal numbers and storing the results

in the first register.

Once the circuit was tested on Quartus II, we built the circuit on the Proto-Board. We

tested the circuit on the board to ensure functionality. With the circuit tested, we wired all of the

inputs and outputs necessary to a Logic Analyzer. We collected two sets of data. The first set

contains the performing of four different operations. This set can be found in Figure 13. The

second set contains the performing of addition of four hexadecimal numbers. This set can be

found in Figure 14. They were broken up into four pieces each because of timing and size.

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Figure 13: This demonstrates the ability of the circuit to be perform four different operations.

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Figure 14: This figure illustrates the circuit’s ability to add four hexadecimal numbers.

Conclusion

The purpose of this lab was to create an ALU. To do so, we followed a structural

illustration given to us to create a schematic in Quartus II. We tested the schematic with

generated waveforms to ensure functionality. Afterwards, we implemented the design on a Proto-

Board. With the circuit complete, we analyzed the inputs and outputs with a Logic Analyzer. As

demonstrated by Figures 13 and 14, the circuit was able to achieve its desired functionality. The

circuit was successful and achieved the goal of the lab.

References

Professor Helen Li’s lecture slides

Circuit diagrams for circuits from Courseweb

"Arithmetic Logic Unit." Wikipedia. Wikimedia Foundation. Web. 9 Apr. 2016.

Lab Partner: Brandon Jones