Passive Equalization of Test Fixtures for High-Speed Digital Measurements with

Automated Test Equipment

Jose Moreira1, Michael Howieson2, Michael Petersen2, Mark Broman2, Jonathan Kenton3

1Verigy, Herrenbergerstrasse 130, 71034 Böblingen, Germany

2Thin Film Technology, 1980 Commerce Drive, N. Mankato 56003-1702 MN, USA

3Intel, 1900 Prairie City Road,

Folsom 95630 CA, USA

ABSTRACT — Automated test equipment (ATE) is used extensively in production test and device characterization of integrated circuits (ICs). With future devices forecasted to contain hundreds of I/O cells operating at speeds from 5Gb/s to 10Gb/s, the challenge to test those devices with an ATE system is becoming more complex. The speed bottleneck is moving from the pin electronics of the ATE to the test fixture connecting the ATE to the device under test (DUT). The layout of the test interface will require thinner and longer signal traces which will have an unacceptable loss for the required data rates. This challenge will require the use of compensation techniques to address the increased loss of the signal traces. This article presents one strategy to address this challenge by integrating passive equalization in the test-fixture signal trace.

I. INTRODUCTION

Current state-of-the-art integrated circuits (ICs) that are in volume production already contain tens of I/O cells running at speeds between 5Gb/s and 10Gb/s [1]. With the increased availability and quality of these high-speed I/O cells in standard CMOS processes, this trend will continue with near-future devices containing hundreds of these I/O cells. Device pin counts will then be above one thousand, when taking into account all the pins (high-speed, power, low-speed, etc…).

The challenge for the automated test equipment

(ATE) industry is to be able to provide the tools for testing and characterizing these I/O cells at-speed. This means that the ATE platform must be able to provide stimulus and measure to a large number of high-speed pins of the device under test (DUT). This is one of the toughest challenges facing the ATE industry [2]-[3].

ATE systems that are able to test at-speed ICs at 10Gb/s with limited pin count have been available for some time [4]. The challenge is to test multi-gigabit high pin count ICs and remain cost effective. In the past, most of the devices in this speed area were intended for wired

communication applications (e.g. SONET). In the near future they will be intended for consumer markets such as desktop computers, where cost-of-test is a key factor.

In an ATE system, the DUT is connected to the ATE pin electronics through a printed circuit board (PCB) that is known as the test fixture, device interface board, or DUT loadboard. This test fixture contains a series of signal traces (microstrip or stripline) that connect the ATE pin electronics to the socket where the DUT will interface with the test fixture. Fig 1 shows a test fixture docked to an ATE system.

The test fixture in the above figure is for a

relatively small device with only eight I/Os running at 10Gb/s. For devices with hundreds of I/O cells, it might be necessary to use all the resources of the ATE system. This will result in test fixture signal traces with lengths of 50 cm for some of the signal traces in this specific ATE system. Fig 2 shows a representation of this challenge by demonstrating the degradation of a 6.4 Gb/s waveform when traveling though 19 cm of a test fixture trace using state-of-the-art

Fig 1: Test fixture docked to a Verigy V93000 ATE

system.

techniques and materials (19mil width on ROGERS4350).

The above figure clearly shows the need to

develop techniques to address this issue that go beyond the trace geometry or type of dielectric material used on the test fixture. The reason is that even using of state-of-the-art PCB materials and manufacturing techniques, we are unable to solve the issue of the signal traces loss for long trace lengths at high data rates.

One possible compensation technique is the use of a compensation filter that flattens the frequency response by attenuating the lower frequencies. Fig 3 shows the basics of this technique in the frequency domain.

This type of filter, also known as a passive

equalizer filter is not new, but the use of this technique to compensate signal in the 10Gb/s range on a test fixture is new and presents different challenges given the high data rates that the equalizer must address.

In the next section, we will outline the loss

components of a PCB signal trace followed by an introduction to passive equalization. We will then present a process for choosing the correct equalizer for a given application. Finally, we will present some experimental results with a real application followed by some conclusions. In an appendix we will present a quick discussion of software equalization and how it is related to passive equalization.

II. MICROSTRIP AND STIPLINE LOSS

The loss of a PCB signal trace can be roughly divided into three areas [5]-[6]: conductor loss, dielectric loss and radiation loss. The conductor loss can be also sub-divided into more terms as shown in Fig 4.

For the applications discussed in this article, we

will concentrate on the skin effect and dielectric loss contributions. They are the major contributors of the high-frequency loss of signals traversing long signal traces.

Two types of geometries are typically used on test fixtures for high-speed signals. They are stripline and microstrip. If careful attention is payed to the microstrip plating process [7], the loss of a microstrip and a stripline is very similar as shown in Fig 5. At high-frequencies the microstrip does have additional issues due to its quasi-TEM propagation mode, but for the purposes of this article the use of a microstrip or stripline is considered the same.

Several references provide approximate analytical solutions for the losses in a microstrip or stripline trace [8]-[9], but current simulation tools are able to compute the loss profile accurately if appropriate care is taken [10].

Fig 2: Diagram showing the challenge of long test

fixture traces for high-speed digital applications.

Fig 3: Basics of passive equalization of the

frequency-dependent loss associated with a signal path.

Fig 4: Loss components of a PCB transmission line

(impedance mismatches in the transmission line will also add a “reflection loss”).

Fig 6 shows a simulation setup using the

Agilent Advanced Design Simulation software package for two different stripline lengths in a ROGERS4350 type dielectric. The striplines have a width of 5.5mil.

The setup contains a model of the test fixture

dielectric (ROGERS4350) and of the stripline. The modeled stripline lengths are 10 inch (25.4 cm) and 20 inch (50.8 cm). Fig 7 presents a comparison of the simulated insertion loss for both stripline lengths.

In Fig 7, it is obvious that the trace length

influences the signal path bandwidth significantly.

In this specific case, the doubling of the trace length reduced the bandwidth by more than half. Note, that although we did not account for the effects of the socket, pogo connections, etc..., the use of a simulation tool with simple, but appropriate models, allows the test engineer to understand the effect of the test fixture design trade-offs on the test application.

The above results show how the test fixture design and layout impact the final performance of the ATE measurement system.

Although only the effect of the trace length is presented, the reader must be aware that test fixture design decisions are not limited to only the trace length or dielectric material. Other parameters are also very important for the test fixture performance. For example, the trace width is an important factor since losses due to skin effect are inversely proportional to the trace width. Also, the appropriate design of signal vias including the ground vias to provide a reference plane for the signal via, will influence the signal performance.

III. PASSIVE EQUALIZATION

Passive equalization is not new. The basics of passive equalization was patented already by Bode in 1936 [11] and passive equalization has been used already on ATE [12]. Fig 8 presents two examples of possible passive equalizer circuits.

One important consideration of a passive

equalizer is that it will add a low frequency attenuation to the signal path. However, in a test and measurement application this is easily calibrated out. One needs to keep in mind that the test requirements for a given I/O cell will define a maximum allowed loss for the equalizer that still fulfills the test requirements.

Fig 5: Comparison of the modeled vs. measured loss

for a microstrip and stripline in ROGERS4350.

Fig 6: Simulation setup in ADS.

Fig 7: Insertion loss comparison for two different

trace lengths with the same geometry in the same dielectric material.

Fig 8: Equalizer circuit diagrams (left: a simple RC

high-pass filter, right: a more complex one stage equalizer).

In general, the amount of low frequency attenuation induced by the passive equalizer is exchanged for the achievable bandwidth of the overall signal path.

Fig 9 presents a graphic description of the trade-offs of passive equalization in regards to the two variables that compose the problem. These variables are the loss of the signal path to be equalized and the amount of loss to be allowed in the application.

The equalized bandwidth of the signal path

describes the flatness of the insertion loss response of the path in relation to the digital signal’s spectral power density. The critical spectral power density of the digital stimulus resides at and below the fundamental frequency which in NRZ schemes is one half of the data rate in Hertz.

Since most digital signals have high edge rates they resemble square wave spectrums with odd harmonics of the fundamental frequency. Since the trace loss typically increases exponentially with frequency, most of these harmonics are lost to the trace loss beyond equalization. The spectral power density is also limited by the pattern randomness and balancing encoding at the lower frequencies. Passive equalization reduces jitter by removing intersymbol intereference or ISI by flattening the path loss response through these bands. Fig 10 shows how signal path loss can cutoff the signal harmonics.

On the figure one can observe that equalization is able to bring out the higher frequency contents of the signal that were lost due to the signal path loss.

In order to minimize the impedance

discontinuity experienced by a signal, the use of a small footprint test fixture equalizer is preferred. For the data-rates under discussion [5-10Gb/s], the passive equalizer manufacturer Thin Film Technology has developed an equalizer on a 0603 package size. Fig 11 shows a photograph of the TFT 0603 equalizer.

The equalizer uses a face down footprint

optimized to 20Ghz. Low parasitics and very tight application tolerances make this component ideal for compensating PCB trace loss.

IV. SELECTING THE APPROPRIATE EQUALIZER BY

SIMULATION

This section presents a methodology for selecting a test fixture equalizer by using a defined process. Fig 12 presents the design flow for determining which equalizer to use on a specific signal path of a test fixture.

Fig 9: Passive equalization trade-off matrix.

Fig 10: Signal path insertion loss with and without

equalization and its effect on the spectral power densitiy of a 6.4Gb/s 8b10b data patetrn.

Fig 11: TFT Passive equalizer in a 0603 package

size.

The test engineer needs to provide the signal

trace geometry and material to be used on the construction of the test fixture. With this data it is possible to construct a model of the signal trace loss. In addition, the test engineer needs to decide the maximum loss allowed by the I/O cell in order to determine the range of passive equalization that will work for a given test application/system.

The loss of the equalizer determines to what extent the frequency response of the trace can be flattened. The drawback is that this loss needs to be compensated by the ATE resources. One needs to make sure that the ATE has enough margin to be able to test the application with the chosen loss for the equalizer.

After the maximum loss is chosen, an optimal

RC equalizer can be found by simulation. This step can be very complex since the definition of optimal equalizer might depend on the application. Fig 13 shows one possible approach that consists in simulating different RC configurations to find the one with the highest bandwidth. Note that it is very important to keep the ripple of the frequency response below a certain minimum value.

With the optimal equalizer found, it is possible to perform a time and frequency domain simulation of the test fixture performance with the optimal equalizer. This allows the test engineer to view the performance improvement that can be obtained with a custom design equalizer.

However, because making a custom equalizer for each application is more expensive and requires longer lead-times, a better approach is to select the equalizer from a matrix of available equalizers. This would significantly reduce the cost and lead-time.

This means that after determining the

performance of the optimal equalizer, an equalizer from the available matrix must be chosen. Fig 14 shows this procedure where the optimal equalizer was found and one equalizer from the matrix must now be chosen.

After an equalizer is chosen, a more detailed

simulation including models of the ATE pin electronics (if available) and the DUT driver/receiver needs to be completed.

If the simulated performance is not acceptable, additional compromises might be needed (e.g. allow additional loss or even change the test fixture trace geometry) so that the final performance meets the test engineer needs.

Fig 12: Design flow to select the appropriate

equalizer. Fig 13: Optimization procedure by testing different

equalizers into the same signal path loss.

Fig 14: TFT equalizer family matrix.

Another important point is the distribution of the DC loss on the manufactured equalizers. As previously mentioned, this DC loss can be calibrated out of the measurements. In order to do that it is important the DC loss value is known and has a tight distribution. If the DC loss distribution is very large then it would be necessary to calibrate each equalizer individually through a focus calibration procedure. Fig 15 shows an example of the expected distribution for a real implementation of the 0603 equalizer.

Fig 15 shows it is difficult to keep a tight

distribution across multiple lots. However, this problem can be reduced by an additional laser trimming process. The best solution for a given test fixture is that all the equalizers should be from the same production lot.

V. EXPERIMENTAL RESULTS

This section presents some results obtained by applying the methodology outlined in the “selecting the appropriate equalizer” section to a real application. Fig 16 presents a picture of a test fixture developed to teach the basics of signal integrity and equalization when using the Verigy 12.8Gb/s Pin Scale HX ATE pin electronics card.

In this board there exist several different test structures. They are intended to provide examples

of the signal integrity challenges inherent to the design of high-speed digital test fixtures. One of the examples is the challenge of compensating for 45 cm of a 21 mil microstrip signal trace in ROGERS4350. The surface plating (NiAu with solder mask on top) is also not optimal, which increases the signal trace loss [7].

The ATE pin electronis card used in these

section measurements already includes an integrated passive equalizer [7]. This equalizer is designed to compensate for approximately 10 inches of a 19 mil stripline in ROGERS4350. Fig 17 shows a picture of the pin electronics card showing the integrated equalizer on the driver and receiver blocks of the ATE card.

The integrated equalizer is clearly not enough for the 45 cm microstrip example and additional equalization is needed in the form of a passive equalizer in the test fixture.

Fig 15: Example of the distribution of the equalizer

DC loss for four lots (top) and for one lot (bottom).

Fig 16: Pin Scale HX training test fixture.

Fig 17: Picture of the Pin Scale HX pin electronics

showing the integrated equalizer.

In this application, the DUT is an OC192 10Gb/s transceiver. Following the procedure described in the previous section, an equalizer was selected to compensate for the signal trace loss. Note that in this selection, one needs to take into account the equalizer integrated on the ATE card. Fig 18 shows the two equalizers for the 45 cm (17.7 inches) microstrip differential pair in the test fixture. An identical microstrip trace with no equalizer also exists on the test fixture for comparison.

The selection of the equalizer was done

primarily by evaluating the frequency and time domain response simulations. An equalizer with 4dB loss was chosen for this specific application. The frequency domain simulation results are presented in Fig 19.

The simulated results show an improvement of more than 5GHz on the signal path bandwidth with the integrated equalizer (Fig 17) and the 4dB test fixture passive equalizer in regards to the signal path without equalization. Fig 20 and Fig 21 show the simulation results in the time domain.

The time domain simulation results show a

clear improvement on the data eye parametrics. The overshoot observed on the data eye is due to the fast rise time of the simulated source and also to the fact that the insertion loss curve is not completely flat. Experience has shown us that a slight overshoot in simulation is preferred, as the real driver is typically slower and the signal path’s loss is slightly higher, thus eliminating the overshoot in the real application.

Fig 22 presents a block diagram of the measurement setup showing the different measurement points included in this section.

Fig 18: Equalizers assembled on the microstrip trace

of the test fixture.

Fig 19: Frequency domain simulation results. Note

that the equalizer response is shifted by 4dB for easier readability.

Fig 20: Time domain simulation of the data eye after

the test fixture only with the integrated equalizer.

Fig 21: Time domain simulation of the data eye after

the test fixture with the ATE integrated equalizer and the test fixture equalizer.

Fig 22: Block diagram of the measurement setup.

Fig 23 shows the DUT output data eye at 10GB/s. This is clearly a high-performance driver, delivering a very low jitter data eye with a very fast rise time. Note that this data eye is taken at the output of the DUT with a small (30cm) coaxial cable as shown in Fig 22.

Fig 24 and Fig 25 show the output data eye measured further along the signal path after the 45cm of a microstrip line, with and without the test fixture equalizer. The data eye on Fig 24 shows a significant amount of ISI added by the signal trace loss, while the date eye on Fig 25 shows how the equalizer, by compensating for the frequency dependent loss of the signal trace, is able to reduce the ISI significantly. Although there is an amplitude decrease due to the constant loss of the equalizer, it can easily be calibrated out in the measurements.

Fig 26 and Fig 27 present the eye diagrams

measured by the ATE pin electronics receiver with and without the equalizer on the test fixture. On this measurements, a PRBS7 data pattern was used and 1E9 bits were acquired at each (voltage, timing) measurement point.

Fig 23: DUT output data eye at 10Gb/s with a

PRBS7 pattern.

Fig 24: Data eye at the end of the signal trace

without the passive equalizer on the test fixture.

Fig 25: Data eye at the end of the signal trace with

the passive equalizer on the test fixture.

The results show that the equalizer on the test

fixture is able to improve the measured data eye width by 15 ps.

Fig 28 shows a jitter histogram measurement of the DUT at 10Gb/s with a PRBS7 data pattern using an ATE receiver. The figure presents three different measurement setups: a 45cm microstrip trace without test fixture equalization, the same trace with equalization on the test fixture, and a 25cm (10’’)

stripline trace (19mil on ROGERS4350) with no test fixture equalization. Note that the ATE receiver used on the measurements includes the integrated equalizer shown in Fig 17.

From the above figure it is possible to see that by

adding the equalizer on the test fixture, we are able to obtain a better jitter histogram measurement that is closer to the real output from the DUT.

Another interesting result is to look into the

influence of the data rate on the measurements. Using a bench instrument as stimulus source we increased the data rate from 5 Gb/s to 10Gb/s. The peak-peak jitter from the stimulus source is constant across the different data rates. The signal was measured at the end of the 45cm signal trace with and without the passive equalizer. The results are presented in Table 1. As the datarate increases, the ISI effects on the jitter envelop increase as well. However, since the equalizer flattens and extends the BW of the signal trace’s frequency response, the ISI effects are drastically reduced.

Table 1: Peak-peak jitter measurement dependency on the data rate for the 45cm signal trace with and without equalization.

DATA RATE No EQU With EQU 5Gbps 17 16.76.4Gbps 19.1 15.68Gbps 21.9 16.510Gbps 25.6 15.9

The results show that after 5 Gb/s the measured

peak-peak jitter on the signal trace without equalization increases due to the bandwith limitations of the test fixture that adds ISI jitter to the signal. For the signal trace with equalization it is

Fig 26: Data eye measured by the ATE receiver with

no equalization.

Fig 27: Data eye measured by the ATE receiver with

equalization.

Fig 28: Jitter histogram measurement of the DUT at

10Gb/s with a PRBS7 data pattern.

possible to observe that the measured peak-peak jitter value stays constant due to the increased bandwidth of the test fixture through equalization. This is a very important observation, especially when testing devices with variable data rates.

VI. CONCLUSIONS

This paper has demonstrated that it is possible to address the challenge of the test fixture trace loss for high-speed and high pin count digital interfaces in current and future ICs, by using passive equalization integrated on the test fixture. A design methodology was presented to choose the correct equalizer, and results with a real application were presented, showing the significant improvement that can be obtained by the use of passive equalization integrated on the test fixture.

As more and more silicon suppliers integrate higher numbers of I/O cells running at multi-gigabit speeds, the layout of the test interfaces will require smaller trace widths and longer traces. This means that unacceptable level of frequency dependent loss will be added to the signal to be measured. Passive equalization is not a perfect solution to this problem, as it induces its own amplitude attenuation, but it can increase significantly the bandwidth of the test interface, reducing the ISI added to the signal to be measured. Careful selection of the equalizers is crucial, as it is possible for an equalizer to cause an unacceptable reduction in the signal amplitude to be measured. However, if properly selected the test engineer can address the test interface loss issue as shown in the results with a real application presented in this article.

ACKNOWLEDGEMENT

We would like to thank Bernd Laquai from Verigy for initially bringing together TFT and Verigy and also for all the discussion surrounding signal integrity and equalization. We would like to thank specially to Hubert Werkmann for the contributions to the SW equalization section. We would also like to thank Roger Nettles and Heidi Barnes from Verigy.

APPENDIX: SW EQUALIZATION

In this section we will briefly discuss software equalization or compensation since it is being used in several test and measurement equipment solutions (e.g. real-time sampling scopes) and it is important

to understand the difference from hardware passive equalization.

The starting point for software-based equalization (SWE) is the insertion loss characteristic, or frequency response of the PCB trace to be compensated.

In this approach, an analysis of the effects of the PCB trace on a non-ideal step function is performed to assess the loss effects occurring over the trace.

In order to quantify the frequency response of a PCB trace, two-step function measurements are required. The first measurement is done at the source of a step function simulating the PCB trace. In a second step, the same step function is measured after it has passed the signal path (PCB trace) to be compensated. Based on the difference between the two measured step functions, the response of the PCB trace to an ideal unity step function is calculated. This ideal step function response is the time-domain equivalent to the frequency response or insertion loss in the frequency domain. The calculated step response is the basis for our SWE. Examples for step functions measured before and after PCB trace transmission are shown in Fig 29.

The response to an ideal step is calculated based

on the measurements of Fig 29. This serves as a basis for the design of a FIR filter used to compensate the signal degradations of waveforms measured over this PCB trace.

Fig 30 shows an example of this technique applied to an ATE card running at 2.5Gb/s with a PCI-Express compliance pattern measured at its source and after its transmission through a PCB trace. A FIR filter was generated for this trace according to the methodology described above. This FIR filter was applied to the waveform measured by

Fig 29: Measured step functions before and after

PCB trace transmission.

the ATE receiver after traveling through the PCB trace.

The droop effects after run length are

compensated and the level loss caused by the PCB trace can be seen clearly from the uncorrected full waveform in Fig 30. From this figure, it is also obvious that SWE significantly improves the signal quality, especially regarding the level information of the measured signal.

A lot more can be discussed on SWE. The important point is that although SWE is able to address some of the signal integrity challenges of PCB signal traces, it can only be applied to certain types of data, more explicitly to data that contains time and level information. This is not possible in an at-speed functional test or for example when measuring a BER bathtub curve. In this type of measurement, only pass/fail and time information is measured. SWE cannot be used in this case since no level information is present.

Hardware passive equalization and software equalization are not mutually exclusive. In cases where time and level information are present they can be used together or software equalization can be used instead of HW equalization. In situations where at-speed test is used, only HW equalization is usable.

REFERENCES

[1] M. P. Li, Design and Test for Multiple Gbps Communication Devices and Systems, IEC, 2005

[2] U. Schoettmer, C. Wagner and T. Bleakley, “Device Interfacing: The Weakest Link in the Chain to Break into the Giga Bit Domain?,” IEEE International Test Conference, 2003.

[3] M. Shimanouchi, “New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing,” IEEE International Test Conference, 2002.

[4] Jose Moreira, Gert Hänsel and Frank Koban “Addressing the Challenge of Implementing an At-Speed Production Test Solution for 10Gb/s Wafer Probing” IEC DesignCon West, 2005.

[5] Howard Johnson and Martin Graham, High-Speed Signal Propagation. Prentice Hall 2003.

[6] Stephen C. Thierauf, High-Speed Circuit Board Signal Integrity. Artech House 2004.

[7] J. Moreira et al “PCB Loadboard Design Challenges for Multi-Gigabit Devices in Automated Test Applications” IEC DesignCon West, 2006.

[8] K.C. Gupta, Microstrip Lines and Slotlines. Artech House 1996.

[9] Brian C. Wadell, Transmission Line Design Handbook. Artech House 1991.

[10] Daniel G. Swanson and Wolfgang J.R., Microwave Circuit Modeling Using Electromagnetic Field Simulation. Artech House 2003.

[11] Hendrik W. Bode “Attenuation Equalizer” US Patent 2,096,027,027 1936.

[12] Wolfram Humann “Compensation of Transmission Line Loss for Gbit/s Test on ATEs” IEEE International Test Conference, 2002.

Fig 30: Results of applying SW equalization

through a FIR filter to a 2.5Gb/s DUT output through a test fixture.