A New Pixel Circuit to Compensate Panel Non-uniformity and OLED Degradation on Large IGZO AMOLED Panel

Chun-Chieh Lin, Kuei-Yu Lee, Chih-Cheng Chen, Hong-Shen Lin, Lee-Hsun Chang

and Yu-Hsin Lin

Large Size OLED Technology, AU Optronics Corporation, No. 1,

Li-Shin Rd. 2, Hsinchu Science Park, Hsinchu, Taiwan

Abstract A new 4T2C pixel circuit is proposed in this study to compensate

TFT process variations, Vth, mobility, power line IR-drop, and

OLED degradation in IGZO-TFT process. Compensation

performances show only from ±0.8% to ±1.74% panel non-

uniformity in average.

Author Keywords Active-matrix organic light-emitting diode (AMOLED), panel

non-uniformity, compensation, indium gallium zinc oxide

(IGZO).

1. Introduction Active-matrix organic light-emitting diode (AMOLED) displays

are well-known dream displays in next generation. They have

many advantages such as high contrast ratio and wide viewing

angle. After achieving the significant success in the market of

mobile phone, AMOLED displays currently focus on the larger

panels like full high definition (FHD) or ultra high definition

(UHD) TVs [1]. However, the panel non-uniformity is one of the

critical issues when fabricating larger panels, which results from

many different reasons like threshold voltage (Vth), mobility, and

aspect ratio variations in thin-film transistor (TFT) process [2],

and IR-drop occurring on panel power line [3]. Moreover, OLED

degradation is also the issue on AMOLED panel, which leads

OLED luminance decay. It results from the anode voltage of

OLED component is gradually increased to lead that the driving

current through OLED component is decreased during the long

time drive [4]. As a result, in order to remedy panel non-

uniformity in TFT process, an advanced process, indium gallium

zinc oxide (IGZO) TFT [5] is proposed. This process can achieve

the targets of better panel uniformity, maintaining the required

TFT mobility to drive AMOLED panel, even lower manufacture

cost than low temperature poly-silicon (LTPS) TFT process. But,

it is only suitable for fabricating n-type TFTs. In addition, designs

of compensating pixel circuit are other methods to remedy panel

non-uniformity and OLED degradation. In [6], the pixel circuit is

proposed to compensate Vth variation and alleviate OLED

degradation. But power line IR-drop and OLED degradation also

require considering to be compensated. In [7], Vth variation and

OLED degradation are successfully compensated in the proposed

pixel circuit. However, the proposed circuit is formed by both p-

type and n-type TFTs. In order to fabricate pixel circuit in IGZO-

TFT process, the compensating pixel circuit formed by all n-type

TFTs is needed to be designed. Therefore, in this study, the 4T2C

pixel circuit based on fabricating resolution FHD panel in IGZO-

TFT process is proposed. TFTs in this proposed pixel circuit is

used by all n-type TFTs. The pixel circuit is designed to

compensate TFT variation factors, Vth, mobility, and aspect ratio,

power line IR-drop, and OLED degradation.

(a) (b) (c)

Figure 1. Operation of 4T2C pixel circuit in (a) reset (b) compensation (c) emission periods.

P-19 / C.-C. Lin

SID 2014 DIGEST • 1013ISSN 0097-966X/14/4503-1013-$1.00 © 2014 SID

2. Pixel Circuit to Compensate Panel Non-uniformity and OLED Degradation Figure 1 illustrates the proposed compensation circuit that is

formed by four TFTs and two capacitors (4T2C), where

capacitors, C1 and C2 are utilized to operate procedures of data

storage and compensation. T1 and T4 are scan and driving TFTs,

which are designed to provide display scan operation and

determine OLED luminance, respectively. T2 and T3 are switching

TFTs, which are designed to reset circuit status of last frame time

and enable OLED emission, respectively. S1, E1 and R1 are signal

waveforms for operating scan, emission, and reset procedures,

respectively. IREF is the reference current for compensating

operation. Data represents the display writing in input in each

frame time. Vs and VG represent source and gate voltages of TFT,

T4. VOLED represents driving voltage imposed on OLED

component. OVDD and OVSS are panel power line and ground.

Moreover, named reset, compensation, and emission periods,

figures 1(a), (b), and (c) illustrate the circuit statuses of pre-

charging C2 for resetting pixel circuit, writing in display data with

compensating factors, and enabling OLED emission, respectively.

Figure 2 illustrates the associated waveforms, S1, R1, E1, and Data,

in figure 1 for operating compensation and emission procedures

on pixel circuit. In reset period shown in Figure 1(a), S1, R1, and

E1 reach high voltage levels to turn on T1, T2, and T3. Meanwhile,

gate voltage of T4, VG, is set by reference data, VREF. Source

voltage of T4, Vs, is hence discharged by reference current IREF

through T2 for resetting compensating operation in last frame time.

While the discharge procedure reaches steady state, the current

through T4, IT4, is equal to reference current, IREF as shown in the

following TFT current formula

REFthGSTIVVKI =−=

2

14 )( (1)

REFthsREF

IVVVK =−−=2

1 )( (2)

Therefore, Vs is obtained by

1K

IVVV

REF

thREFs−−= , (3)

where K1 is the well-known parameter consisting of mobility, Cox

and aspect ratio of T4. Note that Vs as shown in figure 1 and

Equation (3) is the anode voltage of OLED component. When

OLED degradation occurs, the anode voltage is increased to lead

different driving current through OLED component. At steady

state of reset status, reference data, VREF, requires being smaller

enough so that Vs is smaller than (VOLED+OVSS) for guaranteeing

against OLED emits. The guarantee can avoid different driving

current flowing through OLED component, which rule out OLED

degradation leading the varied compensation factor, Vs in

Equation (3). Next, during compensation period illustrated in

figure 1(b), S1 maintains high voltage level to open T1. R1 and E1

reach low levels to turn off T2 and T3. Data is written in by display

data, D[1]. Meanwhile, source voltage of T4, Vs, is coupled to

)]1[(21

1

1

REF

REF

thREFSVD

CC

C

K

IVVV −

+

+−−=. (4)

It is similar to last period in figure 1(a), in which to avoid OLED

degradation affects compensation results, Vs also requires being

smaller enough for guaranteeing against OLED emits, i.e.

avoiding storage charges in capacitors, C1 and C2 leak into OLED

component. Last, during emission periods in Figure 1(c), E1

reaches high voltage level to turn on T3. S1 and R1 reach low

levels to turn off T1 and T2. Vs is hence charged from driving

current, IOLED, provided by power line at the steady state as

illustrated in figure 1(c). Meanwhile, gate voltage of T4 is coupled

as

)]]1[([]1[21

1

1

REF

REF

thREFOLEDGVD

CC

C

K

IVVOVSSVDV −

+

+−−−++=

,(5)

At the steady state of emission period, according to well-known

TFT current formula, the current through driving TFT and OLED

component can be written as

.})(

)]]1[([]1[{

2

21

1

1

2

thOLED

REF

REF

thREFOLEDOLED

VOVSSV

VDCC

C

K

IVVOVSSVDKI

−+−

−

+

+−−−++=(6)

Note that K2 is identical to K1 shown in Equation (1). Finally, the

formula of compensated current is re-written as

Figure 2. Associated signal waveforms to drive pixel circuit.

-10 -5 0 5 10 151E-15

1E-13

1E-11

1E-9

1E-7

1E-5

ID(A

)

VGS (V)

Measured

Simulation

Figure 3. I-V curves of measure and simulation to verify the accuracy of IGZO-TFT model.

P-19 / C.-C. Lin

1014 • SID 2014 DIGEST

2

121

1

2 })]]1[()1{[(K

IVD

CC

CKI

REF

REFOLED+−×

+

−= . (7)

Shown clear in Equation (7), one of the panel non-uniformity

factors, Vth is successfully eliminated. Power line IR-drop factor,

OVSS also disappears in Equation (7). Significantly, driving

voltage imposing on OLED, VOLED, affected from OLED

degradation extent is also eliminated in Equation (7), i.e. the

effect of OLED degradation is also compensated. As a result, as

for driving current, IOLED, the effect of varied anode voltage Vs,

can be ruled out. Although other non-uniformity factors such as

TFT mobility and aspect ratio still exist in K’s in Equation (7),

designed pixel circuit has compensating performance. In Equation

(7), K1 and K2 is the same value from driving TFT, T4. Since K2

has the inverse proportion corresponding to

1K

IREF , panel non-

uniformity caused by mobility and aspect ratio variations can be

reduced in formula. Furthermore, variation K effects can be

minimized by selecting the optimal reference current, IREF as

shown in Equation (7). These detailed design procedures are

discussed in next simulation section. Consequently, new 4T2C

pixel is successfully proposed to completely compensate panel

non-uniformity caused from TFT process, power line IR-drop,

and OLED degradation in a long time drive. As shown in figure 1,

in the proposed pixel circuit, n-type TFTs are utilized to fit the

requirement of advanced IGZO process. In next section, the

compensating performances are investigated by simulating a panel

of resolution FHD in IGZO process.

3. Simulation To simulate non-uniformity compensation realizing on larger

panel, resolution FHD fabricated in IGZO process is selected.

First, in order to verify the accuracy of IGZO-TFT model, well-

known TFT I-V curves are shown in figure 3, where simulation

and measure of single TFT component are matching. The

compensating simulation is divided into four parts including

compensating performances of Vth, OVSS, and, K, and the

selections of optimal reference current, IREF. Figure 4 shows Vth

simulation performances between new 4T2C and conventional

2T1C pixel circuits, where variation Vth is set to ±0.3V. In this

figure, driving current errors at every gray levels are compensated

from ±20.3% to ±0.8% in average. Next, OVSS is set to ±1V for

verifying the compensating performances of varied anode voltage,

Vs, in figure 1 between new 4T2C and conventional 2T1C pixel

circuits. As shown in figure 5, current errors at every gray levels

are compensated from ±73.14% to ±1.74% in average. Moreover,

variation K’s in Equation (7) are set to 10% and 20% to verify the

ability of reducing effect on panel non-uniformity as shown in

figure 6. Shown clear in this figure, current errors at every gray

levels between these pixel circuits are also reduced from ±11.33%

to ±7.49% in average. Furthermore, the advanced compensation of

variation K’s in Equation (7) is proposed. As shown in figure 7,

the different reference current IREF’s, (a) 0.1uA, (b) 0.2 uA, and

(c) 0.3 uA as illustrated in figure 1 are imposed on proposed 4T2C

pixel circuits, where different minimum current errors are

observed. These minimum errors correspond to different gray

levels as shown in figure 7(a), (b), and (c), i.e. when inputting

some gray level, the minimum current error caused by variation K

can be obtained by selecting the suitable IREF. Therefore, panel

designers can follow this rule to achieve the best compensation

0 50 100 150 200 250

-30

0

30

60

Cu

rre

nt E

rro

r(%

)

Gray Level

VTH+0.3V_4T2C VTH-0.3V_4T2C VTH+0.3V_2T1C VTH-0.3V_2T1C

0 100 200

-3

0

3

Cu

rre

nt

Err

or(

%)

Gray Level

VTH+0.3V_4T2C

VTH-0.3V_4T2C

Figure 4. Simulation performances of Vth between new 4T2C and conventional 2T1C pixel circuits.

0 50 100 150 200 250-100

0

100

200

300

Curr

en

t E

rro

r(%

)

Gray Level

OVSS+1_4T2C

OVSS-1_4T2C

OVSS+1_2T1C

OVSS-1_2T1C

0 50 100 150 200 250

-3

0

3

Cu

rre

nt E

rro

r(%

)

Gray Level

OVSS+1_4T2C

OVSS-1_4T2C

Figure 5. Simulation performances of OVSS between new 4T2C and conventional 2T1C pixel circuits.

0 100 200 300

-20

-10

0

10

20

Cu

rren

t E

rro

r(%

)

Gray Level

K+20%_4T2C

K+10%_4T2C

K-10%_4T2C

K-20%_4T2C

K+20%_2T1C

K+10%_2T1C

K-10%_2T1C

K-20%_2T1C

Figure 6. Simulation performances of K between new 4T2C and conventional 2T1C pixel circuits..

P-19 / C.-C. Lin

SID 2014 DIGEST • 1015

result in proposed 4T2C pixel. Consequently, compensation

performances on variations, Vth in TFT process, power line IR-

drop, OVSS, and K are successfully verified in this simulation.

4. Summary A new 4T2C pixel circuit to compensate panel non-uniformity

and OLED degradation on AMOLED panel is proposed.

Considering remedying non-uniformity factors on the larger panel

fabricated in the process of IGZO-TFT, this pixel circuit is hence

formed by all n-type TFTs. The non-uniformity factors including

Vth and K in TFT process, OVSS caused from power line IR-drop

are successfully compensated. Moreover, driving voltage

imposing OLED, VOLED, is verified that is eliminated from the

driving formula, i.e. the effect of OLED degradation is removed.

Simulation performs excellent compensation results, in which

only from ±0.8% to ±1.74% current errors in average within Vth

and OVSS variation. As for variation K, current error is also

reduced from ±11.33% to ±7.49%. Last, an advanced method to

compensate variation K is proposed to achieve the best

compensation result.

5. References [1] C. H. Oh, H. J. Shin, W. J. Nam, B. C. Ahn, S. Y. Cha, S. D.

Yeo, “Technological Progress and Commercialization of

OLED TV,” SID Digest, 239-242, (2013).

[2] S. H. Jung, W. J. Nam, M. K. Han, “A New Voltage-

Modulated AMOLED Pixel Design Compensating for

Threshold Voltage Variation in Poly-Si TFTs,” IEEE

Electron Device Letters, 25, 690-692, (2004).

[3] M. H. Jung, O. Kim, “Voltage Distribution of Power Source

in Large AMOLED Displays,” Journal of the Korean

Physical Society, 48, S5-S9, (2006).

[4] M. Hack, J. J. Brown, J. K. Mahon, R. C. Kwong, R. Hewitt,

“Performance of high-efficiency AMOLED displays,”

Journal of the SID, 9, 191-194 (2001).

[5] W. J. Nam, J. S. Shim, H. J. Shin, J. M. Kim, W. S. Ha, K. H.

Park, H. G. Kim, B. S. Kim, C. H. Oh, B. C. Ahn, B. C. Kim,

S. Y. Cha, “55-inch OLED TV using InGaZnO TFTs with

WRGB Pixel Design,” SID Digest, 243-248 (2013).

[6] K. Y. Lee, C. P. Chao, “A New AMOLED Pixel Circuit

with Pulsed Drive and Reverse Bias to Alleviate OLED

Degradation,” IEEE Transactions on Electron Devices, 59,

1123-1130 (2012).

[7] C. L. Lin, Y. C. Chen, “A Novel LTPS-TFT Pixel Circuit

Compensating for TFT Threshold-Voltage Shift, and OLED

Degradation for AMOLED,” IEEE Electron Device Letters,

28, 129-131 (2007).

K+20%_4T2C

K+10%_4T2C

K-10%_4T2C

K-20%_4T2C

0 10 20 30 40 50-10

0

10

I_REF=0.1uA

Cu

rren

t E

rro

r(%

)

Gray Level

0 10 20 30 40 50

-10

0

10

I_REF=0.2uA

Cu

rren

t E

rro

r(%

)

Gray Level

K+20%_4T2C

K+10%_4T2C

K-10%_4T2C

K-20%_4T2C

0 10 20 30 40 50

-10

0

10

I_REF=0.3uA

Curr

ent

Err

or(

%)

Gray Level

K+20%_4T2C

K+10%_4T2C

K-10%_4T2C

K-20%_4T2C

(a) (b) (c)

Figure 7. Simulation performances of inputting, IREF’s (a) 0.1uA (b) 0.2 uA, and (c) 0.3 uA into proposed 4T2C pixel circuit.

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1016 • SID 2014 DIGEST