outline objective - hep.ph.ic.ac.ukdmray/pdffiles/apvcold.pdf · vfp vfs ipsf issf isha ipsp imuxin...

October, 2004 CMS Tracker Week 1

APV settings at cold temperatures

Objective:provide recommendations for APV I2C settings for cold operation,

for test beam and eventually CMS

Outline:what are the temperature effects and where do they come from?experimental method used to measure and compensate for T effectsrecommendations from results of measurements on 4 APV TIB module

Mark Raymond, Imperial College


IPREIPCASC

VFP VFS

IPSF ISSFISHA IPSPIMUXIN

VPSP

APV bias settings

all analogue bias currents on chip derived from one masterreference current (provides reference current to bias gen.)

Iref depends on Vt and R (not V250)

but Vt and R have T dependence

as T↓ , Vt ↑ 1mV / OC R ↓ 0.15% / OC

so Iref ↑ (simulation -> 0.233% / OC)

Reference currentcircuit

APV analogue chain


Temperature effects on APV

T reduces -> master Iref increases -> all I2C bias currents increase -> chip power increases

reduce bias currents (I2C parameters beginning with ‘I’) to compensate

simple method: adjust each parameter by same factor and round to nearest integer

Other T effects

T reduces -> µ increases => gm increases => circuit speed increases, pulse shape changes and needs re-tuning

APV gain also depends on R at MUX I/P stage, so gain goes up as T reduces

gain


Experimental setup

VUTRI card

TIB module

environmentalchamber

flushed withnitrogen


Experimental setup

sensor

12

56

Pt100 temperature sensors

peltier

peltier

hybrid

Al plate

hybrid in contact with Al plate (thermal grease)2 peltier elements cool platePt100 sensor measures hybrid temperature (where APVs 3 and 4 would be if 6 chip module)another Pt100 measures Al plate underside temperature

hybrid temp. ~3O > Al plate temp.temperature stability ~ ± 2O


Experimental setup

peltierfan-cooled

heatsink

90Srsource

scintillatorbeneath sensor

Pt100 hybrid in thermalcontact with Al plate

peltier


Method1) wait for environment to stabilise at target hybrid temperature

2) adjust peltier current to fine tune hybrid temperature to target value

3) tune I2C Ibias parameters to get ~ same V250 and V125 currents as for standard values @ +30O

4) tune ISHA to achieve close approx. to 50 ns peak mode pulse shapeaverage of 16 pulse shapes corresponding to one test pulse linepulse shape tuned “by eye”not found necessary to alter VFS setting (or VPSP)

120

100

80

60

40

20

0

ADC

uni

ts

3002001000time [nsec]

+30o

Isha=46

120

100

80

60

40

20

0

3002001000time [nsec]

-20o

Isha=30

+30 -20peakideal CR-RCdecon


Pulse shapes120

80

40

0

ADC

uni

ts

3002001000

+30o

Isha=46

120

80

40

0

ADC

uni

ts

3002001000

+10o

Isha=38

120

80

40

0

3002001000

+20o

Isha=45

120

80

40

0

AD

C u

nits

3002001000[nsec.]

-10o

Isha=30

120

80

40

0

3002001000

0o

Isha=32

120

80

40

0

3002001000[nsec.]

-20o

Isha=30

Pulse shapes for all temperatures aftertuning for correct power and pulse shape

VFS = 70 for all temperatures

ICAL=80 in all cases, but outputsignal amplitude increases as T↓

1.21-20

1.17-10

1.120

1.08+10

1.04+20

1.00+30

relativetest pulse height

dependenceon T

ICAL derived from master ref. butgain also increases as T↓ so twocontributing effects here


400300200100

0

30025020015010050[nsec.]

-20o

400300200100

0

AD

C u

nits

30025020015010050[nsec.]

-10o

400300200100

0

30025020015010050

0o400

300200100

0

AD

C u

nits

30025020015010050

+10o

400300200100

0

30025020015010050

+20o

400300200100

0

AD

C u

nits

30025020015010050

+30o

400300200100

0

250200150100500[nsec.]

-20o

400300200100

0

AD

C u

nits

250200150100500[nsec.]

-10o

400300200100

0

250200150100500

0o400

300200100

0

AD

C u

nits

250200150100500

+10o

400300200100

0

250200150100500

+20o

400300200100

0

AD

C u

nits

250200150100500

+30o

Peak & deconvolution pulse shapesICAL: 0 -> 240 in steps of 40 (1 mip ~ 60 ADC units)


Chip-to-chip variation on this hybrid80

70

60

50

40

30

20

10

0

AD

C u

nits

300250200150100500[nsec]

apv5 apv6 apv2 apv1

80

70

60

50

40

30

20

10

0

AD

C u

nits

300250200150100500[nsec]

apv5 apv6 apv1 apv2

room temperature measurement – hybrid at 30O

same I2C parameters for all 4 chips (including VFS and ISHA)small ICAL response differences here (but absolute value of test charge subject to chip to chip variation)

and small pulse shape differencesbut these chips will have been picked from same wafer (probably same location on wafer)how will pulse shape vary across full production?

-> look at wafer probe data


120100806040200

Lot_5

120100806040200

Lot_3

peak and deconvolution mode pulse shapes are acquiredfor every chip at wafer test time (for same I2C parameters)

example data here (presented at LECC’02) for lots 1 to 5(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/APV_LECC02_HEP.pdf)

plots show pulse shapes for all KGD normalised to max. pulse height

120100806040200

Lot_1

120100806040200

Lot_3

120100806040200

Lot_2

120100806040200

Lot_5

120100806040200

Lot_4

120100806040200

Lot_1

120100806040200

Lot_2

120100806040200

Lot_4

Peak DeconvolutionLot 1 Lot 1

Lot 4

Lot 5Lot 3

Lot 2

Lot 3 Lot 5

Lot 2 Lot 4

Wafer to wafer pulse shape variation

conclusion

one set of start-up I2C parameters will suit all chips, at least for a particular module type

fine tuning can then followlater


Beta pulse height spectraPeak Mode Deconvolution

90Sr source, sensor HT 250V

strip signal included if neighbour signal < 3 x noise

S/N values quoted for mostprobable signal

500400300200100

0

coun

ts

200150100500

+30o

pk ch 57S/N=25.7

400300200100

0

coun

ts

200150100500

+30o

pk ch 56S/N=16.6

400300200100

0200150100500

ADC units

-20o

pk ch 61S/N=29.0

300

200

100

0200150100500

ADC units

-20o

pk ch 60S/N=17.9

best way to measure gain changes with T gain increase, +30 -> -20 = ~ 7% (7.5% expected from gain resistor)S/N increase: ~13% peak mode, ~8% deconvolution

not quite the same but significant errors here (statistics and details of pulse shape)


Beta pulse height spectra

400300200100

0200150100500

ADC units

-20o

pk ch 61S/N=29.0

400300200100

0

coun

ts

200150100500ADC units

-10o

pk ch 59S/N=28.1

500400300200100

0200150100500

0o

pk ch 58S/N=27.6

500400300200100

0

coun

ts

200150100500

+10o

pk ch 57S/N=26.4

500400300200100

0200150100500

+20o

pk ch 57S/N=24.6

500400300200100

0

coun

ts

200150100500

+30o

pk ch 57S/N=25.7

300

200

100

0200150100500

ADC units

-20o

pk ch 60S/N=17.9

250200150100500

coun

ts

200150100500ADC units

-10o

pk ch 58S/N=18.1

300

200

100

0200150100500

0o

pk ch 56S/N=17.8

200150100500

coun

ts

200150100500

+10o

pk ch 55S/N=16.8

250200150100500

200150100500

+20o

pk ch 57S/N=16.6

400300200100

0

coun

ts

200150100500

+30o

pk ch 56S/N=16.6

Peak Mode Deconvolution


Recommended I2C parameters vs. T

368364374368370366power/APV

147514551479147314801465total power[mW/module]

707070707070VFS

303032384546ISHA

434343434343VPSP

303030303030VFP

303032333434IMUXIN

484852535455IPSP

303032333434ISSF

303032333434IPSF

454549495152IPCASC

858592939698IPRE

- 20O- 10O0O+ 10O+ 20O+ 30O all bias current params (those starting with ‘I’) adjusted by same factorto achieve ~ same total module power at each temperature

over ~ 10O range power variation small(~ few %) so not necessary to re-tuneparameters for variations at this level

slight over-adjustment between 0 -> -10so no further adjustment needed for -20

power/APV = total power / 4 but this alsoincludes APVMUX, DCU and PLL power(not possible to separate out)

recommend values in –10O column for CMS operation

Note: this doesn’t apply to VPSP, ISHAand VFS. ISHA and VFS will depend on sensor type and some chip to chip variationcan also be expected


Digital header amplitudedigital header (and tick mark) amplitude varies with T because levels are set by current ref. circuit similar to that for bias generator

1.111.091.071.051.021.00relative dig. head amplitude

- 20O- 10O0O+ 10O+ 20O+ 30O

dig.headamp.


analogue baseline

VPSP setting

VPSP setting adjusts analogue baseline position

works by introducing DC voltage offset at APSP O/P which in turn produces DC offset current flowing in the MUXstages

choice of VPSP for this studyno major movement in analogue baseline observed with temperaturesame value (43) used throughout

sets baseline at ~ 25% relative to dig. head amp.allows plenty of room for signals and negativeCM excursions

note: power penalty if set higher than necessarye.g. ~ 7% power increase if move from 25%to 50% level

0

100%

18001600140012001000800600400200

0

tota

l mod

ule

pow

er [m

W]

70 60 50 40 30 20 10 0

VPSP setting (decimal)

9080706050403020100

baseline pos'n [% of dig. am

p.]

50%

module powerbaseline pos’n


What happens if no I2C change with T?

100

80

60

40

20

0

AD

C u

nits

250200150100500time [nsec]

30 20 10 0 -10 -20

100

80

60

40

20

0

AD

C u

nits

30025020015010050

30 20 10 0 -10 -20

standard I2C settings used for all temperatures

module power increases by ~ 10% (+30 -> - 20)

test pulse amplitude increases

gm increase in shaper and preamp -> rise-timefaster as T decreases

deconvolution pulse shape sensitive torise-time


T measurement using DCU

DCU ADC value shows linear dependenceon hybrid temperature measured with Pt100

9.65 slope value similar to 9.22 quoted inDCU manual

clearly no problem to use DCU to measurehybrid temp. if calibration factor known

2700

2600

2500

2400

2300

2200

DC

U A

DC

val

ue

3020100-10-20hybrid temp. [deg.C]

2412+9.65/deg.


Summaryrecommendations provided for APV I2C settings for low temperature operation

based on studies of 4 chip TIB modulehybrid temperature used as reference

provides starting point for module operation but free parameters still existVPSP sets analogue baseline. remember power penalty if set highISHA/VFS tune pulse shape

~ some chip to chip variationwill be different for different sensor types

results here consistent with previous studies on single chipspresented CMS week in Catania (June 2001, E. Noah)

note available with more details:http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf

(preliminary version already circulated)

ongoing workverify parameter choice for 6 chip TIB module – expect to be same as 4 chip versionlook at other module types – old TOB module available

70VFS

30ISHA

43VPSP

30VFP

30IMUXIN

48IPSP

30ISSF

30IPSF

45IPCASC

85IPRE

- 10O


Supply currents vs. T if no I2C change

500

400

300

200

mod

ule

curre

nt [m

A]

403020100-10-20

hybrid temperature [ oC]

I125 I250 total I250 digital only I250 analog only

standard I2C settings used for all temperatures

I125 shows 16% increase, +40 -> -20(close to 14% simulated)

I250 total includes digital and analogue

I250 digital only measured by switching biasoff in mode registers

small ~ 3.5% increase, +40 -> -20

I250 analogue only = I250 total – I250 digital only~ 21% increase (> I125 but probably includessome contribution from analogue baseline shift)

module power+40 -> -201.43 W -> 1.56 W ~ 10% increase

but extra power also dissipated in cables

outline objective - hep.ph.ic.ac.ukdmray/pdffiles/apvcold.pdf · vfp vfs ipsf issf isha ipsp imuxin...

Documents