orthogonally modulated cmos readout …does not display a currently valid omb control number. 1....

December 13, 2004Research work supported by the Army Research Laboratory

Jorge A. GarcíaVisiting Assistant Professor

Electrical and Computer Engineering DepartmentUniversity of Delaware

ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS

Report Documentation Page Form ApprovedOMB No. 0704-0188

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1. REPORT DATE 13 DEC 2004 2. REPORT TYPE

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4. TITLE AND SUBTITLE Orthogonally Modulated CMOS Readout Integrated Circuit for Imaging Applications

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7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) University of Delaware,Department of Electrical and ComputerEngineering ,Newark,DE,19716

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Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT

FOR IMAGING APPLICATIONS

• Introduction and motivation• Contribution Phase I: Proof of principle

Orthogonal encoding readout system descriptionPrototype system design and verificationConclusions

• Contribution Phase II: Improving the system performance

Readout cell improvementsTransimpedance amplifier integration

• Conclusion and brainstorm on further improvements

Read Out Integrated Circuit ROIC

ROIC may include:Amplifier electronics Control signal generatorsAnalog-Digital ConversionOn-chip Digital Signal Processing

Distance information: a time of flight measurement

FFT along n

FM chirpgenerator

TriggerCircuit

LASER

N/2 rangecells 4-D

image( x, y, z,

reflectance)

N samples4-D data set

( x, y, n,intensity )

ROICSelf-mixingdetector array

FM/CW LADAR system

Motivation: Readout Integrated Circuit ROIC for active/passive imaging systems

ROIC conventional architecture

Time Domain Multiple AccessControl signals access every readout cell in a time scheduled manner, sampling the voltage signals and transferring them to the readout bus.

It requires faster electronics for bigger photodetector arrays.

Each readout cell must be capable of storing the required charge, which becomes a problem for big array sizes (1024x1024).

_

+

VB

Vout

Read Out Cell Architectures

From Direct Injection to Capacitive

TransImpedanceAmplifier

• Each column is multiplied by a unique code, and the multiplied signals are summed in the row common bus

• Codes are chosen to minimize cross talk

• Current-to-voltage amplifier per row

• Multiplexer scheme to generate single data stream

ROIC proposed architecture

Orthogonal encoding ROIC

Orthogonal Encoding ROICFirst Phase Design Tasks

Test system with four readout cells and a discrete component I-V amplifier

Design of the Active Readout Cell

To design and fabricate a test chip for a proof of principle of the active 2D readout technique.

Active Readout Cell:Design Requirements

Multiplies the input current by the codeProvides detector virtual groundCouples the detector impedance to the busReduces charge injection noise

Readout cell for orthogonal encoding

Active Readout Cell:Implementation

Differential code multiplier

Readout cell for orthogonal encoding

( ) ( ) ( ) [ ( ) ( )] [ ( ) ( )],od o o in ini t i t i t i t i t c t c t+ − + −= − = − ⋅ −

( ) ( ) ( ) ( ) ( ) ,

( ) ( ) ( ) ( ) ( ) ,o in c in c

o in c in c

i t i t c t n i t c t n


+ + −

− + −

= ⋅ + + ⋅ +

= ⋅ + + ⋅ +

Differential output current

Active Readout CellCurrent Locked Loop ILL

Characteristics

Low input impedance

1 1 4 1 4

1 2 3 1 4 2 3.

, with 1

g

s low freq

v g g g gv g g g g g g

γ γγ

− −= = =

− −Detector virtual ground

.1

1 (1 )in low freqZ

gγ= −

Active Readout Cell

Detector virtual ground Low input impedance

Differential code multiplier

Current Locked Loop (ILL)

ILL Replica

Current amplifierCurrent gain High output impedanceCharge cancellation

Signal-code modulation Balanced charge injection

Test chip implementation

Test chip with cell prototypes

4 instances of active readout cell

4 instances of cell with input modulator only

Prototype system testing

Custom printed circuit board for electro-optical testing

PowerConditioning Amps

Code inputs

DUTElectrical inputs

Amps

ROIC electrical verification set up

Code signals generated and conditioned externally

Voltage sources + Resistors emulate electrical current inputs

High-gain off-chip transimpedanceamplifiers on the pcb

Data is acquired and processed in the computer

Test chip with cell prototypes

Verification Results

Proof of principle system with 2 encoding cells

c1

in1i

c1------c2

in2i

c2------

Common Bus To i-v amplifier

Test results

Prototyping phaseconclusion

Satisfactory results with the 2 encoding cells experiment confirm validity of the orthogonal encoding scheme for readout circuits

Integrating the transimpedance amplifiers with improved versions of readout cells should enhance noise performance of the overall system

Applicability extends to passive imaging systems

Depending on the system conditions, the orthogonal encoding architecture is advantageous with respect to the conventional time-multiplexed scheme

Active Readout Cell Improvements

Iin

1:m1:1

VSS

IBIAS

Q6

Q4

Q2Q1

Q3 Q5

VDD

Iout

23 34Qi kT gγ=

( )2 55 3

3

4 1 4 1outgi kT g kT g m mg

γ γ⎛ ⎞

= + = +⎜ ⎟⎝ ⎠

ILL current gain and noise performance

Input referred noise

Minimize g3

Maximize current gain m

( )22

32

14 .out

ieq

mii kT gm m

γ+

= =

Active Readout Cell ImprovementsFully differential architecture

Noise from cascodemirrors is minimized

Additional current mirror for complementary output

Improved charge injection cancellation and offset

IBIASn

VSSVSS

IBIASp

1:m

vdd

Q10

Q9Q8

Q7

Q5Q3

Q1 Q2

Q4

Q6 Q12

Q11Q24

Q23 Q22

Q21

Q20Q19

Q18 Q17

Q16

Q15Q14

Q13

vss

1:m

Iinp Iinn

IoutnIoutp


( ) ( )( ) ( ) ( )

3 2 1 1 4

1 1 3 2

( )( ) 1( )

// P gs Nsin

s in gs P N

g sC g s C C g gV sZI s sC g sC g sC g sC

+ + + −⎛ ⎞= = ⎜ ⎟ + + +⎝ ⎠

Input impedance engineering

Input impedance without Cin

Small-signal model

Frequency / Hertz

100 1k 10k 100k 1M 10M 100M 1G 10G 50G

ILL

inpu

t im

peda

nce

/ Ohm

200

400

1k

2k

4k

10k

20k

40k

100k

First zero z1

First pole p1

Second zero z2

Second pole p2

Third pole p3

From small-signal model, solve for Zin


Frequency / Hertz

100 1k 10k 100k 1M 10M 100M 1G 10G 50G

Impe

danc

e / O

hm

40

100

200

400

1k

2k

4k

10k

20k

40k

100k

200k

400k

1M

2M

4M

Input pad capacitance ILL input impedance

Total input impedance

1 3 3 21

1

1 3 3 22

1

31

22

13

1

2 ( )

2 ( )

z gs N P

P gs N

z gs N P

P gs N

P

N

gs

K C g C g C gz

C C C

K C g C g C gz

C C CgpCgpCgp

C

− − −=

+

− − − −=

+

= −

= −

= −

Input impedance engineering (cont’d)

Input impedance with Cin

CP controls p1 and z1 , but also moves z2 to the leftCN moves p2 close to z2 , canceling its effectp3 determines overall gain-bandwidth

2 2 2 2 2 2 2

1 3 1 3 1 4 2 3 3 1 4 2 3 22 ( (2 )) 2 (2 )gs gs N P N N P PC g C C g C g g g g C g C C g g g g C g+ + − + + − +

ILL pole-zero analysis

Kz=


270fCcompp

500fCin

VDD

Q3

Q1 Q2

Q41:1

Iin

70fCcompn

Input impedance engineering (cont’d)

Compensated input impedance with Cin

CP = 270fF and CN = 70fF compensate the input impedance for Cin = 500fF

Frequency / Hertz

1k 2k 4k 10k 20k 40k 100k200k400k 1M 2M 4M 10M 20M 40M 100M 400M 1G 2G 4G 10G

Ohm

1k

2k

4k

10k

20k

40k

100k

200k

400k

Input pad capacitanceCin=500fF

Compensated ILLinput impedance

Total input impedance

The z2/p2 doublethas vanished

Improved Active Readout Cell Performance

I-diff

-out

/ A

Frequency response

Iout

p / n

A

-3

-2

-1

0

1

2

3

4

Time/µSecs 5µSecs/div

0 5 10 15 20 25 30 35 40 45Io

utn

/ nA

-3

-2

-1

0

1

2

3

4

Ioutp, 3.8nA peak

Ioutn, 3.8nA peak

Transient response

Designed for 500kHz code bandwidth (16 cells)

Current gain of 3.8A/A

Improved Active Readout Cell Performance

Time/µSecs 5µSecs/div

0 5 10 15 20 25 30 35 40 45

Volta

ge@

Iinp/

Iinn

/ mV

-3

-2.9

-2.8

-2.7

-2.6

Virtual ground [email protected]

Virtual ground regulation Noise performance

Between -3.1mV and -2.6mV Input referred noise 400fA/rtHz

V/rt

Hz

500f

1p

2p

3p

Frequency / Hertz

400 1k 2k 4k 10k 20k 40k 100k 200k 400k 1M

Inpu

t Noi

se /

A/rt

Hz

Y1

500f

1p

Total output noise density

Input referred noise density

Noise from Q3 and Q8

Noise from Q25 and Q30

Transimpedance amplifier implementation

Capacitive TIA (CTIA)

RST switch injects charge and produces sampling (kT/C) noise

CDS structure removes sampling noise

SH capacitor produces voltage divider

CTIA with correlated double sampling (cds)

CTIA system-level implementation

Control signals

Dynamics of CTIA system with cds

OTA output

cdsoutput

System output


Fully differential CTIA system

Advantages of fully differential CTIA system

Transient response of

Single-ended vs. Differential output

Vop,

Von

/ m

V

-30

-20

-10

0

10

20

30

Time/µSecs 200nSecs/div

1.8 2 2.2 2.4 2.6 2.8Vo

ut /

mV

0

10

20

30

40

50

60

single-ended outputs still exhibit pedestal error

differential output effectively cancels the pedestal error


External OTA compensation

Input stabilization switches

External OTA compensation and sizing of switches and capacitors

CCDS = 5pF, CSH = 1pF, Ccomp=3pF, Cint = 50fF

Switches designed for worst-case scenario RSW~1kΩ

OTA

OTA circuit-level implementation

Design requirements

2-stage Miller compensated OTA, design requirements

•Gm > 250mSie•avo (2% settling accuracy) > 40k•Input referred noise < 5nV/rtHz•Dominant pole and non-dominant

pole more than three decades apart

•Output common-mode < 10mV•CMRR > 60dB•Input differential capacitance not

to exceed 15pF•Output swing of 2.4Vpk-pk•Dual power supplies of ±2.5V•Best effort on power consumption

and layout area

Ccn

Q6

Q1

Q10

Votan

vd2 vd1

Votap

VBIASp

Q2

VSS

Vin

Q8

Vipvx

Q4

VBIASn

VDDVDD

Q3

Q7Q9

Ccp

OTA design methodology


Transistor models from vendor are used to optimize the design of a single stage of amplification with active loading

Bias conditions are replicated, and noise from biasing strategy is properly filtered out

Design results are back-annotated in work sheet

First and second stage design strategy

VSS

W=w pL=lp

Q5

M=mp

W=w pL=lp

Q3

M=mp

W=w nL=ln

Q2

M=mn

vout

AC 1 0V3

VBIAS

VBIAS

1uC2

1uC1

20uI1

VDD

vin

E1

1100fC3

W=w nL=ln

Q1

M=mn

W=w pL=lp

Q4

M=mp

vout

Circuit for design of amplification stage


Q13 and Q3 compute common-mode voltage from the OTA output and “compare”it to the desired value (GND)

The amplifier produces a current output that regulates the common-mode voltage in the differential amplifier

Common-Mode amplifier design

Common-mode amplifier circuit

W=5uL=5uM=4

Q13

iout

imir

GND

ibias

CSp

cascP

outC

W=10.15uL=2.1u

Q22

W=10.15uL=2.1u

Q21

W=10.15uL=0.7u

M=8

Q18

vss

W=10.15uL=2.1u

M=2

Q1

W=10.15uL=2.1u

M=2

Q16

W=10.15uL=2.1u

M=2

Q6

W=10.15uL=0.7u

Q7

W=10.15uL=0.7u

Q8

W=10.15uL=0.7u

Q9

vdd

W=5uL=5u

Q11

W=5uL=5u

Q12

W=5uL=5uM=4

Q2

W=5uL=5uM=4

Q4

W=5uL=5uM=4

Q3

W=10.15uL=1.925u

M=8

Q5

W=10.15uL=1.925u

M=8

Q10

W=10.15uL=1.925u

M=8

Q14

W=10.15uL=0.7u

M=8

Q19

W=11.55uL=1.05u

Q20

vdd

inA inB

outG

CSn

tailBtailA

curBcurA

OTA design methodologyFinal schematic for differential OTA

W=6.3uL=4.025u

Q10

M=16

100uI1

W=6.3uL=4.025u

Q4

M=16

W=6.3uL=4.025u

Q3

M=16

VG3

VDD

W=6.3uL=4.025u

Q11

M=16

vd2

vonvop

W=5.075uL=5.075u

Q9

M=16

W=5.075uL=5.075u

Q5

M=16

VDD

vin

W=12.43uL=2.975u

Q1

M=16

W=12.43uL=2.975u

Q2

M=16

vip

VSS

W=5.075uL=5.075u

Q6

M=16

W=5.075uL=5.075u

Q7

M=16

vd1

VG3

VG7

140f

Ccp

140f

Ccn

W=5.075uL=5.075u

Q6A

M=16

W=5.075uL=5.075u

Q12

M=16

W=6.3uL=4.025u

Q8

M=16

OTA Performance

:vod/V 1V/div

-2 -1 0 1 2

k

0

5

10

15

20

25

30

35

40

45

26.181545

41.54574k41.57192k

2.4105742-1.208894 1.2016798

Small-signal gain avo

Large-signal gain Avo

Output voltage swing

Frequency / Hertz

10 20 40 100 200 400 1k 2k 4k 10k 20k 40k 100k200k400k 1M 2M 4M 10M 20M 40M 100M 400M 1G 2G 4G 10GVo

d, V

d1 /

V

200m

400m

1

2

4

10

20

40

100

200

400

1k

2k

4k

10k

20k

40k

100k

First stage gain

Total voltage gain

Non-dominant pole @ 8.25MHz

Dominant pole @11.01kHz

Open-loop gain Frequency response

Open-loop gain exceeds 40,000 for the operation range (2.4Vpk-pk)

Dominant and non-dominant pole about three decade apart

OTA Performance

Frequency / Hertz

10 20 40 100 200 400 1k 2k 4k 10k 20k 40k 100k 400k 1M 2M 4M 10M20M40M 100M 400M 1G 2G 4G 10G20G40G 100G

vod

/ V

20m

40m

100m

200m

400m

1

2

4

10

20

40

100

200

400

1k

2k

4k

10k

20k

40k

100kDominant pole @ 1.66kHz

with switch equivalent resistor of 100 Ohm

with switch equivalent resistor of 500 Ohm

for unitary feedback, the phase margin is close to 80 degrees

Frequency response with external compensation

Input differential capacitance

External compensation of 3pF yields phase margin of about 80 degrees

Compensation switch optimally sized for zero-nulling

Cin ~ 12pF at low frequencies

Decays for high frequencies because of absence of Miller effect

Frequency / Hertz

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G 100G 1T 5T

Cid

/ F

1p

2p

5p

10p

-10.9499p

12.09349p

1.143597p

10.00000G10.000000 10.00000G

Miller effect on the input Cgs decreases as the gain lowers

OTA PerformanceVo

p, V

on /

mV

-30

-20

-10

0

10

20

30

Time/µSecs 200nSecs/div

1.8 2 2.2 2.4 2.6 2.8

Vout

/ m

V

0

10

20

30

40

50

60

single-ended outputs still exhibit pedestal error

differential output effectively cancels the pedestal error

Transient response with external compensation

Input referred noise density

External compensation of 3pF effectively reduces differential transient ringing

CMFB amplifier is also compensated (1pF) to reduce common-mode voltage transient ringing

Low frequency input referred noise around 5nV/rtHz

High frequency noise density is not relevant in this case

Frequency / Hertz

1k 2k 4k 10k 20k 40k 100k 200k 400k 1M 2M 4M 10M 20M 40M 100M200M400M 1G 2G 4G 10G

Inpu

t Noi

se /

V/rtH

z

500p

1n

2n

5n

10n

Low frequency input referred noise power density

Input referred noise at this requencies is irrelevant

Second generation ROICFour 1x16 arrays + Fully differential CTIA

Readout cell physical design

Ioutp

IBIAS

wn=2.975u, ln=2.1uwp=1.4u, lp=4.025uwn1=3.3u, ln1=4.025uwn2=4.9u, ln2=4uwp1=3.3u, lp1=4.025uws=1.8u, ls=1.05u, ms=1

70fC4

70fC3

W=1.575uL=1.05u

Q10

W=1.575uL=1.05u

M=5

Q12

W=1.225uL=2.1u

M=5

Q14

W=1.225uL=2.1u

Q15

wn1ln1

Q16

wn1ln1

Q13wn1ln1

Q11

wn1ln1

Q9

wp1lp1

Q34

wp1lp1

Q26

wplp

Q25

M=4

500fC2

270fC1

wplp

Q4

VDD

wnln

Q2

wnLn

Q1

wplp

Q3

VSS

wplp

Q8

wnln

Q7

wnln

Q6

VDD

wplp

Q5

270fC6

wplp

Q24

M=4

wplp

Q30

M=4

wn2ln2

Q17

wn2ln2

Q18wn2ln2

Q19

wn2ln2

Q20

wp1lp1

Q21

wp1lp1

Q23

wslsMs

Q31

wslsMs

Q29

wslsMs

Q28

wslsMs

Q27

code

codeb

code

VSS

500fC5

W=1.225uL=2.1u

Q33

W=1.575uL=1.05u

Q32

wplp

Q22

M=4

VDD

Transistor parameters

Ioutn

IinnIinp

CTIA physical design

Four-capacitor layout using common-centroid techniques

Dummy cap in the middle shorted to ground

Matching transistors and capacitors

All differential pairs are designed with multi-finger, common-centroid structure

The differential OTA is divided into differential pair sections

ROIC physical designFully differential CTIA amplifier

ROIC physical design

Conclusion

( ) ( ) ( ) [ ( ) ( )] [ ( ) ( )],od o o in ini t i t i t i t i t c t c t+ − + −= − = − ⋅ −

Satisfactory results with the prototype experiment confirm validity of the orthogonal encoding scheme for readout circuits

Expect system performance improvement with the design optimization of the readout cell and the integration of the fully differential CTIA

The readout cell with the code-modulator only is an outstanding candidate for highly-scalable imaging systems. Its characteristics: only four transistors, zero noise, no power consumption, no band width limitations.

Further improvement is accomplished if differential photodetector devices are used

( ) ( ) ( ) ( ) ( ) ,

( ) ( ) ( ) ( ) ( ) ,o in c in c

o in c in c



+ + −

− + −

= ⋅ + + ⋅ +

= ⋅ + + ⋅ +

Conclusion (cont’d)Take advantage of switched nature of the system to cancel charge injection peaks from readout cells.

With code-modulator-only cells the system becomes highly-scalable but the noise performance of the OTA amplifier needs to be improved by one order of magnitude

Code-modulator-only readout cell array Capacitive Transimpedance

amplifier per row

Conclusion (cont’d)

Integrating an amplifier to perform differential to single-ended conversion inside the chip would improve the system performance (pedestal voltages and vestigial voltage spikes would be cancelled inside the integrated circuit)

Capacitive Transimpedanceamplifier per row

Single-ended output

Differential amplifier per row

Acknowledgements

Thanks to everybody who has been involved in the dissertation process in one way or another

Fouad, Bill, Mayra

LADAR group, thanks so much for the support

orthogonally modulated cmos readout …does not display a currently valid omb control number. 1....

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