optimization of sub-0.1-μm offset Γ-shaped gate mhemts for millimeter-wave applications

Optimization of sub-0.1-mm offset G-shaped gate MHEMTs

for millimeter-wave applications

Min Han, Myung-Sik Son*, Jung-Hun Oh, Bok-Hyung Lee, Mi-Ra Kim,Sam-Dong Kim, Jin-Koo Rhee

Millimeter-wave Innovation Technology Research Center (MINT), Dongguk University, 3-26 Pildong, Joonggu, Seoul 100-715, South Korea

Received 11 June 2004; received in revised form 18 July 2004; accepted 20 July 2004

Abstract

We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors

(MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated

hydrodynamic simulation for the sub-0.1-mm offset G-gate In0.53Ga0.47As/In0.52Al0.48As MHEMTs shows a reasonable agreement with the

electrical characteristics measured from the fabricated 0.1 mm devices. We have calibrated all the parameters using the measurement data

with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-mm devices. Being simulated

with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 mm, a gate length of 0.05 mm, a

barrier thickness of 10 nm and a channel thickness of 12 nm.

q 2004 Elsevier Ltd. All rights reserved.

PACS: 84; 84.40.Kx; 84.40.Lj; 85; 85.30.De; 85.30.Tv

Keywords: Metamorphic HEMT (MHEMT); InGaAs; InAlAs; GaAs-based HEMT; Transconductance; Cut-off frequency; Maximum frequency of oscillation;

Millimeter-wave frequency

1. Introduction

High electron mobility transistors (HEMTs) on InP

substrates have demonstrated superior microwave and low

noise performances compared to the pseudomorphic

HEMTs on GaAs substrates [1–4]. The excellent device

performance of the InP-based HEMTs operating in the

W-band is mostly due to the lattice-matching InGaAs/

InAlAs/InP material system. However, compared to the

GaAs-based devices, InP-based HEMTs have some critical

drawbacks, such as the mechanical fragility of the wafers

and the higher material cost. Moreover, InP-based HEMTs

may not be quite proper for large-scale device production

because of very slow backside-etching rate of the InP

material. In recent decades, active research has been

performed on GaAs-based metamorphic HEMTs

0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved.

doi:10.1016/j.mejo.2004.07.005

* Corresponding author. Tel.: C82 2 2260 8699; fax: C82 2 2260 3690.

E-mail address: [email protected] (M.-S. Son).

(MHEMTs) to address the needs for both high microwave

performance and low device cost [5–8]. The use of

metamorphic buffers on GaAs substrates was introduced

to accommodate the lattice mismatch between the substrate

and the active layers, as well as to avoid the InP substrates.

With the use of metamorphic buffers, unstrained InGaAs/

InAlAs heterostructures could be grown over a wide range

of indium contents for the InGaAs channels, thereby

exhibiting device performances comparable to those of

InP-based HEMTs. For examples, excellent maximum

frequencies of oscillation (fmax) of 200–400 GHz have

been introduced in recent MHEMTs adopting 0.1–0.2 mm

gate lengths [9–15].

When the sub-0.1-mm MHEMTs are employed for the

millimeter-wave monolithic ICs (MIMICs), such as oscil-

lators, low noise amplifiers, and power amplifiers, to

achieve extremely superior DC and RF performances,

effects of the device scaling on the electrical characteristics

need to be well predicted theoretically. This is because

Microelectronics Journal 35 (2004) 973–983

www.elsevier.com/locate/mejo

http://www.elsevier.com/locate/mejo

M. Han et al. / Microelectronics Journal 35 (2004) 973–983974

a variety of unpredicted phenomena can be dominant in

such a small-size devices. For this purpose, we develop a

device model for In0.53Ga0.47As/In0.52Al0.48As/GaAs

MHEMTs by using a hydrodynamic transport model built

in a commercial ISE-DESSIS simulator [16], and the

calculated results show a reliable agreement of the electrical

characteristics of the fabricated 0.1 mm gate length

MHEMTs. With the uses of the calibrated parameters, we

perform the simulations on the DC and RF performances at

various source-drain spacings (2, 2.5 and 3 mm) and gate

lengths (0.05 and 0.1 mm). Moreover, the effects of the

vertical scaling, such as the thickness variation of the barrier

and channel layers, are also examined.

Fig. 1. Fabricated 70 mm!2-finger MHEMT with a 0.1-mm offset G-shaped

gate. (a) Schematic of the cross-sectional epitaxial structure. (b) Schematic

of the 0.1-mm offset G-gate with a wide-recess structure. (c) Planar view of

the fabricated 70 mm!2-finger MHEMT.

2. Fabrication, characterization and model of 0.1-mm

offset G-shaped gate In0.53Ga0.47As/In0.52Al0.48As/GaAs

MHEMT

0.1-mm offset G-gate MHEMTs with a source-drain

spacing of 2 mm were fabricated, and the measured DC and

RF characteristics are described in the next section. Shown

in Fig. 1(a) and (b) are the layout and a schematic of the

cross-sectional structure of the MHEMT. The planar view of

a fabricated device is also shown in Fig. 1(c), and the 2

fingers with a gate width of 70 mm are adopted for the

devices (hereafter, we call it 70 mm!2). We performed the

iterative calibrations for the model based on the hydro-

dynamic transport model using the identical epitaxial and

gate structures with those of the fabricated devices, as

shown in Figs. 1 and 2. The calculation results from the

calibrated model and the measured DC and RF data are

compared in Fig. 3.

The GaAs-based epitaxial structures for MHEMTs were

grown on 4-in. semi-insulating (SI) (100) GaAs substrates

by using a molecular beam epitaxy (MBE). As shown in

Fig. 1(a), graded buffer layers of 1 mm thick InxAl1KxAs

were grown on SI GaAs substrates by varying the indium

mole fraction from 0 to 0.5; thereafter, 400 nm thick

In0.52Al0.48As buffers were grown to protect the active

layers from the potential impurities coming from the

underlying structures on top of the buffers; active layers

with 23 nm In0.53Ga0.47As channel layers were grown with

double Si d-dopings. Very thin nC In0.53Ga0.47As cap

layers were then grown to provide ohmic contacts at the

source and the drain regions. The measured electron sheet

density and the Hall mobility of the grown epitaxial layers at

room temperature were about 3.4!1012 cmK2 and

9700 cm2/V s, respectively.

As shown in Figs. 1 and 2, the gate electrode is located at

an offset position from the center toward the source. The

structural improvement of the offset gate due to a reduction

in the distance between the source and the gate enhances

the cut-off frequency (fT) and the maximum stable gain

(MSG) by minimizing the gate-to-drain capacitance (Cgd),

as well as the drain resistance (Rd) [17]. In our devices,

the distances between source and drain and between the

source and gate foot were 2 and 0.65 mm, respectively.

The MHEMTs were fabricated in the following

sequences. First, mesa etching was performed to provide

isolated active areas by removing an w200-nm thickness

in an etchant of phosphoric acid/H2O2/H2O (1:1:60),

followed by the formation of ohmic contacts by using the

thermal evaporation of AuGe/Ni/Au (125/28/160 nm)

layers and rapid thermal annealing at 320 8C for 30 s. The

measured specific contact resistance of the ohmic contacts

was w1!10K7 U cm2. The gate recess was done by

Fig. 2. Cross-section view of the device structure and the mesh construction for the simulation.

M. Han et al. / Microelectronics Journal 35 (2004) 973–983 975

etching the cap layers in a succinic acid/H2O2/H2O (1:5:10)

solution. The 0.1 mm G-shaped gate was patterned by lift-off

with PMMA/P(MMA–MAA)/PMMA (100/600/200 nm)

using an 30-keV electron-beam lithography system. The

Schottky contact was formed by using Ti/Au (50/400 nm)

evaporation. Prior to the air-bridge interconnection, 78-nm

Si3N4 passivation layers were deposited in a plasma-

enhanced chemical-vapor deposition (PECVD) system.

The fabricated 70 mm!2 MHEMTs were characterized

by measuring the DC and RF performances. The DC

characteristics, such as I–V and transfer characteristics,

were measured in an HP4156A DC parameter analyzer, and

the measurement results for the MHEMTs of a 2 mm source-

drain spacing are compared with the simulation results in

Fig. 3. The typical saturation drain-source current (Idss)

and pinch-off voltage (Vp) are 60 mA (429 mA/mm) and

K1.7 V, respectively, as shown in Fig. 3(a). The breakdown

voltage (Vbr) of the device at a source-drain spacing of 2 mm

is w3 V. The measured maximum extrinsic transconduc-

tance (gm,max) is w390 mS/mm at a drain voltage (Vd) of

1.0 V and a gate voltage (Vg) of K0.8 V, as shown in

Fig. 3(b).

The RF measurements were performed in the frequency

range of 0.5–50 GHz by using an HP 8510C network

analyzer. As was shown in Fig. 3(c), a high S21 gain

(w7.92 dB) was obtained at a millimeter-wave frequency of

50 GHz. Shown in Fig. 3(d) are the measured h21 gain, S21

gain, and MSG versus the frequency obtained from the

MHEMTs. The devices exhibit an fT of w123 GHz and a

maximum frequency of oscillation (fmax) of w433 GHz,

respectively, from the extrapolation of h21 and MSG for a

device biased at the peak transconductance. The measured

fmax of w433 GHz is comparable to the best data thus far

reported for 0.1 mm MHEMTs [11,12].

To perform the simulation for the indium-mole-depen-

dent DC and millimeter-wave characteristics, we calibrated

the hydrodynamic transport model [16] by using the

fabricated devices, and the important parameters and

the physical considerations are described in detail at the

followings and are also summarized in Tables 1–3.

The work function (F) for the Schottky barriers Ti/Au

(50/400 nm) gate metals was set to 4.33 eV. For this, all the

F values between 4.33 (F of Ti) and 5.1 eV (F of Au) were

examined; however, a F of 4.33 eV gave the best calibration

results. In addition, the barrier lowering effect for the

Schottky gate was considered by inserting a hypothetical

thin (2 A) oxide layer just below the gate. We ignored the

leakage current across the gate electrodes due to the

tunneling of electrons and/or holes through the Schottky

barrier because this current is extremely small and not


a major factor affecting the current level significantly in our

simulations. However, for the breakdown condition at a

higher drain bias, the gate leakage current has to be

reconsidered because the hot-spot region between the gate

and the drain is affected by this current flow.

For the energy band model, the built-in parameters of the

simulator were used for each epitaxial material. Each

electrode (gate, source and drain) was connected to the

extrinsic resistors in order to take into account the contact

resistances between the pad metals and the electrode

terminals. These extrinsic resistances were determined

from the S-parameter measurements using a small-signal

Fig. 3. Simulation and measurement results for the DC and the RF characteristic

frequency (VdsZ1.5 V, VgsZK0.7 V). (d) fT and fmax versus the frequency (VdsZ

model [18]. The determined extrinsic resistances to the

source, the drain, and the gate were 2.57, 6.59, and 1.82 U,

respectively. To convert the sheet densities for each d-

doping layer to the volume concentrations, a thickness of

20 A for each d-doping layer was assumed. From this, a

sheet density of 4.5!1012 cmK2 for the upper d-doping was

converted to 2.25!1019 cmK3, for example.

In the hydrodynamic model, the effect of electron

temperature was taken into account, while the effects of

hole and lattice temperatures were not. This is because the

contribution of hole temperature to the thermal effect is very

small due to the negligible hole carrier density compared to

s. (a) Ids versus Vds. (b) Ids and gm versus Vgs. (c) S-parameters versus the

1.5 V, VgsZK0.7 V). (e) fT and fmax versus Vgs (VdsZ1.5 V).

Fig. 3 (continued)


the huge electron density in the channel layer, and the effect

of lattice temperature was already considered in the electron

carrier temperature to achieve a faster simulation [16].

Moreover, the impact ionization for the breakdown

was not considered in the model because the impact

ionization does not significantly affect the DC character-

istics in a drain voltage range of 0–2.5 V. For the generation

and recombination for the carriers, we used Shockley–

Read–Hall, Radiative (direct), and Auger recombination

models.

To determine the carrier motilities in each epitaxial layer,

a constant mobility model, a doping-dependent mobility

degradation model, and a mobility degradation model were

used. For the mobility degradation model, we considered the

degradation mechanisms at the interfaces due to acoustic

phonon scattering and the scattering caused by surface

Table 1

Constant mobilities, saturation velocities, and b exponents for In0.53Ga0.47-

As and In0.52Al0.48As materials used in hydrodynamic Canali model

Parameters Materials

In0.53Ga0.47As In0.52Al0.48As

Electrons Holes Electrons Holes

mlow Low-field

mobility

(cm2/V s)

9710 331 4226 75

nsat Saturation

velocity (cm/s)

2.0!107 8.0!106 1.0!107 3.0!106

b Exponent (l) 1.3 1.3 1.5 1.5

tc Energy relax-

ation time (ps)

1.0 0.4 1.0 0.4

Table 2

Parameters for the doping-dependent mobility degradation model of

Masetti

Parameters Materials

In0.53Ga0.47As In0.52Al0.48As

Electrons Holes Electrons Holes

mconst (cm2/V s) 9710 331 4226 75

mmin1 (cm2/V s) 3372 75 220 40

mmin2 (cm2/V s) 3372 75 220 40

m1 (cm2/V s) 0 0 0 0

Pc (cm3) 6.0!1015 0 0 0

Cr (cm3) 8.9!1016 1.0!1017 1.5!1014 3.8!1017

Cs (cm3) 3.34!1020 6.1!1020 3.34!1020 6.1!1020

a (l) 0.76 1.37 0.27 0.79

b (l) 2.0 2.0 2.0 2.0


roughness. The hydrodynamic Canali model [16] is used to

take into account a constant low-field mobility and a

high-field saturation in the constant low-field mobility. The

carrier mobility of the hydrodynamic Canali model is

given by

m Zmlowffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1 Ca2ðwc Kw0Þb

pCaðwc Kw0Þ

b=2h i2=b

; (1)

where mlow is the constant low-field mobility, wc Z3kBTc=2

is the average carrier thermal energy, and wc Z3kBTL=2

gives the equilibrium thermal energy. The parameter a is

Table 3

Simulation results for the Ids–Vds at various gate lengths and source-drain spacin

Gate length (mm) Source-drain spa

2 mm

Idss (mA) 0.1 58

0.05 56

Vp (V) 0.1 K1.5

0.05 K1.75

gm (mS/mm) 0.1 370 (VgsZK0.5

0.05 295 (VgsZK0.8

fT (GHz) 0.1 114

0.05 136

given by

a Z1

2

mlow

qtcv2sat

� �b=2

; (2)

where tc is the energy relaxation time of carriers, and the

index c can be either e for the electron or h for the hole. The

saturation velocity nsat and the exponent b were determined

in the same way as for the standard Canali model. For

average carrier energies, wc (less than the thermal energy

w0), the mobility is set to the low-field value, mZmlow.

Table 1 shows a summary of the important calibrated

mobility parameters for the InxGa1KxAs and the In0.52

Al0.48As materials for the hydrodynamic Canali model used

in the simulations.

For the ohmic contacts, such as the source and the drain,

we appended into the model the effect of dopant diffusion

(Si in the cap layer and Ge in the ohmic metals) during

the thermal evaporation and alloy processes to form the

AuGe/Ni/Au layers. This was done by assuming that the

dopants follow a Gaussian distribution. For example, the Ge

doping distributions in the ohmic contacts under the source

and the drain electrodes show a peak concentration of 2.5!1018 cmK3 and a junction concentration of 1!1016 cmK3 at

a depth of 0.15 mm. A constant doping concentration of

6.0!1018 cmK3 in the cap layer was added to the Ge

distributions to consider the thermal diffusion out of the cap

layer. This correction was achieved by using a lateral decay

factor of 0.005 for the constant doping distribution.

Scattering phenomena of the carriers with charged impurity

ions can lead to the degradation of the carrier mobility in the

doped regions. For this, the Masetti model [16] was also

adopted to simulate the doping-dependent mobility degra-

dation in the epitaxial layers under the source and the drain

contacts. The Masetti model gives the carrier mobility as

follows:

mdop Z mmin1exp KPc

Ni

� �C

mconst Kmmin2

1 C Ni

Cr

� �a

Km1

1 C Cs

Ni

� �b; (3)

gs

cing

2.5 mm 3 mm

50 46

52 48

K1.5 K1.5

K1.75 K1.75

) 330 (VgsZK0.5) 300 (VgsZK0.5)

) 255 (VgsZK0.8) 240 (VgsZK0.8)

114 110

130 128.5


where NiZND CNA denotes the total concentration of

ionized impurities. The low-doping reference mobility

mconst is set to the constant low-field mobility of mlow.

mmin1, mmin2, and m1 are the reference mobilities. Pc, Cr, and

Cs are the reference doping concentrations, while a and b

are the exponents. Table 2 shows the calibrated parameters

for the InxGa1KxAs and the In0.52Al0.48As materials in the

Masetti model.

At both interfaces of the passivation/In0.52Al0.48As and

of the gate contact/In0.52Al0.48As, the carriers are subjected

to the scatterings due to acoustic surface phonons and the

surface roughness because the high transverse electric-field

forces carriers to interact strongly with the semiconductor–

insulator interface. This mobility degradation at the

semiconductor–insulator interface, like the channel region

of a metal oxide semiconductor field effect transistor, is well

described by the Lombardi model [16], where the transverse

field computation normal to the interface is based on the

Enormal methods [16]. The related parameters used in the

simulations are all built-in parameters for the InxGa1KxAs

and the In0.52Al0.48As materials. Moreover, at these

interfaces, the trap centers can exist because the Si3N4

passivation layer deposited on the semiconductors gives rise

to a variety of crystalline defects at the interfaces. To

accommodate the trap effect at the interface of passivations,

we used a one-level acceptor-type trap in the middle of the

energy band gap for the In0.52Al0.48As barrier layer. The

electron and the hole capture cross-sections were set to a

value of 1.0!10K15 cmK2. Through the rigorous calibra-

tions, it was estimated that the interface trap density is

w6.3!1011 cmK2 for the passivation of our fabricated

devices.

3. Results and discussion

Fig. 3(a) shows the comparison of the measurement

results with the simulation data for the Ids–Vds character-

istics. As shown in the plots, the measured and calculated

Idss at a Vgs of 0 V are 429 and 428 mA/mm at the same Vds

of 2.5 V, respectively. The comparison for the gm at a Vds of

1.0 V is also shown in Fig. 3(b). The measured and

calculated gm,max are 390 and 344.7 mS/mm, respectively.

There is some amount of discrepancy in gm,max, therefore

overall simulation data for the millimeter-wave character-

istics are slightly different from the measurements.

However, in the case of DC characteristics, there is an

excellent agreement with the measurement results.

Shown in Fig. 3(c) and (d) is the comparative results of

the millimeter-wave characteristics including S21, h21,

MSG, fT, and fmax. As shown in Fig. 3(c), the S21 gain at

50 GHz obtained from the simulation is w5.99 dB while the

measurement result is w7.92 dB, and the difference of

w1.9 dB is maintained over the whole frequency range.

Other S-parameters and the h21 gains also exhibit a similar

difference of w2 dB. These differences in millimeter-wave

characteristics are not that great, thus it is believed that

the model describes quite closely the device characteristics.

The fT was extracted from the extrapolation of h21

curve. The measured and calculated fT at a bias condition

of VdsZ1.5 V and VgsZK0.7 V are 123 and 113.7 GHz,

respectively, as shown in Fig. 3(e). The fmax was extracted

from the extrapolated curve of Mason’s unilateral gains

(MUG) by the definition of jMUGjZ1 in all simulations.

The calculated and measured fmax were 433 and 207.5 GHz

as extracted at 50 GHz. The difference in fmax is quite great;

however, it is supposed that this difference arises from the

different extraction methods because the calculated result

was extracted from the MUG curve while the measurement

was from the MSG curve.

The scaling effects (gate length and source-drain

spacing) on the MHEMTs were characterized by using the

calibrated model. The same parameter sets were maintained

in the calculation. As the source-drain spacing is decreased,

the Idss is increased, as shown in Fig. 4. The Idss, hereafter, is

defined as a maximum drain saturation current density

measured at a Vg of 0 V. Extrinsic transconductance (gm) is

therefore increased with the decrease of source-drain

spacing. However, one interesting result is that the gm is

decreased with the decrease of gate length, as shown in

Fig. 5. From the classical theory of the device physics, the

gm is to be increased with the reduction of gate length.

However, this model suggests that the opposite result can be

observed in modern nano-scaled HEMT devices, as reported

in other earlier works [19].

In the case of millimeter-wave characteristic, the fT is

increased with the decrease of gate length despite the

corresponding decrease of gm. This result can be explained

by the increase of gate-source capacitance (Cgs) and gate-

drain capacitance (Cgd), as shown in Eq. (4).

fTfgm

ðCgd CCgsÞ(4)

To validate our hypothesis, we calculated both Cgs and Cgd,

and Table 4 shows the results. At the same source-drain

spacing condition, Cgs and Cgd are both decreased with the

decrease of gate length. From a simple calculation using Eq.

(4), it can be shown that increased ratio of fT has a good

agreement with the differential ratio of the gm and the total

capacitance of CgsCCgd.

Vertical scaling effect (barrier and channel thicknesses)

is also examined by varying the barrier layer thickness (15

and 10 nm) and the channel layer thickness (23, 20, 15 and

12 nm). As shown in Table 3, both gm and fT depend on the

source-drain spacing and the gate length. For this reason, the

simulation was performed at a fixed source-drain spacing of

2 mm and a gate length of 0.1 mm by varying the barrier

layer thickness. Table 5 shows that a significant enhance-

ment in gm is obtained with the reduction of the barrier

thickness, and however, that its negligible effect on the

millimeter-wave characteristics is observed. To optimize

Fig. 4. Simulation results for the Ids–Vds at various gate lengths and source-drain spacings. (a) Gate lengthZ0.1 mm, source-drain spacingZ2 mm. (b) Gate

lengthZ0.05 mm, source-drain spacingZ2 mm. (c) Gate lengthZ0.1 mm, source-drain spacingZ2.5 mm. (d) Gate lengthZ0.05 mm, source-drain spacingZ2.5 mm. (e) Gate lengthZ0.1 mm, source-drain spacingZ3 mm. (f) Gate lengthZ0.05 mm, source-drain spacingZ3 mm.


Fig. 5. Simulation results for the transconductance at various gate lengths

and source-drain spacings. (a) Gate lengthZ0.1 mm, source-drain spa-

cingZ2–3 mm. (b) Gate lengthZ0.05 mm, source-drain spacingZ2–3 mm.

Table 4

Simulation results for the Cgd and Cgs at various gate lengths and source-

drain spacings

Gate length

0.05 mm

Gate length

0.1 mm

Source-drain 2 mm Cgd 26.63 fF 38.27 fF

Cgs 19.54 fF 28.24 fF

Source-drain 2.5 mm Cgd 27.1 fF 38.74 fF

Cgs 15.95 fF 20 fF

Source-drain 3 mm Cgd 26.82 fF 40.37 fF

Cgs 13.5 fF 16.42 fF

Table 5

Summary of the electrical characteristics at various barrier layer

thicknesses (gate lengthZ0.1 mm, source-drain spacingZ2 mm)

Barrier thickness

15 nm 10 nm

Idss (mA) Measurement 59.65 No data

Simulation 59.78 58

Vp (V) Measurement K1.7 No data

Simulation K1.5 K1.5

gm (mS/mm) Measurement 390

(VgsZK0.8,

VdsZ1)

No data

Simulation 344.67

(VgsZK0.71,

VdsZ1)

370 (VgsZK0.50,

VdsZ1)

S21 (at 50 l)

(dB)

Measurement 7.92

(VgsZK0.7 V,

VdsZ1.5 V)

No data

Simulation 5.99

(VgsZK0.7 V,

VdsZ1.5 V)

No data

fT (GHz) Measurement 123

(VgsZK0.7 V,

VdsZ1.5 V)

No data

Simulation 113.7

(VgsZK0.7 V,

VdsZ1.5 V)

114

(VgsZK0.7 V,

VdsZ1.5 V)


the devices performance, a variety of channel thicknesses,

such as 23, 20, and 15 nm were taken into account for the

simulation at a source-drain spacing of 2 mm, a gate length

of 50 nm, and a barrier layer thickness of 10 nm. As shown

in the simulation results of Figs. 6 and 7, the DC and the RF

performances are all enhanced with the decrease of channel

layer thickness (Table 6).

Fig. 6. Simulation results for the gm at various channel thicknesses (source-

drain spacingZ2 mm, gate lengthZ0.05 mm, barrier thicknessZ10 nm).

Fig. 7. Simulation results for the fT and fmax at various channel thicknesses

(source-drain spacingZ2 mm, gate lengthZ0.05 mm, barrier thicknessZ10 nm). (a) fT versus the channel thickness. (b) fmax versus the channel

thickness.

Table 6

Summary of the electrical characteristics at various channel layer

thicknesses (gate lengthZ0.05 mm, source-drain spacingZ2 mm)

Thickness of

channel layer

(nm)

Gate length (50 nm)/barrier thickness

(10 nm), source-drain spacing (2 mm)

Idss (mA) 23 56.3 (at VdsZ2.5 V)

20 55.7 (at VdsZ2.5 V)

15 54.5 (at VdsZ2.5 V)

12 53.5 (at VdsZ2.5 V)

VT (V) 23 K1.353

20 K1.273

15 K1.128

12 K1.137

gm,max

(mS/mm)

23 295.15 (at VgsZK0.65, VdsZ1.0 V)

20 316.66 (at VgsZK0.62, VdsZ1.0 V)

15 354.60 (at VgsZK0.77, VdsZ1.0 V)

12 358.91 (at VgsZK0.78, VdsZ1.0 V)

fT,max

(GHz)

23 137.44 (at VgsZK0.93, VdsZ1.5 V)

20 143.42 (at VgsZK0.88, VdsZ1.5 V)

15 152.28 (at VgsZK0.80, VdsZ1.5 V)

12 155.18 (at VgsZK0.80, VdsZ1.5 V)

fmax,max

(GHz)

23 218.13 (at VgsZK1.00, VdsZ1.5 V)

20 225.55 (at VgsZK0.99, VdsZ1.5 V)

15 233.20 (at VgsZK0.87, VdsZ1.5 V)

12 239.36 (at VgsZK0.90, VdsZ1.5 V)


4. Summary

A model for the sub-0.1-mm offset G-gate In0.53Ga0.47

As/In0.52Al0.48As MHEMTs is reported with a reasonable

agreement with the electrical characteristics measured from

the fabricated 0.1 mm devices. To take into account the

sophisticated carrier transport physics in sub-0.1-mm

devices, all the parameters were calibrated using the

measurement data with various physical considerations for

the model to obtain accurate device performances.

We examined the effects of device scaling in both lateral

and vertical directions on the MHEMTs. From the

simulations, the MHEMTs gave the best electrical perform-

ances at a condition of 0.1 mm source-drain spacing, 50 nm

gate length, 10 nm barrier layer thickness, and 23 nm

channel layer thickness.

Acknowledgments

This work was supported by Korea Science and

Engineering Foundation (KOSEF) under the Engineering

Research Center (ERC) program through the Millimeter-

Wave Innovation Technology Research Center at Dongguk

University.

References

[1] L.D. Nguyen, A.S. Brown, M.A. Thompson, L.M. Jelloian, IEEE

Trans. Electron. Dev. 39 (1992) 2007.

[2] M. Wojtowicz, R. Lai, D.C. Streit, G.I. Ng, T.R. Block, K.L. Tan,

P.H. Liu, A.K. Freudenthal, R.M. Dia, IEEE Electron. Dev. Lett. 15

(1994) 477.

[3] A. Endoh, Y. Yamashita, M. Higashiwaki, K. Hikosaka, M. Mimura,

S. Hiyamizu, T. Maysui, Proceedings of 12th International Con-

ference on InP and Related Materials, Williamsburg, USA, 2000,

p. 87.

[4] P.M. Smith, S.M.J. Riu, M.Y. Kao, P. Ho, S.C. Wang, K.H.G. Duh,

S.T. Fu, P.C. Chao, IEEE Microwave Guided Wave Lett. 5 (1995)

230.

[5] J.Y. Shim, H.S. Yoon, S.J. Kim, J.Y. Hong, W.J. Chang, D.M. Kang,

J.H. Lee, K.H. Lee, J. Korean Phys. Soc. 38 (2002) 528.

[6] H.S. Yoon, J.H. Lee, J.Y. Shim, D.M. Kang, J.Y. Hong, W.J. Chang,

K.H. Lee, J. Korean Phys. Soc. 42 (2003) 434.

[7] J.H. Lee, J.Y. Shim, H.S. Yoon, H.C. Kim, J. Korean Phys. Soc. 42

(2003) 662.

[8] D.H. Kim, S.Y. Oh, J.J. Kim, J.H. Lee, K.W. Chung, K.S. Seo,

J. Korean Phys. Soc. 41 (2002) 1036.

[9] A. Cappy, Y. Cordier, S. Bollaert, M. Zaknoune, Proceedings of GaAs

IC Symposium, Monterey, California, USA, 1999, p. 217.


[10] M. Chertouk, H. Heiss, D. Xu, S. Kraus, W. Klein, G. Bohm,

G. Trankle, G. Weimann, IEEE Electron. Dev. Lett. 17 (1996) 273.

[11] M. Zaknoune, Y. Cordier, S. Bollaert, Y. Druelle, D. Theron, Y.

Crosnier, Device Research Conference Digest, Charlottesville, 1998,

p. 34.

[12] D.C. Dumka, W.E. Hoke, P.J. Lemonias, G. Cueva, I.

Adesida, International Electron Device Meeting, Washington,

1999, p. 783.

[13] C.S. Whelan, W.E. Hoke, R.A. McTaggart, P.S. Lyman, P.F. Marsh,

R.E. Leoni III, S.J. Lichwala, T.E. Kazior, IEEE Microwave Theory

and Techniques Society, Digest, Anaheim, California, USA, 1999,

p. 1187.

[14] C. Gassler, V. Ziegler, C. Wolk, R. Deufel, F.-J. Berlec, IEEE

International Electron Device Meeting, San Francisco, California,

USA, 2000, p. 11.

[15] H.S. Yoon, J.H. Lee, J.Y. Shim, S.J. Kim, D.M. Kang, J.Y. Hong, W.J.

Chang, K.H. Lee, Proceedings of 14th International Conference on

InP and Related Materials, Stockholm, Sweden, 2002, p. 201.

[16] ISE-DESSIS manual, Ver. 7.5.

[17] T. Suemitsu, T. Enoki, H. Yokoyama, Y. Ishii, Jpn. J. Appl. Phys. 37

(1998) 1365.

[18] D.-S. Park. Master Thesis. Dongguk University, 2001.

[19] K. Kalna, S. Roy, A. Asenov, K. Elgaid, I. Thayne, Scaling of

PHEMT to decanano dimensions, Solid State Electron. 46 (2002) 631.

optimization of sub-0.1-μm offset Γ-shaped gate mhemts for millimeter-wave applications

Documents