wideband millimeter-wave integrated circuits...
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WIDEBAND MILLIMETER-WAVE INTEGRATED CIRCUITS AND SYSTEMS FOR HIGH SPEED POINT-TO-POINT LINK AND AUTOMOTIVE RADAR APPLICATIONS
By
AUSTIN YING-KUANG CHEN
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARITAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2010
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© 2010 Austin Ying-Kuang Chen
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To my parents
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ACKNOWLEDGMENTS
I would first like to express my deepest gratitude to my parents for their
unconditional support and caring (when I needed it the most), especially my dad who
has always believed in me and never doubted my abilities to excel and achieve, and my
mom, who has taken good care of me since I was young. My greatest respect for them
cannot be overemphasized.
I am profoundly grateful to my academic advisor at the University of Florida,
Dr. Jenshan Lin for his continuous guidance and support. His encouragement and
advice throughout my Ph.D. career have been extremely motivating and indispensable.
His professional knowledge in the field of research has been invaluable. I would also
like to thank my Ph.D. committee members Dr. William Eisenstadt, Dr. John Harris, Dr.
Loc Vu-Quoc, and Dr. Fan Ren for their helpful comments and insightful opinions. In
addition, I would like to thank Dr. Robert Fox and Dr. Kenneth O for helpful and
stimulating discussions.
I am also thankful to Dr. Young-Kai Chen, the director of the High Speed
Electronics Design Group, Bell Laboratories, Alcatel-Lucent for providing me with the
opportunity to work with other top-notch talents in the Lab and the resources to perform
my Ph.D. research. I am deeply grateful to Dr. Yves Baeyens who was my professor at
Columbia University and industrial advisor. Dr. Baeyens is also the technical manager
of the High Speed Electronics Design Group during my time at Bell Labs. His
remarkable knowledge in microwave/millimeter-wave circuits and high speed optical
communication design has certainly helped in paving the way for my research direction.
My heartfelt thanks also go to my colleagues at Bell Labs: Dr. Joe Weiner for teaching
me how to do layout design when I first started; Dr. Kun-Yii Tu for his continuous
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support and encouragement; Dr. Jaesik Lee for his generous design insights on high
speed analog-to-digital converters (ADCs); Pascal Roux for enlightening me in
microwave power amplifier designs; Marta Rambaud for her great patience and
measurement support; Dr. Noriaki Kaneda for useful suggestions; Dr. Nils Weimann, Dr.
Vincent Houtsma, and Dr. Rose Kopf for chip fabrication; and Dr. Ting-Chen Hu for his
helpful suggestions. Dr. Hu has also been a great friend who played basketball with me
after works (Of course, he needs more exercise and practice). I am also indebted to the
exchange scholars from the Republic of Taiwan, Dr. Hsiao-Bin Barry Liang, Fan-Ren
Liao, and Hsien-Ku Chen for sharing some design insights; intern from Columbia
University Shih-An Yu for useful discussions on phase-locked loop (PLL); UCLA interns
Jim Sun and Michael Wu for helpful discussions on antenna and metamaterial; and
intern from Korea University, Hokyu Lee for sharing his knowledge in ADC and op-amp
designs. They have all made my life at work much more enjoyable.
I want to acknowledge the help that I received from many professors during my
memorable time at Columbia University, Dr. Wen-I Wang, Dr. Peter Kinget, Dr. Yannis
Tsividis, Dr. Paul Diament, and Dr. Irving Kalet.
My appreciation also goes to the former and current Radio Frequency Circuits and
Systems (RFCSR) Research group members: Dr. Tien-Yu Chang, Dr. Lance Covert, Dr.
Zhenning Low, Dr. Changzhi Li, Zivin Park, Mingqi Chen, Xiaogang Yu, Yan Yan, and
Te-Yu Kao. I would also like to thank Chun-Ming Tang for his help with my work during
my time at UF as well as for being a competitive basketball player.
Last but not least, I would especially like to thank my parents and my elder brother
once again for their spiritual and financial support, and for always being with me during
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the ups and downs. Without their encouragement, this dissertation would not even have
been started.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS.................................................................................................. 4
LIST OF TABLES.......................................................................................................... 10
LIST OF FIGURES........................................................................................................ 11
ABSTRACT ................................................................................................................... 15
CHAPTER
1 INTRODUCTION .................................................................................................... 17
1.1 Motivation ......................................................................................................... 17 1.2 Objective and Scope of Research .................................................................... 20 1.3 Publications ...................................................................................................... 20 1.4 Outline of Dissertation....................................................................................... 21
2 MILLIMETER-WAVE ACTIVE AND PASSIVE DEVICES ....................................... 23
2.1 Introduction ....................................................................................................... 23 2.2 Front-End Technology ...................................................................................... 24
2.2.1 Device Figures of Merit (FoMs) ............................................................... 24 2.2.2 Heterojunction Bipolar Transistor (HBT) Devices .................................... 29 2.2.3 JAZZ 0.18 μm SiGe BiCMOS Technology............................................... 31
2.3 Back-End-of-Line (BEOL) Technology.............................................................. 34 2.4 Design and Modeling of Transmission Lines .................................................... 35
3 LOW-NOISE AMPLIFIERS (LNAs)......................................................................... 40
3.1 Introduction ....................................................................................................... 40 3.2 62 GHz Broadband Feedback Cascode LNA ................................................... 41
3.2.1 Circuit Topology ...................................................................................... 41 3.2.2 Stability Analysis ..................................................................................... 43 3.2.3 Synthesis of Matching Networks ............................................................. 45 3.2.4 Experimental Results............................................................................... 46
3.3 77 GHz Low-Power Linear LNA........................................................................ 50 3.3.1 Amplifier Circuit Design ........................................................................... 50 3.3.2 Experimental Results............................................................................... 53
3.4 87 GHz High Gain LNA..................................................................................... 57 3.4.1 Amplifier Circuit Design ........................................................................... 57 3.4.2 Experimental Results............................................................................... 58
3.5 Chapter Summary............................................................................................. 61
4 WIDEBAND MIXED LUMPED-DISTRIBUTED-ELEMENT POWER SPLITTERS .. 64
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4.1 Introduction ....................................................................................................... 64 4.2 Out-of-Phase Power Splitters Design ............................................................... 66
4.2.1 Mixed Lumped-Distributed Wilkinson Power Divider ............................... 66 4.2.2 П and Т Phase Shifters in 180o and 90o Power Splitters ......................... 67
4.3 Implementation and Experimental Results........................................................ 69 4.4 Chapter Summary............................................................................................. 76
5 HIGH GAIN DOUBLE-BALANCED ACTIVE FREQUENCY DOUBLER ................. 77
5.1 Introduction ....................................................................................................... 77 5.2 Highlights of Frequency Doubler Design Approaches....................................... 77 5.3 Active Frequency Doubler Design .................................................................... 79
5.3.1 Circuit Architecture .................................................................................. 79 5.3.2 Stability.................................................................................................... 81 5.3.3 Design for High Speed, Conversion Gain, and Output Power ................. 83 5.3.4 Layout Design ......................................................................................... 84
5.4 Experimental Results ........................................................................................ 84 5.5 Chapter Summary............................................................................................. 91
6 HIGHLY LINEAR DOUBLE-BALANCED ACTIVE UP-CONVERSION MIXERS..... 92
6.1 Introduction ....................................................................................................... 92 6.2 Up-Conversion Mixer Design ............................................................................ 93 6.3 Experimental Results ........................................................................................ 94 6.4 Chapter Summary............................................................................................. 97
7 INTEGRTATED WIDEBAND LINEAR RECEIVER ............................................... 100
7.1 Introduction ..................................................................................................... 100 7.2 Circuit Blocks Design ...................................................................................... 101
7.2.1 Low-Noise Amplifier............................................................................... 101 7.2.2 Down-Conversion Mixer and Integrated Passive Balun......................... 102 7.2.3 Internal LO Generation .......................................................................... 105
7.3 Implementation and Experimental Results...................................................... 105 7.4 Chapter Summary........................................................................................... 111
8 SUBMILLIMETER-WAVE HIGH-POWER HARMONIC SIGNAL GENERATION . 112
8.1 Introduction ..................................................................................................... 112 8.2 Submicron Indium Phosphide (InP) D-HBT Technology ................................. 113 8.3 Push-Push Oscillator Circuit Design ............................................................... 116
8.3.1 General Nth Harmonic Oscillators Analysis............................................ 116 8.3.2 160 GHz and 200 GHz Push-Push Oscillators Design .......................... 121
8.4 Experimental Results ...................................................................................... 125 8.5 Chapter Summary........................................................................................... 132
9 SUMMARY AND FUTURE WORKS..................................................................... 134
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9.1 Summary ........................................................................................................ 134 9.2 Future Works .................................................................................................. 135
9.2.1 Wideband Direct-Conversion Transmitter Front-End............................. 135 9.2.2 Other Opportunities in Bulk CMOS........................................................ 135
LIST OF REFERENCES ............................................................................................. 137
BIOGRAPHICAL SKETCH.......................................................................................... 146
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LIST OF TABLES
Table page 3-1 Performance comparisons of ≥60 GHz silicon-based single-ended low-noise
amplifiers ............................................................................................................ 50
3-2 Performance comparisons of ≥ 77 GHz silicon HBT-based single-ended low-noise amplifiers................................................................................................... 56
3-3 Performance of previously reported ≥85 GHz silicon HBT-based single-ended low-noise amplifiers ................................................................................. 62
4-1 Performance summary of the three power splitters ............................................ 76
5-1 Performance of prior published frequency doublers ........................................... 91
6-1 Performance of prior published silicon-based up-conversion mixers.................. 99
7-1 Performance of prior published SiGe HBT/BiCMOS 77 GHz down-covnversion mixers........................................................................................... 110
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LIST OF FIGURES
Figure page 1-1 Atmospheric attenuation versus frequency......................................................... 18
2-1 Simplified HBT model ......................................................................................... 26
2-2 Circuit diagram for maximum available gain extraction ...................................... 26
2-3 Circuit diagram for maximum stable gain extraction ........................................... 27
2-4 Circuit diagram for Mason’s unilateral power gain extraction ............................. 28
2-5 Top view of a simplified HBT device layout ........................................................ 32
2-6 Simulated transit frequency (fT), maximum oscillation frequency (fmax), and maximum power gain (Gmax) of the device.......................................................... 34
2-7 Cross sections of SiGe BiCMOS BEOL.............................................................. 36
2-8 Implementations of the coplanar waveguide and thin-film microstrip line ........... 37
2-9 Simulated loss of quarter-wavelength (λ/4) line plotted against characteristic impedance (Zo) ................................................................................................... 38
3-1 Circuit schematic of the two-stage 62 GHz low-noise amplifier .......................... 42
3-2 Stability analysis of a cascode amplifier ............................................................. 44
3-3 Chip microphotograph of the two-stage 62 GHz low-noise amplifier .................. 47
3-4 Measured power gain and noise figure of the 62 GHz LNA................................ 48
3-5 Measured input and output return losses of the 62 GHz LNA ............................ 48
3-6 Measured reverse isolation of the 62 GHz LNA.................................................. 49
3-7 Measured linearity characteristics of Pout and gain of the 62 GHz LNA .............. 49
3-8 Circuit schematic of the two-stage 77 GHz low-noise amplifier .......................... 52
3-9 Microphotograph of the two-stage 77 GHz low-noise amplifier .......................... 54
3-10 Simulated and measured power gain (S21) and noise figure of the 77 GHz LNA .................................................................................................................... 54
3-11 Simulated and measured input and output return losses of the 77 GHz LNA..... 55
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3-12 Measured linearity characteristics of Pout and gain of the 77 GHz LNA .............. 55
3-13 Circuit schematic of the 87 GHz low-noise amplifier........................................... 59
3-14 Chip microphotograph of the 87 GHz low-noise amplifier................................... 59
3-15 Simulated and measured power gains (S21) and noise figures of the 87 GHz LNA .................................................................................................................... 60
3-16 Simulated and measured input and output return losses of the 87 GHz LNA..... 60
3-17 Measured linearity characteristics of Pout and gain of the 87 GHz LNA .............. 62
4-1 Simplified block diagrams of single sideband (SSB) quadrature architecture. receiver and transmitter...................................................................................... 65
4-2 Block diagrams of Wilkinson power dividers....................................................... 66
4-3 Unit Cells for generating ±90° and ±45° phase shifts.......................................... 67
4-4 Mixed lumped-distributed-element out-of-phase power splitter .......................... 68
4-5 Chip microphotographs of the 180° power splitter and 90° power splitter. ......... 70
4-6 Measurement and simulation results of the 180° power splitter ......................... 72
4-7 Measurement and simulation results of the 90° power splitter ........................... 73
4-8 Simulation results of the compensated 90° powers splitter ................................ 75
5-1 Schematic of the double-balanced active frequency doubler ............................. 80
5-2 Sources of instability in emitter followers............................................................ 82
5-3 Microphotograph of the double-balanced active frequency doubler. .................. 85
5-4 On-wafer measurement setup for the active frequency doubler. ........................ 86
5-5 Measured conversion gain at input powers of -9 dBm and -8 dBm. ................... 86
5-6 Measured fundamental suppression................................................................... 88
5-7 Output spectrum of the active frequency doubler at 50 GHz output frequency (not corrected for the losses). ............................................................................. 88
6-1 Block diagram and circuit schematic of the double-balanced active up-conversion mixer ................................................................................................ 95
6-2 Microphotograph of the active up-conversion mixer ........................................... 96
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6-3 Measurement setup for active up-conversion mixer ........................................... 96
6-4 Measured SSB conversion gain and LO to RF isolation..................................... 98
6-5 Measured mixer linearity characteristics at 77 GHz and 80 GHz........................ 98
7-1 Simplified block diagram of the wideband receiver with on-chip active frequency doubler............................................................................................. 101
7-2 Circuit schematic of the 77 GHz two-stage LNA [26]........................................ 102
7-3 Circuit schematic of the standalone down-conversion mixer. ........................... 103
7-4 Microphotograph of the wideband receiver....................................................... 106
7-5 Measured receiver and down-conversion mixer conversion gain and noise figure (IF fixed at 100 MHz) .............................................................................. 106
7-6 Measured mixer conversion gain and SSB NF vs. LO input power .................. 108
7-7 Measured RF and LO port matching and port-to-port isolation of the mixer ..... 109
7-8 Measured linearity characteristics of IF output power and conversion gain of the mixer and receiver at RF = 77 GHz ............................................................ 109
8-1 Dry etched D-HBT before planarization [92]. .................................................... 114
8-2 Extrapolated fT and fmax of 0.5 x 4.0 μm2 emitter InP D-HBT measured as a function of collector current [93]........................................................................ 115
8-3 Current gain (|h21|2) and unilateral Mason’s gain (GU) plotted against
frequency [92]................................................................................................... 116
8-4 Block diagram of the push-push architecture with phase coupling network...... 117
8-5 Block diagram of the push-push architecture with fundamental differential oscillator ........................................................................................................... 117
8-6 Schematic of the push-push oscillator based on differential Colpitts topology . 122
8-7 Equivalent sub-oscillator circuits in differential mode and common mode........ 123
8-8 Inverted thin-film microstrip transmission line cross section ............................. 124
8-9 Layout view and microphotograph of the 200 GHz push-push oscillator .......... 125
8-10 Layout view and microphotograph of the 160 GHz push-push oscillator .......... 126
8-11 Push-push oscillator measurement setup......................................................... 126
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8-12 Measured second harmonic frequency and output power as a function of negative supply VEE for 200 GHz push-push oscillator ..................................... 127
8-13 Measured second harmonic frequency and output power as a function of negative supply VB for 200 GHz push-push oscillator (VEE fixed at 3.2 V) ........ 127
8-14 Downconverted spectrum of 200 GHz push-push oscillator. (Not yet corrected for the losses) ................................................................................... 129
8-15 Detailed downconverted spectrum of 200 GHz push-push oscillator. (Not yet corrected for the losses) ................................................................................... 129
8-16 Measured second harmonic frequency and output power as a function of negative supply VEE for 160 GHz push-push oscillator ..................................... 130
8-17 Measured second harmonic frequency and output power as a function of negative supply VB for 160 GHz push-push oscillator (VEE fixed at 3.0 V) ........ 130
8-18 Downconverted spectrum of 160 GHz push-push oscillator. (Not yet corrected for the losses) ................................................................................... 131
8-19 Detailed downconverted spectrum of 160 GHz push-push oscillator. (Not yet corrected for the losses) ................................................................................... 131
9-1 Block diagram of the wideband direct-conversion transmitter front-end ........... 135
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
WIDEBAND MILLIMETER-WAVE INTEGRATED CIRCUITS AND SYSTEMS FOR
HIGH SPEED POINT-TO-POINT LINK AND AUTOMOTIVE RADAR APPLICATIONS
By
Austin Ying-Kuang Chen
May 2010
Chair: Jenshan Lin Major: Electrical and Computer Engineering
Until recently, low-cost millimeter-wave (mm-wave) integrated radio systems are
emerging thanks to the rapid evolution of advanced SiGe and CMOS technologies. In
particular, low-cost SiGe BiCMOS technology has been identified as a technology well-
suited for both active and passive imaging applications, such as high-resolution
automotive radars and concealed weapon detections due to its excellent high frequency
performance, high yield, and high level of integration. To further maintain the low
production cost advantage, efficient technology sharing suggests the key components
should be universal. Therefore it is worthwhile to integrate multiple standards that
include lower E-band 71–76 GHz and higher E-band 81–86 GHz multi-Gbps high speed
point-to-point links, 76–77 GHz long-range and 77–81 GHz short-range automotive
radars into a single chip. This Ph.D. dissertation demonstrates wideband active and
passive components and systems to be utilized for such a universal transceiver.
By investigating the circuit architectures and using combined analog and
microwave design techniques, these individual circuit blocks, such as low-power linear
77 GHz low-noise amplifier (LNA), down-conversion mixer, passive balun, tunable
quadrature power splitter (QPS), and 100 GHz regenerative frequency divider (RFD),
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and 80 GHz active frequency doubler are independently characterized and optimized for
gain, wideband, noise figure (NF) and linearity performance. A 68–82 GHz highly
integrated, wideband linear receiver is demonstrated. The receiver achieves a
maximum gain of 28.1 dB, a NF of 8 dB, and an input-referred 1 dB gain compression
point (IP1dB) of -23.6 dBm at 77 GHz while dissipating 413 mW. The receiver enables
applications within the band to share and reuse the same front-end chip. To further
explore the opportunity at higher frequency, an 81–92.6 GHz low-noise amplifier is
demonstrated with a gain of 21 dB, a NF of 9 dB, and an IP1dB of -18.8 dBm.
On the other hand, critical transmitter building blocks, such as an up-conversion
mixer has also been investigated. A highly linear double-balanced active up-conversion
mixer based upon multi-tanh triplet technique has been validated to show a single
sideband (SSB) power conversion gain of 5.1 dB and an output-referred 1 dB gain
compression point (OP1dB) of -5.8 dBm at 77 GHz.
Finally, a high-power signal generation at submillimeter-wave is demonstrated and
fabricated in InGaAs/InP D-HBT technology. The second harmonic push-push oscillator
shows an output power of 0 dBm at 200 GHz, which opens a new frontier for
applications, such as weather observation radar, chemical, and tumor detections, and
next-generation optical systems. By using an even higher order harmonic generation,
THz signal sources can be expected in the very near future.
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CHAPTER 1 INTRODUCTION
1.1 Motivation
Recently, the IEEE 802.16 Working Group has been developing standards for
Wireless Metropolitan Area Networks (WMAN) in the 10–66 GHz frequency range [1].
Much of its development has been dedicated to encompassing the 60 GHz millimeter-
wave (mm-wave) band for multi-gigabit short-range personal area networks (PANs) and
wireless high-definition multimedia interfaces (wHDMIs). According to Shannon’s
theorem, the maximum capacity that can provide the highest possible data rate for
reliable transmission in bits per second can be expressed by (1.1):
)1(log2 SNRBWC Channel (1-1)
This fact intuitively suggests that, for a given signal-to-noise ratio (SNR), the most
straightforward way to enhance a high data rate with even a modest modulation is by
increasing the channel bandwidth (BWchannel).
With the availability of a 7 GHz bandwidth from the 59–66 GHz unlicensed band in
Europe and Japan, and 57–64 GHz in the United States, congestion issues at
frequency below 10 GHz are ameliorated. The 60 GHz band offers several unique
advantages that include: 1) large contiguous bandwidth for high data rate; 2) small
wavelength for realizing integrated antennas; 3) excellent frequency reuse (less co-
channel interference) for more secure wireless communication. With the advent of high
fT and fmax silicon-based technology processes and their high integration capability, high
yield, and low cost, these have aroused strong research interests in and demand for
silicon millimeter-wave integrated circuits and systems.
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Besides the evolution of the short-range 60 GHz standard, the FCC has also
approved the licensed E-band which spans 71–76 GHz, 81–86 GHz, and 92–93 GHz.
The promising applications in-band include fiber replacement or extension, point-to-
point wireless local area networks, and broadband internet access with a data rate of
more than 10 Gbps utilizing more spectrally efficient modulation schemes [2]. The
transmission range at 70 GHz and 80 GHz can be many miles compared with the 60
GHz counterpart. Figure 1-1 shows atmospheric attenuation versus frequency. A large
peak at 60 GHz caused by oxygen molecules (15 dB/km) has adversely increased the
atmospheric attenuation. However, a large window can be seen in which the attenuation
has dropped back to 0.5 dB/km and is therefore deemed suitable for wireless
communication.
Figure 1-1. Atmospheric attenuation versus frequency.
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On the other hand, significant research and development efforts have been
dedicated to high resolution millimeter-wave active and/or passive imaging for military,
biomedical, and automotive applications such as concealed weapon and tumor
detections, and collision avoidance radar sensor. Of particular interest, high
performance long- (76–77 GHz) and short- (77–81 GHz) range automotive radars have
shown steady progress toward commercial success in today’s much advanced silicon-
based technologies. In automotive radar applications, the sensors must be able to
function in various adverse weather and low-visibility conditions and still accurately
detect and position different targets. Therefore, stringent demands on high linearity and
dynamic range are required to meet the specifications. Depending on the channel
bandwidth, the high dynamic range requirement in narrowband systems can sometimes
be relaxed if the distortions and interferers fall out of band. However, for wideband
systems such as high speed point-to-point wireless link (71–76 GHz) and short range
automotive radar (77–81 GHz), special design techniques to boost the input-referred
third order intercept point (IIP3) are often required to fulfill the link budget and dynamic
range [3].
Silicon Germanium (SiGe) technology has been identified as a suitable
semiconductor technology with the capability to fulfill the high frequency demands and
the cost aspects, especially with its potential for large scale integration when compared
with the exotic III-V compound semiconductors such as Indium Phosphide (InP) and
Gallium Arsenide (GaAs) [4]. To reduce the production cost and time-to-market, the
design of the key components should be universal. Efficient technology sharing
between E-band high speed data communication and automotive radars [5] is one way
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to tackle this problem but that requires the front-end circuits to operate within the
allocated wide bandwidth.
1.2 Objective and Scope of Research
The objective and scope of this research are to investigate the critical front-end
and back-end millimeter-wave building blocks such as low-noise amplifier (LNA), down-
and up- conversion mixers, voltage-controlled oscillator (VCO), power amplifier (PA),
high-speed frequency divider, frequency multiplier, passive balun and quadrature power
splitter that are needed to accomplish a more complete front-end transmitter and
receiver. Combined novel analog and microwave circuit design techniques are used
extensively to overcome the difficulties encountered in the design (including a high
linearity requirement, low noise performance, and high output power) as well as to
optimize the individual circuit for the best millimeter-wave performance. Upon
successful demonstration of the critical building blocks and front-end integration, a more
ambitious effort could be dedicated the development of a high performance phased
array transceiver. This transceiver would consist of multiple antennas that enable beam
and null forming in various directions using electronic steering in an effort to eliminate
the need for continuous mechanical reorientation of the antennas. In addition, with
multiple-input-multiple-output (MIMO) as a diversity technique, the system can further
improve the link quality.
1.3 Publications
[1] A. Y.-K. Chen, H.-B. Liang, Y. Baeyens, Y.-K. Chen, and Y.-S. Lin, “A broadband millimeter-wave low-noise amplifier in SiGe BiCMOS technology,” in IEEE Silicon Monolithic Integrated Circuits in RF systems (SiRF), Orlando, FL, Jan. 2008, pp. 86–89.
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[2] A. Y.-K. Chen, H.-B. Liang, Y. Baeyens, Y.-K. Chen, J. Lin, and Y.-S. Lin, “Wideband mixed lumped-distributed-element 90o and 180o power splitters on silicon substrate for millimeter-wave applications,” in IEEE Radio Frequency Integrated Circuit (RFIC) Symposium, Atlanta, GA, Jun. 2008, pp. 449–452.
[3] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A 36–80 GHz high gain millimeter-wave double-doubled active frequency doubler in SiGe BiCMOS,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 9, pp. 572–574, Sep. 2009.
[4] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A low-power linear SiGe BiCMOS low-noise amplifier for millimeter-wave Active imaging,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 2, pp. 103–105, Feb. 2010.
[5] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A W-band highly linear SiGe BiCMOS double-balanced active up-conversion mixer using multi-tanh technique,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 220–222, Apr. 2010.
[6] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A 68–82 GHz integrated wideband linear receiver using 0.18 μm SiGe BiCMOS,” accepted, IEEE Radio Frequency Integrated Circuit (RFIC) Symposium, Anaheim, CA, May. 2010.
[7] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A 21 dB gain 87 GHz low-noise amplifier using 0.18 μm SiGe BiCMOS,” IEE Electron. Lett. vol 46, no. 5 pp. 332–333, Mar. 2010.
[8] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A W-band high gain double-balanced active up-conversion mixer using 0.18 μm SiGe BiCMOS,” submitted to IEE Electron. Lett.
[9] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A 100 GHz SiGe BiCMOS regenerative frequency divider using inductive peaking technique,” in preparation for IEE Electron. Lett.
[10] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “Design and characterization of W-band high gain power amplifiers for high-speed point-to-point link and automotive radar applications,” in preparation for Journal of Solid-State Circuits (JSSC).
[11] A. Y.-K. Chen, H.-B. Liang, Y. Baeyens, Y.-S. Lin, Y.-K. Chen, and J. Lin, “A tunable phase-compensated wideband millimeter-wave quadrature power splitter on silicon substrate,” in preparation for Transactions on Microwave Theory and Techniques (TMTT).
1.4 Outline of Dissertation
This dissertation presents and demonstrates some of the aforementioned circuit
blocks necessary for system integration. Chapter 2 reviews some indispensable figures
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of merit (FoMs) to characterize a device technology. Chapter 3 presents three LNAs for
various applications at 60 GHz, 70–80 GHz, and 90 GHz band. Next, in Chapter 4, two
180o and 90o power splitters using the back-end-of-the-line (BEOL) of the technology
are demonstrated. Chapter 5 shows a high gain wideband double-balanced frequency
doubler while Chapter 6 shows a highly linear up-conversion mixers using multi-tanh
triplet technique. Chapter 7 demonstrates an integrated wideband linear receiver.
Chapter 8 discusses a method to further extend the operating frequency of an oscillator
implemented with Indium Phosphide (InP) technology. Finally, Chapter 9 summarizes
the dissertation and discusses the future works.
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CHAPTER 2 MILLIMETER-WAVE ACTIVE AND PASSIVE DEVICES
2.1 Introduction
In recent years, the considerable advances in silicon-based technologies propelled
by high performance digital applications such as microprocessors and digital signal
processing have been now deemed comparable to the III-V compound semiconductors
in many aspects. However, some intrinsic barriers such as low carrier mobility, low
resistivity, and non-insulating silicon substrate still present many technical challenges
for performance of silicon-based technologies. Thanks to the aggressive device
geometry scaling in CMOS and SiGe HBT, the millimeter-wave circuit performance
which can be quantified by transit frequency (fT), maximum oscillation frequency (fmax),
and minimum noise figure (NFmin) are continuously being improved. High fT and fmax of
300 GHz in SiGe BiCMOS have been demonstrated in [6], [7]. These remarkable
metrics have enabled the design of millimeter-wave integrated circuits with low power
and high performance. The ability to integrate with the digital backend in silicon
technologies means high system integration is possible, thereby reducing the number of
separate modules needed in a traditional III-V approach. This research has
demonstrated that lower overall system cost can be expected with silicon technologies
than with their III-V semiconductors counterpart. Moreover, higher yield achievable with
silicon technologies is also important to reduce the manufacturing cost.
In this chapter, different figures of merit such as fT, fmax, and different power gain
definitions will be introduced to quantify the performance of a given device technology.
Several properties of HBT device such as transconductance and NF will be outlined.
Next the JAZZ 0.18 μm SiGe BiCMOS technology used for the millimeter-wave circuit
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designs will be presented. Back-end-of-the-line (BEOL) technology will be outlined. And
finally two types of commonly used transmission lines will be discussed and compared.
2.2 Front-End Technology
2.2.1 Device Figures of Merit (FoMs)
For small signal applications, the transit frequency fT (current-gain-bandwidth
product) is a useful figure of merit which is defined as the frequency at which the short
circuit current gain becomes unity. It is mainly important for analog design and is
typically used to characterize the gain-bandwidth product of a lumped amplifier stage.
As each process shrinks, the lateral and vertical scaling led to lower parasitic and thus
faster speed for the CMOS and BiCMOS devices. In additional, the modification of the
doping SiGe base layer combined with the reduction in the graded base width have
improved the base transit time, resulting in an increase in device speed. Subsequent
reduction in the epi layer thickness also leads to a decrease in the collector transit time,
further increasing the fT. This can be derived by converting from S parameters to H
parameters h21 which denotes forward current gain as follows:
12212211
2121 )1)(1(
2
SSSS
Sh
(2-1)
In normal frequency range, h21 rolls off with -20 dB/decade. At lower frequencies,
leakage may lead to flat h21 while inductive parasitic gives resonance in h21 at high
frequencies. It is worthwhile to mention that de-embedding is crucial to determine the
intrinsic fT of the device. In the first order approximation, fT can also be expressed as
follows:
)(2 CC
gf mT (2-2)
25
where Cπ is the sum of the base-emitter junction depletion-layer capacitance and the
emitter diffusion capacitance while Cμ is the base-collector junction depletion-layer
capacitance [8]. Sometimes, fT is also useful to quantify the speed of large signal digital
circuits such as ECL static dividers.
Unlike circuit designs at RF < 5 GHz where the operating frequencies are much
less than the maximum oscillation frequency fmax in which the device performance can
be treated independently of the device layout, at millimeter-wave, the device
performance can be adversely impacted by the layout. fmax is defined as the frequency
at which the device becomes passive (or maximum power gain is unity). In many
circuits, fmax is considered as a more important FoM than the actual fT which does not
take into account the need to push and pull the currents in the circuits through the loads.
fmax is not influenced by lossless matching networks applied at input and output or by
lossless feedback networks. Additionally, fmax is independent of circuit topologies such
as common-base (gate), common-emitter (source), common-collector (drain). As the
name suggests, fmax is the maximum frequency at which the device can be made to
oscillate (fundamental). Therefore it gives maximum operating range for oscillators.
Losses in resonator, bias, and matching networks in practical applications will reduce
the maximum frequency. Additionally, fmax also provides an insight about the maximum
frequency and useful power gain the device will have for tuned resonant amplifiers.
Figure 2-1 shows a simplified HBT model to characterize fmax. The fmax can be
approximated as
cbib
T
Cr
ff
8max (2-3)
26
Cbe
Ccbi
Ccbx
gmVbeRbe
RbbB C
E
Rex
Rcrb
Figure 2-1. Simplified HBT model.
Where Ccbi and Ccbx are intrinsic and extrinsic collector-base capacitance, respectively.
Note that to obtain a high fmax, the base resistance rb and Ccb should be reduced.
Reduced rb can be achieved by selecting a large but fingered device. This also helps
reduce the noise contribution of the device. However, large size requires large current
drive for peak fT and fmax, and more importantly the junction capacitance also increases
with the larger transistors. Therefore compromises have to be made to suit the
individual functional block performance.
Before getting to the determination of fmax, several gain definitions should be
discussed. Figure 2-2 shows the circuit diagram for maximum available gain (MAG)
extraction.
Vsig
LosslessMatchingNetwork
LosslessMatchingNetwork
Rsig
RL
Figure 2-2. Circuit diagram for maximum available gain extraction.
27
When the device is unconditionally stable, there exists a maximum available gain
for the device under test. The matching networks are lossless and are used to achieve
simultaneously conjugate input and output match. This gain can be expressed as
follows:
12
12
21 KKS
SMAG (2-4)
Where K is Rollet stability factor and should be ≥1 for stability. When K is less
than unity, then MAG is no long valid, instead maximum stable gain (MSG) shall be
introduced. Figure 2-3 shows the circuit diagram for maximum stable gain (MSG)
extraction.
Vsig
LosslessMatchingNetwork
LosslessMatchingNetwork
Rsig
RL
Resistive Stabilization
Figure 2-3. Circuit diagram for maximum stable gain extraction.
Since the device is conditionally stable, the device first needs to be stabilized
with resistors. Then the device is simultaneously conjugate input and output matched.
The MSG can be expressed as follows:
12
21
12
21
S
S
Y
YMSG (2-5)
In MSG, K is exactly equal to unity and this defines the knee frequency where the
device is right on the boundary between stability and instability. Note that in the first
order, MSG does not depend on fT or rb. For the hybrid-П model, MSG rolls off at -10
28
dB/decade while MAG has no fixed slope. In general, the fmax can be extrapolated from
MAG. However, the accuracy of this could sometimes be uncertain since the slope
changes as a function of frequency (depending on K). A more accurate extraction of fmax
can be extrapolated from Mason’s unilateral power gain (GU). Figure 2-4 shows the
circuit diagram for Masons’ unilateral power gain (GU) extraction.
Vsig
LosslessMatchingNetwork
LosslessMatchingNetwork
Rsig
Shunt Feedback
Series Feedback
RL
Figure 2-4. Circuit diagram for Mason’s unilateral power gain extraction.
Lossless reactive feedback networks are used to compensate for the device feedback
Y12. The device is then stabilized and simultaneously conjugate input and output
matched. The GU can be expressed as follows:
12212211
2
1221
4 GGGG
YYGU
)/Re(/
1/
2
1
12211221
2
1221
SSSSk
SS
(2-6)
29
For the hybrid-П model, GU rolls off at -20 dB/decade and is independent of all the
lossless reactive elements and pad reactance. Therefore the fmax can be more reliably
obtained after the extrapolation from Mason’s gain. It is interesting to point out that GU
remains unchanged regardless of the circuit topology.
2.2.2 Heterojunction Bipolar Transistor (HBT) Devices
SiGe BiCMOS processes integrated high-performance heterojunction bipolar
transistors (HBTs) with state-of-the-art CMOS technology. Bipolar devices are
developed for front-end high speed and high frequency operation. Bipolar transistors
are preferred for RF designs due to the higher value of gm achievable for a given bias
current. MOS devices on the other hand are mainly being considered for backend digital
or high-density DSP functions. In such case, the co-existence of both bipolar and MOS
devices suggests that SiGe BiCMOS can be a viable candidate to address the individual
needs and enhance the circuit performance.
When compared to CMOS devices, SiGe HBTs exhibit lower 1/f noise, higher
transconductance (gm), higher output resistance (ro), and higher breakdown voltage for
the same device speed. In particular, the intrinsic gain which is set by gmro can help to
better justify the technology of choice. Transconductance is the ability of the device to
source the current due to the exponential relationship between the output current in
response to the input voltage of the bipolar device. Its transconductance is much better
than that of an FET where the relationship is only quadratic. To see the difference, gm of
the bipolar and FET can be expressed by (2-7) and (2-8) as follows:
kT
qIg C
BJTm , (2-7)
DMOSm Iconstg ., (2-8)
30
The transconductance of the bipolar is proportional to the collector current IC while
the transconductance of the FET is only proportional to the square root of its drain
current ID. Besides, by adjusting the Ge concentration which modifies the electric field
across the base and thus the carrier concentration, it improves the Early voltage (VA),
therefore the output resistance. These advantages are particularly meaningful for
millimeter-wave VCO and power amplifier designs. In addition, fmax of an HBT is less
sensitive to layout parasitic and this further enhances the design robustness.
In bipolar transistors, the 1/f noise is mostly generated in the emitter/base
junction. MOS devices, on the other hand are surface conduction devices where the
current flow is affected by the properties of the Si/SiO2 interface. The quality of the p-n
junction and the quality of the oxide interface dictate the power of the 1/f noise. The
HBT devices these days tend to have a clean Si/SiGe interface and their noise
properties, especially 1/f noise are significantly better than that of MOS devices.
Moreover, node-to-node scaling in FETs moves oxide interfaces even closer to the
active channel, resulting in a poorer 1/f noise performance. In bipolar, NF depends on
the intrinsic base resistance rb, emitter resistance re, internal capacitances and
transconductance. However, the addition of Ge implanted into the base changes the
band-gap voltage in a way that suppresses reverse hold injection from base to emitter.
This allows the base doping to be greatly increased. Heavier doping decreases the
base resistance and therefore lowers the thermal noise of the base. The heavier doped
poly emitters also lead to lower emitter resistance.
Device matching is another issue to consider especially in analog design. The
matching of VBE is determined by the doping profiles of the p-n junctions across the
31
emitter-base. With each technology node scaling, these doping levels increase and
therefore better matching can be expected.
Due to constant field scaling, the optimal current density for peak fT, peak fmax, and
NFmin remained unchanged from one technology node to another. This is convenient
when porting the design from one node to another. However, for HBT with different
technology nodes, the optimal current density for peak fT, peak fmax, and NFmin varies.
Higher collector current density (JC) at a given fT can be obtained by increasing the
collector doping, which delays the onset of the Kirk effect. For a given fmax, the higher
current density along with high breakdown voltage in HBTs offers significant advantage
over the MOS devices for large signal circuit blocks such as VCO and PA. This high
power capability shows that SiGe HBTs are at least competitive with transistors made in
III-V semiconductors.
2.2.3 JAZZ 0.18 μm SiGe BiCMOS Technology
All active circuits in this dissertation are designed and fabricated with JAZZ 0.18
μm SiGe BiCMOS technology [9], [10]. The effective emitter width of the HBT is 0.15
μm. The breakdown voltages VCEO and VCBO of the HBT are 1.8 V and 5.8 V,
respectively. The low-cost technology is accomplished without employing extra
processing steps such as selective epitaxy and raised extrinsic base to further enhance
the fT and fmax [6], [7]. In short, having a technology that has a high process uniformity,
high reliability, high yield, high design robustness, and high integration level will be of
significant interest. Figure 2-5 shows a top view of a simplified HBT device layout.
The SiGe BiCMOS technology also features 0.18 μm CMOS transistors with 1.8 V
and 3.3 V supply options for digital backend, enabling high system level integration. The
32
B
B BC CE
SUB
SUB
SUB
SUB
Figure 2-5. Top view of a simplified HBT device layout.
passive components available in the design library include rectangular and octagonal
spiral inductors with patterned ground shield (PGS) option, vertical metal-insulator-metal
(MIM) capacitors (2 fF/μm2), and thin-film, low- and high-density poly resistors. Shown
in Figure 2-6(a), (b), and (c) are the simulated transit frequency (fT), maximum
oscillation frequency (fmax), and maximum power gain (Gmax) plotted against collector
current (IC) for different device configurations (CBEB, CBEBC, and CBEBEBC) and
emitter lengths (EL) at 1.7 V supply voltage. As can be seen the optimal current density
for peak fT and fmax is ~10 mA/μm2. It is also observed that CBEBC configurations with
smaller EL achieve highest fT for speed and highest fmax for power gain and noise
performance. Note that fmax is strongly dependent on device layout which modulates the
base resistance rb and base-collector capacitance Cbc.
33
0 5 10 15 20 25 30 3550
100
150
200
250
Tra
nsi
t F
req
uen
cy (
GH
z)
Collector Current IC (mA)
CBEB (3 m)
CBEBC (3 m)
CBEBEBC (3 m)
CBEB (8 m)
CBEBC (8 m)
CBEBEBC (8 m)
A
0 5 10 15 20 25 30 3550
100
150
200
250
Max
. O
scil
lati
on
Fre
q.
(GH
z)
Collector Current IC (mA)
CBEB (3 m)
CBEBC (3 m)
CBEBEBC (3 m)
CBEB (8 m)
CBEBC (8 m)
CBEBEBC (8 m)
B Figure 2-6. Simulated A) Transit frequency (fT). B) Maximum oscillation frequency (fmax).
C) Maximum power gain (Gmax) against collector current (IC) for different device configurations and emitter lengths.
34
0 5 10 15 20 25 30 350
2
4
6
8
10
Ma
xim
um
Po
we
r G
ain
(d
B)
Collector Current IC (mA)
CBEB (3 m)
CBEBC (3 m)
CBEBEBC (3 m)
CBEB (8 m)
CBEBC (8 m)
CBEBEBC (8 m)
C Figure 2-6. Continued
2.3 Back-End-of-Line (BEOL) Technology
The back-end-of-the-line of the technology features six aluminum metal layers.
Aluminum material has a lower conductivity which gives rise to slightly higher skin depth
s compared to copper metal layers. At mm-wave, due to the skin effect, both materials
suffer significant loss and which affects the quality factor Q of the inductor. As the
frequency increases, currents start to flow in the substrate through capacitance and
magnetic coupling. This loss of energy into the substrate causes an effective increase in
resistance. In addition, the skin effect starts to raise the resistance of the metal traces at
high frequencies. For millimeter-wave dedicated BEOL, 2 to 3 thicker metals are desired.
On the other hand, the low resistively substrate allows the field lines to penetrate and
induce losses. In fact, as the total dielectric height reduces from one technology node to
another, the influence of the substrate losses on the propagation constant increases.
The vertical shrink of the BEOL imposes very strict layout design rules in terms of metal
35
densities per unit area and also electromigration rules at high temperature. In addition,
the stress rule which dictates the width of the interconnects allowed implies that
cheesed structure is needed to maintain the homogeneity of the metallization. Figure 2-
7 outlines the cross sections of SiGe BiCMOS BOEL. The top metal 6 is 2.81 μm thick
and should be used to implement spiral inductors or transmission lines. The total
dielectric height is 10.82 μm and this distance is crucial to reduce the loss and increase
the inductance per unit length.
2.4 Design and Modeling of Transmission Lines
Transmission lines are essential passive elements at mm-wave since there is no
ambiguity in defining the reference plane. The signal and ground are co-located and as
such, it is easy to make connections and transitions. The transmission lines have well-
known characteristic which avoid degradation in analog or digital systems due to
reflections, ringing and limited bandwidth. The structure provides a well-defined path for
return current which reduces magnetic and electric field coupling to adjacent structures
and lossy substrate. Moreover, all the interconnects can be modeled directly with
transmission lines. Unlike the RFIC designs at lower frequencies (physical circuit
dimension << electrical wavelength), this modeling is critical especially at mm-wave
where any metal traces on the order of a wavelength exhibits distributed effect. The
modeling of the interconnect is necessary to correctly transfer the signal power from
one point to another. To account for distributed effect which causes the voltages and
currents to vary in magnitude and phase over its length, impedance matching is
therefore required on internal mm-wave nodes within the circuit to ensure maximum
power transfer. Transmission lines in this case can be used as circuit elements for
36
0
0.28
0.49
1.14
1.66
2.46
2.98
3.78
4.3
5.1
5.72
7.72
9.31
11.31
14.12
Substrate
FO X
poly
M 1
M 6
M 5
M 4
M 3
M 2
O VC O xide (Erel=4.2)
O V C N itrie (Erel=7)14.32
14.92
cont
Z-Coordinate (um )
V ia5
V ia4
V ia3
V ia2
V ia1
IM D 5(Erel=4.2)
IM D 4(Erel=4.2)
IM D 2(Erel=4.2)
IM D 3(Erel=4.2)
IM D 1(Erel=4.2)
ILD (Erel=4.1)
(Thickness)0.6 um
2 um
2 um
0.62 um
2.81 um
1.59 um
0.8 um
0.52 um
0.2 um
0.8 um
0.52 um
0.52 um
0.8 um
0.65 um
0.21 um
0.28 um
A ir
Figure 2-7. Cross sections of SiGe BiCMOS BEOL.
reactive matching which optimize the power transfer and realization of resonators for
oscillator design.
37
Figure 2-8(a) and (b) show two common implementations of on-chip transmission
lines, namely, coplanar waveguide and thin-film microstrip line. The CPW is
implemented with one signal line surrounded by two adjacent grounds. By varying the
signal-to-ground spacing, Zo can be changed. The larger the gap spacing S, the more
fields penetrate into the substrate and cause additional shunt losses. On-chip CPWs are
believed to present higher quality factor Q for an inductor [11]. However, since CPW
consists of three unconnected conductor plates, there exit the even mode and odd
mode. The undesired odd mode at discontinuity can be converted to an asymmetric
slot-line mode which presents wrong characteristics. Underpasses thus have to be used
to force the two ground plates to achieve the same potential. The isolation to the
neighboring transmission lines is also achieved due to the two adjacent ground plates.
Si Substrate
ToxTmet W S Top metal layer
Electrical field lines
A Si Substrate
Tox
Top metal layer
Bottom metal layer (GND)
Electrical field lines
W
B
Figure 2-8. A) Coplanar waveguide. B) Thin-film microstrip line.
In this dissertation, all the inductors are implemented with thin-film microstrip
transmission lines. The line structure provides a better accuracy in attaining the
characteristic impedance (Z0) and a well-defined path for the return current. In addition,
microstrip lines can be reliably and quickly predicted and modeled using EM simulators.
This shortens the overall design cycle since test structures are not necessary to verify
the accuracy. More importantly, the equivalent inductance can be approximated by the
equation (2-9) if l << λ/4.
38
lf
ZL
o
o
tan2
(2-9)
2
(2-10)
o
e
f
C
(2-11)
Where Zo is the characteristic impedance, l is the length of the line, β is the phase
constant, εe is the characteristic effective dielectric constant, and C is the speed of light.
The approximation can be used for initial back-of-envelope calculation to determine the
required length of the line for a given inductance. As an additional benefit, microstrip
lines can be made more compact, therefore affecting the overall chip size. The top
metal (M6) is used as signal line and the bottom metal (M1) is used as ground plane to
minimize conductor loss. The effective dielectric height for such a line structure is
9.65 μm. The characteristic impedance Zo can be increased by reducing the width at the
Figure 2-9. Simulated loss of quarter-wavelength (λ/4) line plotted against characteristic impedance (Zo).
39
expense of additional loss. Therefore the narrower lines give higher inductance per unit
length. The full ground plane shielding was adopted including the RF I/O pads to
minimize the substrate loss and provide good average ground potential [12]. To avoid
the crosstalk between the lines, the spaces between the microstrips are made more
than three times the dielectric thickness.
The modeling of the thin-film microstrip is done with SONNET EM simulator and
then further verified by Agilent ADS Momentum. Both simulators support up to 2.5 D
accuracy, which is necessary to correctly capture the effect of finite thickness of the
metals. Figure 2-9 shows a simulated loss of quarter-wavelength λ/4 line against
characteristic impedance (Zo) using SONNET EM simulator. The length of a quarter-
wavelength line (λ/4) is ~600 μm at 60 GHz in this technology and the 50 Ω line is
achieved with a line width of 16.5 μm and has a loss of 0.46 dB per millimeter at 100
GHz.
40
CHAPTER 3 LOW-NOISE AMPLIFIERS (LNAS)
3.1 Introduction
The low-noise amplifier remains to be the most essential building block especially
in a millimeter-wave radio design. The key requirements in an mm-wave LNA design
include low-noise figure, power gain, linearity, wide matching bandwidth, stability,
robustness to PVT variation, and power dissipation. When the weak signal along with
the noise is received at the antenna, the low-noise amplifier must be capable of
amplifying the weak signal while adding only minimum noise to it. In fact, the first stage
is always being considered as the most critical building block in terms of contribution to
noise figure. The power gain presented by the same block can either emphasize or de-
emphasize the noise figure contribution from the subsequent stages such as image
reject filter, mixer, and/or active balun. Design for linearity should also be dedicated if
the LNA consists of multi-stage because the linearity of the later stages will dominate
the overall receiver linearity, therefore dynamic range.
Matching network design is also crucial as it sets the bandwidth of the amplifier,
matching for maximum power or minimum noise. The correct choice of a network
topology could also help reduce the overall loss due to the excessive length of the
transmission lines which typically render lower power gain of the amplifier, larger chip
size, and narrower 3-dB bandwidth.
To contrast with the LNA designs below 10 GHz which lumped design approach is
valid, the thought process for mm-wave design must take the distributed effect into
consideration. All the metal traces and interconnections are now on the order of a
wavelength. When this happens, the interconnections can no longer be treated just like
41
a trivial node to node connection. In fact, they should be accurately modeled as
transmission lines in one way or another. Another implication is that the impedance
matching is necessary on internal nodes within the circuit to ensure maximum power
transfer.
At mm-wave, the device is operating at much closer to the cutoff frequencies,
namely, fT and fmax. This gives rise to an amplifier with higher NF and lower power gain.
Usually multi-stage is required to meet the gain requirement at cost of power dissipation
and linearity. To make things worse, the parasitic associated with the nodes is
significant enough to shift the desired operating frequency. This indicates that a design
margin is needed to enhance to robustness and reliability. Therefore, the trade-offs
have to be thoughtfully deliberated to achieve the design goal.
In this chapter, four LNAs with different design approaches emphasizing on
bandwidth and linearity will be described. Amplifier stability analysis will be presented in
section 3.2. Finally the experimental results will be discussed.
3.2 62 GHz Broadband Feedback Cascode LNA
3.2.1 Circuit Topology
Conventional bipolar-based low-noise amplifiers utilize inductive degeneration at
emitter together with base inductor to achieve simultaneous power match and noise
match [13]. This is true for heterojunction bipolar transistors (HBTs) where the noise
sources in,b and in,c can be assumed uncorrelated for design frequencies less than fT/2
[14]. However, due to emitter degeneration, power gain reduction in the initial stage
gives rise to signal-noise-ratio degradation in the subsequent stages. More interestingly,
the parasitic associated with the non-trivial degenerated inductor along with the base
inductor and base-emitter capacitor tends to narrow the 3 dB bandwidth and de-stabilize
42
the amplifier at millimeter-wave. In this section, a wideband LNA based on a simple two-
element input matching network is presented.
The schematic of the 62 GHz low-noise amplifier is shown in Figure 3-1. The
amplifier consists of two cascode stages, in which the first stage is biased and sized for
minimum noise figure (NFmin) and the second stage is optimized for good gain and
linearity. Resistors R1 and R2 set the proper quiescent points for the cascode devices
Q2 and Q4, respectively. C4 and C5 are used as high frequencies bypass. A shunt
resistor-capacitor feedback is used to linearize the second stage while compromising
the gain. The cascode topology was chosen for its high gain, stability, and robustness to
process and model variations [15].
Figure 3-1. Circuit schematic of the two-stage 62 GHz low-noise amplifier.
43
3.2.2 Stability Analysis
Stability design has always been posing many challenges in an amplifier design. A
good amplifier design should be unconditionally stable at all frequencies, including DC.
Stability design can be decomposed into low frequency and high frequency. The
boundary is typically set by the knee frequency, the frequency between maximum stable
gain (MSG) and maximum available gain (MAG) of an active device or when the stability
factor (K) equals to unity. At low frequencies, the device is often not stable since it is
capable of providing substantial gains. Because of the feedback capacitor which makes
the active device bilateral, the device at these frequencies is very likely to present
instability. On the contrary, this is less true at high frequencies especially at mm-wave.
However, when inductive degeneration is used in an amplifier design as part of the
matching network, the parasitic capacitance contributed by the inductor needs to be
carefully attended and this will be discussed in section 3.3.1. Nevertheless, the overall
stability has to be maintained if it is a multi-stage amplifier design. In which case, all the
internal nodes need to be examined more individually.
The cascode amplifier provides better stability compared to the common emitter
structure because of the reduced feedback from the Miller capacitance Q1. The cascode
topology shields the Miller capacitance from the load and improves the isolation, hence
S12. However, cascode topology can still present high frequency instability and cause
the amplifier to oscillate due to non-optimal layout. Figure 3-2(a) and 3-2(b) show the
cascode stage and its small signal equivalent circuit, respectively [16].
To gain an intuition, the bottom transistor Q1 can be replaced with a capacitor Cout1
to ground at high frequency. Assuming ZCbe << rbe at the frequency of interest, which is
44
A
B
Figure 3-2. A) Cascode circuit for stability analysis. B) Small signal equivalent circuit of the cascode circuit.
valid at millimeter-wave, the input impedance looking into the base of the cascode
device is
out1beout1be2
mbin, ωC
1
ωC
1j
CCω
gZ
inin XR (3-1)
The first term in the equation (3-1) has shown a negative real part which is
generated by the capacitive degeneration from the bottom device Q1 output impedance.
The oscillation is possible if the magnitude of Rin is larger than the loss (RB) of the series
45
resonant tank formed by CB, LB, where LB is the parasitic inductance of interconnects
and CB. Zin,a shows the input impedance including CB and the parasitic inductance
Bout1beout1be2
main, ωC
1
ωC
1
ωC
1j
CCω
gZ jω LB (3-2)
The oscillation frequency is therefore determined by LB, CB, Cbe, and Cout1. Note
the above analysis has ignored the effect of Cbc of the top device Q2. Though it is
possible to add an extra series resistance at the base of the cascode device Q2 to damp
the oscillation, it is typically not preferred for LNA design as the series resistor will
worsen the noise performance and also cause gain reduction. The low frequency
stability is improved with a series RC network (R4-C7). The small value resistor R4
reduces the gain at low frequencies, and helps the Edwards-Sinsky stability factor μ to
stay above unity [17].
Despite the potential risk of low and high frequency oscillations, with careful
design and layout, the amplifier is unconditionally stable from DC to 110 GHz, and
under all bias conditions.
3.2.3 Synthesis of Matching Networks
The input matching network consists of a microstrip transmission line TL1 and an
equivalent shunt capacitor C1. The input matching network is designed to synthesize the
optimum reflection coefficient, Γopt, for minimum noise figure from the characteristic
impedance (50 Ω). The solution that yields the shortest TL1 is adopted as any extra line
loss especially at the input will be detrimental to the noise figure. A small value shunt
capacitor C1 is realized equivalently with four capacitors in series. The lumped method
has helped reduce the coupling of the lines and the form size. While it is possible to use
a multi-order LC-ladder for wideband matching [18], it is not preferred at millimeter-wave
46
where the losses from the extra passive components at input will directly couple to the
overall noise figure and degrade the gain
The transmission line TL2 and capacitor C2 are designed for interstage matching.
Proper selection of the component values gives the best compromise between gain and
linearity. The output is conjugately gain matched to the 50 Ω load. Though the cascode
topology used in the design is good for gain and isolation, but it is also notorious for its
narrowband output matching due to the Bode-Fano criterion [19]. The output impedance
looking into the collector of the output cascode Q4 is relatively high compared to that of
a CE stage, making cascode stage harder to achieve wideband matching. A shunt RC
feedback (R3-C3) is introduced to broaden the bandwidth at the expense of the gain.
The input and output RF pads are modeled as shunt capacitors and series inductors
and are used as part of the matching networks.
3.2.4 Experimental Results
The chip microphotograph of the LNA is shown in Figure 3-3. The resulting
dimension of the chip is 560 μm x 360 μm (0.2 mm2). The measured power gain (S21) is
shown in Figure 3-4. The parasitic of the RF pads has been taken into consideration
during simulation so no pad de-embedding is performed. The measured maximum
transducer gain is 15.8 dB at 62 GHz when biased at 2.5 V and reaches 19.2 dB when
biased at 3.3 V supply. The 3-dB bandwidth is 54 GHz to 70 GHz. The measured S11
and S22 are both depicted in Figure 3-5. The output return loss S22 is 18 dB at 62 GHz
and is better than 12 dB from 59 GHz to 72 GHz. The input return loss S11, however, is
8 dB at 62 GHz. This deviation is primarily due to the small shunt capacitor C1 needed
to synthesize the input matching network. As mentioned in 3.2.3, four equivalent
capacitors in series were used to realize the small value capacitor C1. Post simulation
47
has revealed that the parasitic capacitance associated with the series-connected
capacitors has caused such a deviation. This small value capacitor may be better
realized by an open shunt stub. Therefore, for better accuracy at millimeter-waves,
distributed elements could be considered to replace the lumped counterparts. The
reverse isolation |S12| shown in Figure 3-6 is better than 40 dB across the 3-dB
bandwidth. The LNA is unconditionally stable from DC to 110 GHz. The noise
measurement was conducted with a calibrated V-band noise source and a waveguide
down-converter. Figure 3-4 shows the measured noise figure (NF) when biased at 2.5 V
supply. The NF is 6.8 dB at 62 GHz and is 6.3 dB, the lowest at 64 GHz. An additional
loss of ~1 dB was accounted for the input WR-15 waveguide probe while the noise
contribution from the loss of the down-converter and the output 1 mm cable were not
corrected. The input 1 dB gain compression point (IP1dB) measurement result is shown
in Figure 3-7 and is -16.8 dBm at 62 GHz at 2.5 V. The estimated input-referred third
order intercept point (IIP3) is believed to be between -7 and -5 dBm.
Figure 3-3. Chip microphotograph of the two-stage 62 GHz low-noise amplifier.
RFin RFout
DC Bias
48
50 55 60 65 70 75 800
5
10
15
20
S2
1 a
nd
NF
(d
B)
Frequency (GHz)
3.3 V 2.5 V NF at 2.5 V
Figure 3-4. Measured power gain and noise figure of the 62 GHz LNA.
50 55 60 65 70 75 80-25
-20
-15
-10
-5
0
S11
an
d S
22 (
dB
)
Frequency (GHz)
S11 S22
Figure 3-5. Measured input and output return losses of the 62 GHz LNA.
49
50 55 60 65 70 75 80-70
-65
-60
-55
-50
-45
-40
-35
S1
2 (d
B)
Frequency (GHz)
Figure 3-6. Measured reverse isolation of the 62 GHz LNA.
-25 -20 -15-10
-5
0
5
10
15
Gai
n (
dB
)
Pout Gain
Pin (dBm)
Po
ut
(dB
m)
IP1dB = -16.8 dBm
0
5
10
15
20
Figure 3-7. Measured linearity characteristics of Pout and gain of the 62 GHz LNA.
50
Table 3.1 summarizes the performance of the previously reported ≥ 60 GHz
silicon-based single-ended low-noise amplifiers operating in a similar frequency range
[20], [11] and [21], including the one presented in section 3.2. For fair comparisons, the
figure of merit (FoM) computed in (3-3) has accounted for every aspect of the LNA
characteristics possible. Note that NFavg is strongly dependent on fT and fmax of the
technology.
diss
dBoLNA PNF
IPfGFoM
)1(
))(( 1max
(3-3) Table 3-1. Performance comparisons of ≥60 GHz silicon-based single-ended low-noise
amplifiers
Reference [20] [11] [21] THIS WORK 62 GHZ [16]
Technology fT/fmax (GHz)
0.13 μm SiGe BiCMOS 200/290
0.13 μm CMOS N.A/135
0.25μm SiGe HBT 200/200
0.18 μm SiGe BiCMOS 200/200
Frequency (GHz) 61.5 60 60 62
3 dB Bandwidth and Range (GHz)
11 57-68
14 51-65
9 56-65
16 54-70
S21 (dB) 14.7 12 14 15.8/19.2 S11 (dB) -6 <-15 -15 -8 S22 (dB) -17 <-15 -9 -18 S12 (dB) -40 <-45 N.A <-40
NF (dB) 4.5 8.8 6.8* 6.8 Input P1dB (dBm) -20 -10 N.A -16.8 Pdiss (mW) [email protected] [email protected] [email protected] [email protected] FoM 0.91 0.401 - 0.55
3.3 77 GHz Low-Power Linear LNA
3.3.1 Amplifier Circuit Design
The schematic of the two-stage LNA is shown in Figure 3-8. The first cascode
input stage is chosen for its higher power gain and improved input-to-output isolation at
51
the expense of higher NFmin (the effect of parasitic capacitance at CB device M2 input
ZCpara dominates over 1/gm-M2 at mm-wave) compared to the common emitter.
However, the finite contribution of base-collector capacitance (Cbc-M1) of device M1 at
mm-wave frequency could cause signal loss via Cbc-M1 and Cbe-M2 to ground. To mitigate
this effect, only two base fingers (CBEBC) are used for the input devices to decrease
Cbc-M1, Cbe-M1, and Cbc-M2. By using such configuration, the noise performance (NFmin)
and maximum power gain (Gmax) at high frequency are improved when compared with
the higher NFmin single-base device (CBE) and larger parasitic capacitance triple-base
finger device (CBEBEBC). Simulations have confirmed an improvement in both power
gain (S21) and NFmin by at least 1.5 dB and ~0.1 dB, respectively, at 80 GHz when
double-base finger devices are used for the LNA design instead of triple-base finger
devices. Common emitter (CE) with double-base finger device is used in the second
stage for its improved linearity and broader output matching bandwidth.
Assume the amplifier is first input matched to the 50 Ω source resistance RS, the
quality factor of the input resonant network Qnetwork (80 GHz) can to first order be
approximated by
S
TLTLFeedo
in
innetwork R
LLL
Z
ZQ
)(
)Re(
)Im( 21 (3-4)
where LFeed is the inductance of the feedline (~10 pH) and the Qnetwork is set to be 1.5
according to the initial choices of transmission line inductors (LTL1 and LTL2) in this
design. Next, the LTL1, LTL2, and input pad inductance (Lpad) along with devices M1 and
M2 are optimized and sized to achieve wideband noise matching. This is applicable
thanks to the lower Qnetwork (~1.3 after the optimization) which renders the design a
favorable wideband characteristic and better robustness to process variation. More
52
RFout
TL6
TL7
C2
VCC2
Bias2
R3
C5
M2
M1
TL3
TL4
TL2
TL1RFin
C1
R1
VCC1
Bias1
M3
TL5
C6R2
C3
C4
190 µm/80 pH
75 µm/35 pH
238 µm/155 pH
70 µm/40 pH
300 fF
160 µm/63 pH
235 µm/140 pH
130 µm/70 pH
8x0.15 µm2
8x0.15 µm2 6.8x0.15 µm2
500 O
2 pF
Feed
Feed
Vcas1
Figure 3-8. Circuit schematic of the two-stage 77 GHz low-noise amplifier.
importantly, the linearity (characterized by input P1dB) based on this input resonant
network is drastically improved by at least 3 dB at the expense of a slight increase in
NFmin by ~0.15 dB. Both inductive degenerations (LTL2 and LTL5) are utilized for linearity,
increasing Re(Zin), and low frequency stability. However, it is observed that at mm-wave
frequency the non-negligible parasitic capacitances Cpara associated with the
degenerated inductors could generate a negative resistance –gm/ 02CbeCpara to offset
the Re(Zin) and de-stabilize the amplifier. The presence of Cpara not only de-tunes the
input matching but also deteriorates the gain and NF of the amplifier. Under this
consideration, the inductor LTL2 (35 pH) is preferably kept small to reduce the
associated parasitic capacitance and preserve the power gain while satisfying the
necessary condition for wideband noise matching as described. The inductor LTL5 that
presents a larger inductance (70 pH) is chosen to further optimize the linearity of the
53
second CE stage; therefore further improving the overall input IP3. The cascode stage is
optimally biased for NFmin while the CE stage is biased at a slightly higher collector
current density (Jc) for linearity. High frequency instability due to the parasitic
inductance and resistance of the base interconnect is suppressed by placing the
capacitor C1 as close as possible to the base of M2 in layout.
The interstage matching network is synthesized with LTL3, LTL4, C2, and LTL5, with
the component values chosen to compromise among the gain, bandwidth, and linearity.
The output stage is conjugately power gain matched to the 50 Ω load with LTL6 and LTL7.
The wideband bypass capacitor arrays are used to reduce ground bounces at
millimeter-wave and internal loop oscillations at low frequencies.
3.3.2 Experimental Results
The low-noise amplifier was fabricated in a low-cost 200 GHz fT and fmax JAZZ 0.18 μm
SiGe BiCMOS process. All the inductors are implemented with thin-film microstrip
transmission lines. The top metal is used as signal line and the bottom metal is used as
ground plane to minimize the conductor loss. The full ground plane shielding was
adopted including the RF I/O pads to minimize the substrate loss and provide good
average ground potential [12]. The microphotograph of the fabricated LNA is shown in
Figure 3-9. The dimension of the chip including the pads is 650 μm x 630 μm. The LNA
is unconditionally stable from DC to 110 GHz. The simulated and measured S21 and
NF are shown in Figure 3-10. The amplifier has a measured peak power gain of 14.5 dB
at 77 GHz and a 3 dB bandwidth of 14.5 GHz from 69 to 83.5 GHz. The reverse
isolation is better than 33 dB over the 3 dB bandwidth. The simulated and measured
input and output return losses shown in Figure 3-11 are better than 11 dB and 17 dB at
77 GHz, respectively. The shift in S11 is due in part to the underestimation of the high
54
Figure 3-9. Microphotograph of the two-stage 77 GHz low-noise amplifier.
50 55 60 65 70 75 80 85 90 95 100-5
0
5
10
15
20
Frequency (GHz)
S21
an
d N
F (
dB
)
S21(M) NF(M) S21(S) NF(S)
Figure 3-10. Simulated and measured power gain (S21) and noise figure of the 77 GHz
LNA.
RFin RFout
DC
DC Bias
TL1
TL2
TL4
TL3
TL7
TL6
TL5
55
50 55 60 65 70 75 80 85 90 95 100-35
-30
-25
-20
-15
-10
-5
0
S11
an
d S
22 (
dB
)
Frequency (GHz)
S11(M) S22(M) S11(S) S22(S)
Figure 3-11. Simulated and measured input and output return losses of the 77 GHz
LNA.
-25 -20 -15 -10-10
-5
0
5
10
15
Gai
n (
dB
)
Pout Gain
Pin (dBm)
Po
ut
(dB
m)
Input P1dB = -11.4 dBm
0
5
10
15
20
Figure 3-12. Measured linearity characteristics of Pout and gain of the 77 GHz LNA.
56
Table 3-2. Performance comparisons of ≥ 77 GHz silicon HBT-based single-ended low-noise amplifiers
Reference [22] [23] [24] [25] This Work [26]
Technology fT/fmax (GHz)
SiGe:C BiCMOS 200/200
SiGe:C HBT 225/300
0.12 μm SiGe8T HBT 205/290
0.18 μm SiGe BiCMOS 200/200
0.18 μm SiGe BiCMOS 200/200
Number of Stages 3 2 2 4 2
Frequency (GHz) 79 77 77 77 77
3 dB Bandwidth and Range (GHz)
9 74-83
12 ~75-87
12 ~76-88
10 75-85
14.5 69-83.5
S21 (dB) 21.7 8.3 15 33 14.5 S11 (dB) -25 -26 -10 ~-10 -11 S22 (dB) -9 -19 -21 -6 -17 S12 (dB) -40 -33 -40 -45 -33 NF (dB) - 5.5 5.6 (sim) 6.2* 6.9 Input P1dB (dBm) - -3 -17 -40 -11.4 Pdiss (mW) 94 121 14.4 224.4 37
*denotes measurement result with 12 dB associated gain.
impedance TL1. The measured NF is 6.9 dB at 77 GHz and is lower than 8 dB from 64
to 81 GHz.
A slightly higher NF is attributed primarily to larger base resistance Rb (lower fmax)
of the device technology, chosen cascode topology as well as the adopted wideband
noise matching technique. Note however that the degradation in the NF due to the shift
in S11 is negligible, as confirmed in both simulation and measurement.
The IP1dB measurement result is shown in Figure 3-12 and is -11.4 dBm at 77 GHz.
The estimated IIP3 is believed to be between -2 and 0 dBm. The nominal supply
voltages of the first cascode and second CE stage are 3.3 V and 1.5 V, respectively.
The circuit draws a total of 15 mA and consumes only 37 mW given the fmax of the
device technology.
57
Table 3.2 summarizes the performance of the previously published ~77 GHz
single-ended low-noise amplifiers [22]–[25]. It is observed that the amplifier in this work
[26], compared to the other state-of-the-art silicon HBT-based single-ended low-noise
amplifiers, has achieved similar gain, NF, wide bandwidth at W-band, and high linearity
(IP1dB) with the lowest power consumption of only 37 mW.
3.4 87 GHz High Gain LNA
3.4.1 Amplifier Circuit Design
Multi-gigabit-per-second (multi-Gb/s) point-to-point (P2P) wireless links over
multiple kilometer transmissions have gained significant momentum in recent years.
The spectrum allocation in 71–76 GHz, 81–86 GHz, and 92–95 GHz bands have been
deemed suitable for realizing such high-data-rate millimeter-wave systems due to the
wide unchannelized bandwidth [27]. These bands in contrast to the 60 GHz band have
much lower atmospheric absorption thereby allowing longer transmission range. Other
promising applications including concealed weapon detection, medical imaging, and
weather observation sensor have also demanded for higher resolution radars operating
at 94 GHz [28]. However, most of the high performance circuits are still being realized
by the more expensive Gallium Arsenide (GaAs) and Indium Phosphide (InP)
technologies, including those commercially available on the market. So far, very few
fully characterized low-noise amplifiers have been reported with the more cost efficient
and higher yield SiGe BiCMOS processes. In one, a high gain four-stage common
emitter (CE) W-band (75–110 GHz) LNA has been demonstrated for imaging arrays [29]
while another single stage cascode LNA based on unilateral gain peaking was achieved
with reduced device profile [30], all implemented in IBM 8HP 0.12 μm 200/290 fT/fmax
SiGe BiCMOS technology. In this section, the performance of a highly competitive
58
two-stage high gain 87 GHz LNA fabricated in a low-cost 200 GHz fT and fmax JAZZ 0.18
μm SiGe BiCMOS technology.
Shown in Figure 3-13, the LNA consists of two cascode stages for high power gain (S21)
and improved isolation (S12) at the expense of higher NFmin. To achieve high gain with a
cascode at millimeter-wave frequency, only double-base finger devices (CBEBC) are
used instead of triple-base finger devices (CBEBEBC) to reduce both intrinsic and
extrinsic base-collector capacitance Cbc of device M1 and M2. By doing so, the signal
loss via Cbc-M1 and base-emitter capacitance Cbe-M2 to ground can be minimized. The
device size of the first cascode stage (M1 and M2) is chosen along with LTL1 and LTL2 to
synthesize a low quality factor (<1.5) input resonant network (Qnetwork). The selection
helps improve the linearity performance of the LNA and achieve wideband input
matching. Price to pay, however, is a slight increase in the overall NF. The first stage
was biased to compromise between the gain and NF while the second stage was
biased for gain and linearity. The emitter lengths (LE) of the device M1/M2 and M3/M4
are 9 μm and 6.8 μm, respectively. The interstage matching network was synthesized
with LTL3, LTL4, and C2. LTL5 and LTL6 were used to conjugately match the output stage to
50 Ω load. The corresponding inductance values associated with each transmission line
are LTL1 = 80 pH, LTL2 = 35 pH, LTL3 = 45 pH, LTL4 = 100 pH, LTL5 = 23 pH, and LTL6 =150
pH. Finally, broadband bypass capacitor arrays are used to reduce supply/ground
bounces at millimeter-wave and present resistive loading for low frequency stability.
3.4.2 Experimental Results
The chip microphotograph of the LNA is shown in Figure 3-14. The overall chip
size is 635 μm x 625 μm. Unconditional stability was ensured from DC to 110 GHz for
59
RFout
TL6
TL5
C2
VCC
Bias2
M2
M1
TL3
TL4
TL2
TL1RFin
C1
R1
VCC
Bias1
M3
R3
C4
C5
Feed
Feed
M4
C3
R4
C6
C7
Vcas1
R2
Vcas2
Figure 3-13. Circuit schematic of the 87 GHz low-noise amplifier.
Figure 3-14. Chip microphotograph of the 87 GHz low-noise amplifier.
RFin RFou
DC Bias
DC Bias
TL1
TL2
TL3
TL4
TL5
TL6
60
75 80 85 90 95 100 105 1100
5
10
15
20
25
S21(M) S21(S) NF(M) NF(S)
S21
an
d N
F (
dB
)
Frequency (GHz)
Figure 3-15. Simulated and measured power gains (S21) and noise figures of the 87 GHz LNA.
75 80 85 90 95 100 105 110-25
-20
-15
-10
-5
0
S11(M) S22(M) S11(S) S22(S)
S1
1 a
nd
S2
2 (d
B)
Frequency (GHz)
Figure 3-16. Simulated and measured input and output return losses of the 87 GHz LNA.
61
the LNA design. The measured and simulated S21 and NF are depicted in Figure 3-15. A
very good agreement between the measured and simulated results can be observed.
The LNA has a peak power gain of 21 dB at 87 GHz and a 3 dB bandwidth of 11.6 GHz
from 81 to 92.6 GHz. A gain of 10.2 dB was also obtained at 100 GHz. Input and output
return losses are 17.3 dB and 11.7 dB at 87 GHz, respectively, as shown in Figure 3-16.
Wideband input matching with input return loss greater than 10 dB is accomplished
across the W-band which is validated by the use of low Qnetwork. The reverse isolation is
better than 45 dB over the 3 dB bandwidth. The measured NF is 9.1 dB at 87 GHz and
is between 8–10 dB from 80 to 93 GHz. The input P1dB is -18.8 dBm at 87 GHz as
shown in Figure 3-17. The LNA draws a total current of 15.2 mA from a nominal 3.3 V
supply. For comparison purposes, the figure of merit (FoMLNA) in (3.3) is used to
account possibly for every characteristic of the LNA. Table 3.3 summarizes the
performance of the previously reported silicon HBT-based single-ended low-noise
amplifiers operating in a similar frequency range [29], [30]. The LNA in this work [31]
has demonstrated a better FoM even with the lower fmax of the technology compared to
[29].
3.5 Chapter Summary
Three low-noise amplifiers operating at 62 GHz, 77 GHz, and 87 GHz are
presented. First, a wideband LNA covering the minimum unlicensed 7 GHz bandwidth
from 59 GHz to 66 GHz was presented. It has been demonstrated that the cascode
topology, though, posts a limit on the quality of matching due to the high output
impedance, is a viable candidate to simultaneously achieve reasonable gain and wide
bandwidth using simple feedback at millimeter-wave. The results have shown a 3 dB
62
-28 -26 -24 -22 -20 -18 -1610
15
20
25
Gain
Po
ut
(dB
m)
Gai
n (
dB
)
Pin (dBm)
Input P1dB = -18.8 dBm
-10
-5
0
5
Pout
Figure 3-17. Measured linearity characteristics of Pout and gain of the 87 GHz LNA.
Table 3-3. Performance of previously reported ≥85 GHz silicon HBT-based single-
ended low-noise amplifiers
Reference [29] [30] This Work [31]
Technology fT/fmax (GHz)
0.12 μm SiGe BiCMOS 200/290
0.12 μm SiGe BiCMOS 200/290
0.18 μm SiGe BiCMOS 200/200
Number of Stages 4 1 2 Frequency (GHz) 88 91 87 3 dB BW (GHz) 80-97 84-100 81-92.6 S21 (dB) 19 13 21 S11 (dB) ~-6.3 ~-8 -17.3 S22 (dB) ~-8 ~-13 -11.7 S12 (dB) <-35 ~-20 <-45 NF (dB) ~8.5 5.1 9.1 Input P1dB (dBm) -22 - -18.8 Pdiss (mW) @ VDC [email protected] [email protected] [email protected] Chip Area (μm2) 0.3 0.59 0.4 FoM 0.29 N/A* 0.41
63
bandwidth of 16 GHz a peak power gain of 15.8 dB from 2.5 V, and an IP1dB of -16.8
dBm at 62 GHz. Next, the design of a low-power linear and wideband 77 GHz low-noise
amplifier was presented. The techniques for high linearity and wideband design have
been demonstrated. The LNA achieves a peak gain of 14.5 dB at 77 GHz with a 3 dB
bandwidth of 14.5 GHz from 69 GHz to 83.5 GHz. The measured NF and IP1dB are 6.9
dB and -11.4 dBm, respectively, at 77 GHz. Such characteristics of the LNA are crucial
for 71–76 GHz high speed point to point wireless link, 76–77 GHz long-range and
77–81 GHz short-range automotive radar applications. Last but not least, the 87 GHz
LNA has achieved a respectable peak power gain of 21 dB at 87 GHz with a measured
NF of 9.1 dB and an IP1dB of -18.8 dBm while dissipating a DC power of 50.2 mW from a
nominal 3.3 V. The experimental results have shown suitability of this LNA for 81–86
GHz, 92–95 GHz high speed wireless point-to-point links and 94 GHz high resolution
imaging applications.
64
CHAPTER 4 WIDEBAND MIXED LUMPED-DISTRIBUTED-ELEMENT POWER SPLITTERS
4.1 Introduction
In 2003, the Federal Communications Commission (FCC) has approved three new
commercial bands at 71 GHz to 76 GHz, 81 GHz to 86 GHz, and 92 GHz to 95 GHz to
be the true multi-gigabit-per-second wireless communication for fiber replacement or
extension, point-to-point wireless local area network, and broadband wireless internet
access [32]. Significant development efforts have also been dedicated to encompass
the 76 GHz to 77 GHz band for automotive radar applications. While the oxygen
absorption and rain attenuation hinder the transmission distance of the 60 GHz band,
the approved new bands provide more atmospheric deterioration resistance that
enables much longer transmission range (several miles). To achieve full-duplex data
rates of 10 Gbps, more spectrally efficient modulation schemes must be adopted; for
instance, M-ary phase shift keying (PSK) or quadrature amplitude modulation (QAM).
Figure 4-1 shows the simplified single sideband (SSB) quadrature transmitter and
receiver front end to exploit the necessary (de)modulations. In particular, the millimeter-
wave (mm-wave) 180° power splitters in the RF paths are used as baluns for single
ended to differential conversion and vice versa while the 90° power splitters are used for
quadrature generation in the LO paths. Therefore, it is desirable to have power splitters
that possess low insertion loss, good amplitude and phase balance, wide bandwidth,
and are compact in size.
Some favorable experimental results on distributed 180° and 90° hybrids at mm-
wave have been shown [33]. However, many applications such as image reject mixers
do not need true hybrids [34]. In fact, good voltage coupling is hard to achieve
65
especially in silicon-based technology at mm-wave. For tight coupling, either the gap
between the lines has to be narrow which requires a large Zo,even/Zo,odd ratio, as in a
coupled line coupler, or the lines are made narrow which exhibit more loss at coupled
port, as in a Lange coupler. These degrade the amplitude balance between the through
port (S21) and the coupled port (S31) that is required for good image rejection. In this
work, the mixed lumped-distributed-element power splitters offer alternatives to the true
distributed hybrid counterparts. The 180° and 90° power splitters are based on the
lumped-distributed Wilkinson divider with phase shifter at the outputs [12]. The lumped-
distributed Wilkinson divider was derived based upon the conventional lumped
Wilkinson divider with the inductors replaced by the distributed thin-film microstrip
transmission lines for lower loss and smaller process variations. Additional Π and Τ
phase adjusting networks are attached at the two output ports for corresponding phase
shifts [34]–[36].
LNA 0/180 0/90RFin
I
QA
PA0/1800/90 RFout
I
QB
Figure 4-1. Simplified block diagrams of single sideband (SSB) quadrature architecture.
A) Receiver. B) Transmitter.
66
4.2 Out-of-Phase Power Splitters Design
For analysis purposes, a lumped-distributed out-of-phase power splitter is
decomposed into an in-phase lumped-distributed Wilkinson power divider and two
phase shifters attached at the output ports.
4.2.1 Mixed Lumped-Distributed Wilkinson Power Divider
The conventional lumped Wilkinson power divider shown in Figure 4-2(a) uses
capacitors and inductors to mimic the quarter-wave transmission lines. However, at
mm-wave lumped spiral inductors exhibit higher loss than the distributed transmission
lines. Minimizing the loss is of particular importance especially at mm-wave when high
power gain from the LNA and high output power from the VCO are hard to obtain.
Therefore, on-chip microstrip transmission lines shown in Figure 4-2(b) are used to
realize all the lumped inductors because they are more resistant to process variations
and can be reliably and quickly modeled.
A B Figure 4-2. Block diagrams of Wilkinson power dividers. A) Lumped-element equivalent.
B) Lumped-distributed-element equivalent.
The component values LW, CW, and RW of the Wilkinson power divider can be
obtained via ABCD matrix [34]–[36] and are shown as follows:
67
0
0
2
2
f
ZLW
(4-1)
00 22
1
fZCW
(4-2)
02ZRW (4-3)
where02Z and 0f are the required characteristic impedance and center frequency for
quarterwave transmission lines in the divider, respectively.
4.2.2 П and Т Phase Shifters in 180o and 90o Power Splitters
The phase shifters of the 180° splitter consist of a high-pass filter and a low-pass
filter each generating either a positive or negative 90° phase difference. To synthesize
the low-pass and high-pass networks depicted in Figure 4-3(a) and 4-3(b), respectively,
(4-1) and (4-2) can be used with the term 2 Z0 replaced by Z0 [34], [35].
LRp
CRp CRp
A
CLT CLT
LLT
B
Figure 4-3. Unit Cells for generating ±90° and ±45° phase shifts. A) RHπ network. B) LHΤ network.
For the phase shifters in 90° splitter, the right-handed (RH) and left-handed (LH)
unit cells approach in Fig. 3 is introduced. The detailed analysis can be found in [34]–
[36] and are not discussed here. The closed-form design equations are treated in [34]
and are shown in (4-4)–(4-7). The RHπ and LHΤ networks are chosen for their compact
68
size and electrical characteristics. The component values of the phase shifters are
restricted by the condition (θRH - θLH) = 90°, resulting in a positive and negative 45°
phase shift in RHπ and LHT networks, respectively.
RHR f
ZL
sin2 0
0 (4-4)
RH
RHR fZ
C
sin
cos1
2
1
00
(4-5)
LHLT f
ZL
sin
1
2 0
0
(4-6)
LH
LHLT fZ
C
cos1
sin
2
1
00
(4-7)
It is observed that the ±90° phase shifters in the 180° splitter are the special case
of (4-4) – (4-7) when θRH = 90° = θLT. With the lumped-distributed Wilkinson power
divider described and the proper phase shifters, the out-of-phase power splitter is
synthesized and shown in Figure 4-4.
Port 1 Port 2
Port 3
TL1
TL2, LW TL3, LRp TL5
TL5
TL4,LLT
2CW
CW
CW
TL2, LW
CRp CRp
CLT CLT
RW
Figure 4-4. Mixed lumped-distributed-element out-of-phase power splitter.
69
4.3 Implementation and Experimental Results
The two power splitters were fabricated in SiGe BiCMOS 0.18 μm technology. The
back-end-of-the-line (BEOL) of the technology features six metal layers with aluminum
used as the thick top metal. The sub-100 pH inductors in both splitters are implemented
with thin-film microstrip transmission lines. All the lines are implemented with the top
metal (M6) as the signal line and the bottom metal (M1) as the ground plane. The
chosen implementation ensures the maximum SiO2 dielectric height to minimize the
conductor loss which is proportional to square root of frequency. The full ground plane
shielding has been adopted to isolate the conductive substrate and provide good
average ground potential. The short interconnects have been modeled and accounted
for. The spaces between the lines are more than four times the dielectric thickness to
avoid mutual couplings. All the capacitors used are MIM provided by the technology.
The chip photos of 180° and 90° power splitters are shown in Figure 4-5(a) and 4-
5(b), respectively. The overall dimensions of the core splitters are 240 μm x 440 μm and
220 μm x 400 μm, respectively. A two-port 110 GHz vector network analyzer (VNA) is
used to measure the two-port S-parameters with the other output port terminated with
an on-chip 50 Ω resistor. Therefore, two versions of each power splitter are required to
fully characterize the three-port networks. The measurement and simulation results of
the 180° and 90° power splitters are shown in Figure 4-6 and Figure 4-7, respectively.
For the 180° power splitter, the amplitude balance (A23) is better than 0.05 dB while the
phase difference (Φ23) is within 0.1° at 77 GHz. The input and output return losses are
better than 10 dB from 60 GHz to 100 GHz. Good amplitude balance within ±0.5 dB is
achieved from 66 GHz to 87 GHz and the phase difference is within ±2° from 70 GHz to
70
A
B Figure 4-5. Chip microphotograph of A) 180° power splitter. B) 90° power splitter.
84 GHz.
The 90° power splitter exhibits amplitude balance better than 0.25 dB at 77 GHz
and is within ±0.5 dB from 67 GHz to 110 GHz. The input and output return losses are
better than 10 dB from 60 GHz to 95 GHz. However, a ~5° phase error is observed at
77 GHz. The mismatch is primarily due to the small capacitor CRπ needed to synthesize
the RHπ network at output port 2. The post simulation has revealed that the parasitics
associated with the four series-connected capacitors used to realize CRπ have not been
properly modeled, therefore causing such deviation.
71
60 70 80 90 100-6
-5
-4
-3
S21
an
d S
31 (
dB
)
Frequency (GHz)
S21(meas.) S31(meas.) S21(sim.) S31(sim.)
A
40 50 60 70 80 90 100-40
-35
-30
-25
-20
-15
-10
-5
0
S11
, S22
, an
d S
33 (
dB
)
Frequency (GHz)
S11(meas.) S22(meas.)
S33(meas.)
S11(sim.)
S22(sim.) S33(sim)
B
Figure 4-6. Measured (symbols) and simulated (lines) A) Transmission. B) Reflection. C) Amplitude and phase difference of the 180° power splitter.
72
60 70 80 90 100155
160
165
170
175
180
185
190
195
200
-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.00.51.0
Am
pli
tud
e D
iffe
ren
ce (
dB
)
Ph
ase
Dif
fere
nce
(D
egre
e)
Frequency (GHz)
C Figure 4-6. Continued.
60 70 80 90 100-6
-5
-4
-3
S21
an
d S
31 (
dB
)
Frequency (GHz)
S21(meas.) S31(meas.) S21(sim.) S31(sim.)
A
Figure 4-7. Measured (symbols) and simulated (lines) A) Transmission. B) Reflection. C) Amplitude and phase difference of the 90° power splitter.
73
40 50 60 70 80 90 100-40
-35
-30
-25
-20
-15
-10
-5
0
S11
, S22
, an
d S
33 (
dB
)
Frequency (GHz)
S11(meas.)
S22(meas.)
S33(meas.) S11(sim.)
S22(sim.)
S33(sim.)
B
60 70 80 90 10075
80
85
90
95
100
105
110
-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.00.51.0
Ph
ase
Dif
fere
nce
(D
egre
e)
Frequency (GHz)
Am
plit
ud
e D
iffe
ren
ce (
dB
)
C
Figure 4-7. Continued.
74
To enhance the design robustness and flexibility, the phase deviation of the 90°
power splitter could be compensated by placing a MOS varactor in shunt with CRπ at
output port 2. Figure 4-8 shows the simulation results of the compensated 90° power
splitter with various DC biases. An improvement in the phase error can be seen in
Figure 4-8(c) when the varactor is DC biased at 0 V. The compensation technique adds
an additional degree of freedom to the design and also provides more resistance to
process variation and parasitic while not affecting the transmission and reflections.
Nevertheless, the phase difference is within ±2° from 64 GHz to 104 GHz before the
compensation. The performance of the 180°, 90°, and compensated 90° power splitters
are summarized in Table 4.1.
40 50 60 70 80 90 100-6
-5
-4
-3
S21
an
d S
31 (
dB
)
Frequency (GHz)
S21 VDC = 2V S21 VDC = 0 V S21 VDC = -2V S31 VDC = -2, 0, and 2V
A Figure 4-8. Simulated A) Transmission. B) Reflection. C) Amplitude and phase
difference of the compensated 90° powers splitter.
75
40 50 60 70 80 90 100-35
-30
-25
-20
-15
-10
-5
0
S11
, S22
, an
d S
33 (
dB
)
Frequency (GHz)
S11 VDC = 2V S11 VDC = 0V S11 VDC = -2V S22 VDC = 2V S22 VDC = 0V S22 VDC = -2V S33 VDC = -2, 0, and 2V
B
60 70 80 90 10085
90
95
100
105
110
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0VDC= -2V
VDC= 2V
VDC= 0V
Ph
ase
dif
fere
nce
(D
egre
e)
Frequency (GHz)
VDC= -2V
VDC= 0V
VDC= 2V
Am
plit
ud
e d
iffe
ren
ce (
dB
)
C
Figure 4-8. Continued.
76
Table 4-1. Performance summary of the three power splitters
77 GHz 180o Power Splitter
77 GHz 90o Power Splitter
77 GHz Compensated 90o Power Splitter
S21 [dB] -4.93 -4.15 -4.4
S 31 [dB] -4.88 -4.36 -4.4
Amplitude Error [dB] 0.05 0.21 0
Phase Error [o] 0.1 ~5 0.1
Bandwidth [GHz] 70 – 84 64 – 104 63 – 100 Φ23 180±2 85±2 90±2
*denotes simulation results with varactor biased at 0 V.
4.4 Chapter Summary
In this chapter, wideband mixed lumped-distributed-element 180° and 90° power
splitters were presented. Distributed thin-film microstrip transmission lines were used
instead of lumped inductors to reduce insertion loss and to combat process variations.
This approach offers alternatives to true hybrid designs for realizing the equal signal
power divisions and the necessary phase shifts in baluns and I/Q (de)modulators.
Improved port-to-port amplitude balance is demonstrated in the design where at
millimeter-wave good voltage coupling is hard to achieve in true hybrids. To the best of
author’s knowledge, this is the first millimeter-wave power splitters design with mixed
lumped-distributed techniques attempted in silicon-based technology
77
CHAPTER 5 HIGH GAIN DOUBLE-BALANCED ACTIVE FREQUENCY DOUBLER
5.1 Introduction
The design for high spectral purity, stability, and high power signal source at mm-
wave has always been difficult and crucial. In fact, as the design frequency increases, it
becomes more challenging to phase-lock the fundamental VCO and meet the stringent
phase noise and jitter requirement mainly due to the limited tank quality factor Qtank
(dominated by Q of the varactor), minimum noise figure (NFmin), and maximum
oscillation frequency (fmax) of the device technology.
Alternatively, integrated high frequency signal generation using a low and stable
frequency source or low frequency PLL synthesizer with a frequency doubler can relax
the performance specifications [37]–[39]. In addition, the power-speed tradeoff of the
fundamental VCO and pre-scaler can be significantly reduced, thus the overall system
power budget. Therefore, it is attractive to exploit a high power and high conversion
gain frequency doubler that can effectively operate at a high and over a wide range of
frequencies.
In this chapter, highlights of different doubler design approaches will first be
presented in Section 5.2. Section 5.3 addresses the frequency doubler design
techniques, optimizations, and tradeoffs. Experimental results and high frequency
measurement techniques are discussed in detail in Section 5.4.
5.2 Highlights of Frequency Doubler Design Approaches
The conventional active doublers based on the reflector approach use λ/4 and λ/2
transmission lines extensively at the fundamental and second harmonic (λ/4 at fo = λ/2
at 2fo) [40], [41]. This not only increases the chip size, but also limits the doubler
78
bandwidth. In addition, the required input power drive is high, typically0 dBm. The
fundamental suppression is also degraded due to the bandwidth of the high Q bandpass
filter. Besides, the losses incurred by the long transmission lines together with the single
active device usually give conversion losses and low output powers at mm-wave [42].
To further increase the output bandwidth, frequency diplexer which consists of a
bandpass filter (BPF) and a bandstop filter (BSF) may be employed at the doubler
output [43]. Although this technique has been validated for bandwidth extension, it has
been rendered impractical because the required filters even at 2fo will occupy
tremendous real estate. The length of a quarter-wave transformer is ~600 μm at 60 GHz
in today’s state-of-the-art SiGe BiCMOS technology. The overall stability of the single
device across the bandwidth is also difficult to maintain, and generally resistive
terminations or shunt RC networks are needed especially for LF stability. More
importantly, fully differential interface with the preceding and following differential stages
is only possible with additional combiners and/or baluns, making such approach
unattractive.
Harmonic generations using diode circuits are also widely employed at microwave
frequencies. Reactive doublers based on varactors or step-recovery diodes (SRDs) that
make use of the diode’s non-linear junction capacitance often exhibit good conversion
efficiency (theoretically 100% according to Manley-Rowe relations [44]) and low noise
performance. However, such doublers are notoriously unstable, sensitive to slight
mistuning, and inherently narrowband [45]. Resistive frequency doublers generating full-
wave-rectified sine wave from quad diodes (typically Schottky-barrier diodes) have
demonstrated wide usable bandwidth and reasonable fundamental rejections [46], [47].
79
However, they suffer greatly from the conversion loss (typically from -12 to -15 dB)
owing to the large series resistance. Larger size diodes can be used to improve the
performance at the expense of the parasitic which limits the high frequency response. It
has also been shown quantitatively and experimentally that the resistive frequency
doubler is less efficient compared with its reactive counterpart and the maximum
conversion efficiency is typically less than 25%. Therefore the drawbacks of the passive
doubler can be summarized by its high conversion loss, mediocre output power, and
high input power drive, typically 10 dBm. The availability of broadband baluns is also
necessary to provide fully differential operation across the bandwidth. Moreover, special
devices like Schottky-barrier diodes (SBDs) may not be available in the standard
process; the added options further increase the manufacturing costs.
In this chapter, the double-balanced active frequency doubler based on Gilbert cell
design was chosen for its fully differential signaling, high gain, high output power, and
wide bandwidth. The heterojunction bipolar transistors (HBTs) have been considered as
the most suited technology of choice for this topology due to their superior
transconductance (gm) when compared with today’s 65 nm or 45 nm CMOS transistors
counterpart.
5.3 Active Frequency Doubler Design
5.3.1 Circuit Architecture
The schematic of the double-balanced active frequency doubler is shown in Figure
5-1. The frequency doubler design is based on the Gilbert cell multiplier which operates
by injecting identical signals to both input ports. The non-linear signal current from the
transconductor (M9–M10) is modulated by the switching transistor quad (M5–M8),
which operates as commutating analog switches. The frequency doubler generates a
80
IN
VCC
+
- +
-OUT
Vbias
Input Buffers Doubler Core Output Buffers
M1 M2 M3 M4 M5 M6 M7 M8
M9 M10
M11 M12
TL1 TL2
R1 R2
R3 R4 R5 R6
R7
R8 R9
Figure 5-1. Schematic of the double-balanced active frequency doubler.
DC term and a second harmonic of the input signal due to the non-linear characteristics
of the switching transistor quad. This desired non-linearity comes from the switching
action of the transistor quad which is defined by the non-linear exponential
characteristics of the devices. In cases when the signal current is not fully steered from
one branch to another due to imperfect switching, a portion of the signal will flow to
base-emitter capacitance Cbe and base resistance rb for charging and discharging,
which gives rise to undesired non-linearity. It is worth noting that the desired second
harmonic are attributed to the mixing effects (N x M). The conversion gain of the circuit
is to first order determined by the constructive and destructive interference of the mixing
terms. Therefore, it is imperative that the number of harmonics be set sufficiently large
to ensure accuracy in Harmonic Balance simulation.
81
The resonant loads, formed by the transmission line inductors along with the
capacitances from the devices are tuned to pick up the second harmonic while filtering
out the undesired spurs. The input double emitter followers (M1–M4) are used to
present low impedance to drive the two input ports and provide DC level-shift and
broadband matching. The output stage emitter followers (M11–M12) serving as buffers
are used to isolate the doubler core from the 50 Ω load and provides output matching.
No output amplifier is added after the output emitter followers for this wideband design
due to the higher generation of unwanted harmonics, resulting in degraded fundamental
rejection.
5.3.2 Stability
The stability issue remains to be one of the main challenges especially in an
active frequency doubler design. Thus, it is worthwhile to revisit some of the
fundamentals to gain an intuitive insight. Heuristically, emitter followers are well-known
for isolation, wideband matching, and are popularly used for DC level shift in many high
speed circuit designs. However, the on-chip ringing behavior and undamped oscillation
could render unpleasant surprise if multiple cascaded EFs are used [48]. The reasons
can be explained by the following two scenarios. Figure 5-2 (a) and (b) show sources of
instability due to capacitive loading and inductive output impedance, respectively. From
Figure 5-2 (a), it is observed that when the output of M1 is loaded capacitively by Cbe of
M2, the input impedance Zin contains a negative resistance which can be first-order
approximated by –gm/ 02CBE1(CCS+CBE2). It is obvious that a larger device size provides
better current driving capability. However, the increased capacitance associated with
M2 along with the parasitic inductance from the interconnects can form a parasitic
82
Colpitts oscillator. Furthermore, from Figure 5-2 (b), the output impedance Zout of the M1
could appear inductive over a range of frequency if 1/gm1 < Rs + rb. This could cause
resonance with the capacitor of the following stage or an unmatched transmission line
to Cpad and 50 Ω load [49]. However, with proper selection of the devices’ quiescent
points, dimensions, and length of interconnects; the problem of potential instability can
be resolved.
M1
CBE1
Lpara
Lpara
M2CBE2
CCS
VCC
GND
-R + jX
Lpara
M1CBE1
Lpara
GND
CBE2 + CCS
VCC
Parasitic
OscillatorColpitts
CSCS
A
M1
GND
VCC
CBE1
rb
Cpad 50O
Zo , l
CparaCS
IC1
Rs + jXsTline Interconnect
Inductive if 1/gm1 < Rs + rb
output
B
Figure 5-2. Sources of instability in emitter followers due to A) Capacitive loading. B) Inductive output impedance.
83
5.3.3 Design for Speed, Conversion Gain, and Output Power
All the devices in the active frequency doubler are optimized for the RF
performance up to 80 GHz due to the measurement limitation. To achieve good driving
capability, the double emitter followers at the input should be sized to accommodate the
large DC current for large gm. This is useful to avoid signal loss from the LO to the first
EF (M1–M2) and second (M3–M4) EF pairs. It also helps to minimize the impact on the
switching time of the transistor quad. In order to increase the switching speed of the
transistor quad and achieve high conversion gain, small transistor quad devices should
be used to reduce the base-emitter capacitance Cbe, base-collector capacitance Cbc,
and the associated parasitic capacitance. At mm-wave, employing large devices could
cause signal to leak via the parasitic. However, small devices tend to incur more rb
which could potentially increase the charge and discharge time constant. In addition,
since the collector current is proportional to the emitter area, small devices could also
result in incomplete switching for current steering, which degrades the conversion gain.
A reasonable compromise therefore must be made to achieve the optimal RF
performance. In this design, the device configuration CBEBC was chosen for the
transistor quad to reduce rb despite with a slight increase in Cbc. It can be seen from
Chapter 2 that this configuration achieves the highest fT. Nevertheless, the fT of the
transistor quad is set to at least twice the maximum operating frequency to guarantee
fast switching. The output stage emitter followers are sized for and biased at high fT and
fmax for output power while maintaining good output matching to the load. A transmission
line inductor of 60 pH was chosen as the load to boost the conversion gain at the
second harmonic and optimize the output frequency response.
84
5.3.4 Layout Design
The back-end-of-the-line (BEOL) of the SiGe BiCMOS technology provides six
metal layers. The 60 pH inductive loads in the frequency doubler were synthesized with
thin-film microstrip transmission lines. The top metal is used as signal line and the
bottom metal is used as ground plane to minimize the conductor loss. The full ground
plane shielding has been adopted to isolate the conductive substrate and provide good
average ground potential [12]. The symmetry of the frequency doubler layout is highly
desirable and emphasized for common-mode noise rejection. The lengths of the
interconnects are kept as short as possible to avoid additional signal loss. The
dimensions of the input and output transmission lines are chosen for impedance
matching. Note that a careful optimization of the matched output transmission line is
needed to avoid ringing or resonance.
5.4 Experimental Results
The microphotograph of the double-balanced active frequency doubler is shown in
Figure 5-3. The dimension of the chip including the pads is 640 μm x 425 μm (0.272
mm2). The on-wafer measurement setup consists of two parts: (1) output frequency Fout
< 50 GHz and (2) output frequency Fout from 50–80 GHz. First, the losses due to
cabling and probe tips were corrected by measuring from the input cable, 180° hybrid
junction, input probe (GSSG), thru-substrate, and output probe (GSSG) with a
synthesized sweeper (Agilent/HP 83650A), power meter (Anritsu ML 2437A) and 50
GHz power sensor (Anritsu MA 2445A). Next the output cable loss was considered
alone by feeding the power from the sweeper and measuring the output power with a 50
GHz spectrum analyzer (Agilent E4448A) and/or 50 GHz power sensor.The same
measurement was repeated for verification using Anritsu vector signal generator
85
(E8267D). Since the losses at the fundamental and second harmonic are different at
both input and output, the two-step calibration method ensures accurate extraction of
the loss due to cabling and probes at the fundamental and 2nd harmonic, respectively.
Figure 5-3. Microphotograph of the double-balanced active frequency doubler.
Synthesized Sweeper
or Vector Signal
Generator
1800 Hybrid
GSSG
DUT
P G P
Spectrum Analyzer
GSGSG
A
Figure 5-4. On-wafer measurement setup for A) Fout ≤ 50 GHz. B) 50 GHz ≤ Fout ≤ 80 GHz.
RFin
RFout
Bias
86
Synthesized Sweeper
or Vector Signal
Generator
1800 Hybrid
GSSG
DUT
P G P
GSG
WR-15WR-10
V-Band or W-Band
Power Sensor
HP Power Meter
B
Figure 5-4. Continued.
30 40 50 60 70 80 90-5
0
5
10
15
Co
nve
rsio
n G
ain
(d
B)
Output Frequency (GHz)
-9 dBm -8 dBm (Single) -8 dBm (Differential)
Figure 5-5. Measured conversion gain at input powers of -9 dBm and -8 dBm.
87
Figure 5-4 (a) shows the measurement setup for Fout ≤ 50 GHz. The measurement
was conducted with the Anritsu vector signal generator (E8267D), 10–40 GHz 180°
hybrid junction (HY1040-180), differential GSSG input probe, and differential GSGSG
output probes. Single-ended output is connected to the spectrum analyzer (PSA E4448)
while the complementary output is terminated with 50 Ω. Figure 5-4 (b) shows the
measurement setup for 50 GHz ≤ Fout ≤ 80 GHz. The measurement was conducted with
the Anritsu vector signal generator (E8267D), 10–40 GHz 180° hybrid junction
(HY1040-180), differential GSSG probe, WR-10 or WR-15 GSG waveguide probes and
V-band (V8486A) or W-band (W8486A) power sensors connected to the power meter.
Note that the waveguide probes are single-ended and the complementary output is left
unconnected. To minimize the measurement uncertainty, a W-band differential GSGSG
(Beryllium-Copper) with second output terminated with 50 Ω is used to repeat the
measurement from 74–88 GHz. Nevertheless, an additional 3 dB is accounted for
single-ended to differential operation. Figure 5-5 depicts the measured conversion gain
for input powers of -8 dBm (either single-ended or differential probes at output) and -9
dBm. The optimal input power levels to maximize conversion gain at lower frequency
band and higher frequency band are slightly different. Therefore -9 dBm and -8 dBm are
used for output frequencies below and above 50 GHz, respectively. The peak
conversion gain is 10.2 dB at 66 GHz at -8 dBm input power and is better than 0 dB
from 36–80 GHz. The conversion gain of 0.83 dB is observed at 80 GHz for an input
power of -8 dBm with single-ended measurement. An increase in the conversion gain to
2.34 dB is observed when the W-band InP differential probe is used. Therefore the
actual performance of the frequency doubler is better when the complementary port is
88
30 40 50 60 70 80 9010
15
20
25
30
35
40
Fu
nd
amen
tal S
up
pre
ssio
n (
dB
)
Output Frequency (GHz)
Figure 5-6. Measured fundamental suppression.
Figure 5-7. Output spectrum of the active frequency doubler at 50 GHz output frequency (not corrected for the losses).
89
properly terminated. Note that due to the amplitude (±1.2 dB) and phase imbalance
(±12°) of the 10–40 GHz 180° hybrid junction, the measurement beyond 80 GHz should
be corrected.
In order to obtain the fundamental suppression beyond 50 GHz, the output power
at the second harmonic was measured with the V-band and W-band power sensor while
the power at the fundamental was displayed with spectrum analyzer. Figure 5-6 shows
the fundamental suppression versus output frequency. It is seen that the maximum
fundamental suppression of 36 dB is achieved at 60 GHz and is better than 20 dB from
36–80 GHz. Figure 5-7 shows the output spectrum of the doubler at 50 GHz with
fundamental suppression of 30.5 dB when the input power is -9 dBm. The measured
output power versus input power at 3.3 V and 4.0 V supply voltages are shown in Figure
5-8. The maximum output power of 1.7 dBm is observed at 66 GHz with 3.3 V supply at
input power of -7 dBm. The maximum output powers of -3.9 dBm at 3.3 V supply and
-2.4 dBm at 4 V supply at 80 GHz are both achieved with input power of 1 dBm. The
doubler draws 41.6 mA from a nominal 3.3 V supply. The accuracy of the frequency
doubler measurement is estimated to be within ± 1 dB for Fout ≤ 80 GHz.
5.5 Chapter Summary
In this chapter, a high conversion gain double-balanced active frequency doubler
operating from 36 to at least 80 GHz (performance limited by 10–40 GHz 180o hybrid at
input in measurement) is validated and demonstrated. The doubler has achieved a
maximum conversion gain of 10.2 dB at 66 GHz and 0.83 dB at 80 GHz using single-
ended measurement. The maximum output power at 80 GHz is -3.9 dBm at 3.3 V
supply and -2.4 dBm at 4 V supply. The fundamental suppression is better than 20 dB
across the operable output bandwidth. The doubler draws 41.6 mA from a nominal
90
-25 -20 -15 -10 -5 0 5-25
-20
-15
-10
-5
0
5
Ou
tpu
t P
ow
er (
dB
m)
Input Power (dBm)
50 GHz 60 GHz 66 GHz 70 GHz 74 GHz 80 GHz
A
-25 -20 -15 -10 -5 0 5
-25
-20
-15
-10
-5
0
5
Ou
tpu
t P
ow
er (
dB
m)
Input Power (dBm)
50 GHz 60 GHz 80 GHz
B
Figure 5-8. Measured output power versus input power for different output frequencies at A) 3.3 V supply. B) 4.0 V supply.
91
Table 5-1. Performance of prior published frequency doublers
Ref Technology fT/fmax (GHz)
Type Topology Input Output
Operable Output BW (GHz)
Output Frequency (GHz)
Peak Conv. Gain (dB)
Fundamental Suppression (dB)
Max. Pout (dBm)
Pdiss (mW) @ VDC
[46] HBT N.A.
Passive Differential Differential
14 – 40 N.A. -12 >20 2 0
[47] 0.18 μm CMOS N.A.
Passive Differential Differential
25 – 75 38 -11 ~ -15.5 32 – 59 3 0
[42] 90 nm CMOS 140/100
Active Single Single
50 – 69 60 -15.3 ~18 N.A. 4@1
[50] 90 nm CMOS 140/160
Active Single Single
26.5 – 28.5
27 1.5 >11.2 ~-1.5 [email protected]
[51] 0.4 μm SiGe HBT 85/128
Active Differential Differential
18 – 42* 30 5.6 22 0 185@5
[52] 0.5 μm SiGe HBT 80/90
Active Differential Differential
N.A. 14 17 30 -1 [email protected]
[53] 0.8 μm SiGe HBT 80/N.A.
Active Differential Single
34.6 – 37.6
36 3 – 4.5 35 9 – 10.5 95 – 114 @4
[55]
0.12 μm AlGaAs/InGaAs pHEMT 110/>200
Active Single Single
N.A. 76.5 1 30 9 N.A.
[56] 0.15 μm GaAs HEMT 95/N.A.
Active Single Single
48 – 60 60 4 30 9 275@3
[57] 0.2 μm InP HBT 180/220
Active Differential Single
DC – 100 60 1 30 -10 [email protected]
This work [54]
0.18 μm SiGe BiCMOS 200/200
Active Differential Differential
36 – 80* 66 80
10.2 0.83
33 20
1.7 -3.9
*denotes the operable output BW defined as the frequency range in which the conversion gain is larger than 0 dB.
3.3 V supply. Table 5.1 summarizes the performance of prior published frequency
doublers. The double balanced active frequency doubler in this work [54] has, to the
best of author’s knowledge, achieved the highest conversion gains and output powers
at operating frequencies of 66 GHz and 80 GHz among all other silicon-based
technologies reported up to date. The performance of this frequency doubler is also
comparable with some of the state-of-the-art active frequency doublers implemented in
III-V semiconductor technologies such as Gallium Arsenide (GaAs) [55], [56] and Indium
Phosphide (InP) [57] as shown in Table 5.1.
92
CHAPTER 6 HIGHLY LINEAR DOUBLE-BALANCED ACTIVE UP-CONVERSION MIXERS
6.1 Introduction
The rapid emergence of advanced silicon-based semiconductor devices with
excellent RF characteristics have initiated many research works in 71–76 GHz and 81–
86 GHz high-data-rate millimeter-wave radios, 76–77 GHz long and 77–81 GHz short
range automotive radars. These state-of-the-art technologies present an unprecedented
opportunity to realize millimeter-wave systems with high level of integration, high
reliability, and low manufacturing cost. In modern wireless transmitter designs where
up-conversion is inevitable, a mixer is usually required to convert signals from baseband
to RF. Several V-band active up-conversion mixers based on the conventional Gilbert
multiplier design [58]–[61] and Micromixer [62] with improved LO rejection and
conversion gain were reported. Active mixers using dual-gate topology [63]
at K-band and series-connected triplet [64] at Ka-band have been demonstrated. A
V-band passive mixer design in attempt to improve the linearity at the expense of high
LO drive was also reported [65]. These up-conversion mixers, when used in a direct
conversion transmitter, have aimed to achieve high LO rejection and low required LO
power while maintaining an acceptable conversion gain. Particularly, special emphasis
is laid on mixer linearity characterized by OP1dB and output-referred third-order intercept
point (OIP3) to reduce the intermodulation products that in turn produce adjacent and
alternate channel leakages. More critically for a millimeter-wave system, the
requirement for gain or driver stages for expensive power amplification can be relaxed.
So far, however, no progress on W-band up-conversion mixer has yet been reported.
93
In this chapter, a W-band double-balanced active up-conversion mixer based on a
well-established multi-tanh triplet linearization principle [66] is implemented to
demonstrate high OP1dB with conversion gain. Besides, we also address the technical
challenges faced in the high frequency characterization [67].
6.2 Up-Conversion Mixer Design
A linearization technique based on multi-tanh employs N differential pairs in
parallel in which an input voltage offset is intentionally introduced to each pair according
to the mismatched transistor ratio and bias current. By superimposing the distinct
nonlinear transconductance characteristics contributed by the individual differential pair,
it is possible to extend the linear range of a transconductance stage by maintaining a
maximally flat Gm response over an input voltage range.
The block diagram of the double-balanced active up-conversion mixer is shown in
Figure 6-1(a). The mixer core consists of a Gilbert switching transistor quad, multi-tanh
triplet (N=3) transconductance stage, and inductive loads. The output buffers are
included to provide the isolation and impedance matching before balanced-to-
unbalanced conversion. In addition, to complete the mixer operation, an integrated 80
GHz active frequency doubler [57] with a LO buffer are incorporated to drive the LO port
and an on-chip balun [12] is used to combine the up-converted RF outputs. Figure 6-1(b)
shows the circuit schematic of the multi-tanh triplet transconductance stage, which is
composed of three asymmetric differential pairs. The linearity performance of the multi-
tanh triplet transconductance stage is determined by the number of differential pairs (N)
employed, transistor ratio (A) between the outer devices M1 to the inner devices M2,
and the bias current ratio (K) between I1 and I2. The choice of these two design
parameters A and K involves trade-offs among the conversion gain, layout complexity,
94
and flatness in the overall Gm, which plays a major role in the linearity of the mixer. In
addition, to achieve high OP1dB at mixer output to drive the driver amplifier, the up-
conversion mixer typically has to be designed to give more than marginal conversion
gain at millimeter-wave frequency. Taking these design metrics into consideration, an
iterative optimization is performed to determine the transistor ratio A and current ratio K
to be 8 and 3/4, respectively. The transistor ratio A in the triplet design is realized by
sizing the total emitter area (AE) of M1 with respect to M2. The current ratio K can be
accomplished easily with different emitter degeneration resistors in the current sources.
Next, to minimize the unwanted nonlinear effects from the switching quad which would
otherwise impact on the overall linearity of the mixer, the emitter length (LE) of the
transistor quad is chosen to be 2.5 μm and is biased at peak fT to achieve fast switching.
The device layout configuration CBEBC for the best RF performance along with the
chosen switch device geometry not only helps improve LO suppression, conversion
gain, and output power but also eases the local oscillator (LO) design at high frequency,
thereby reducing the overall power consumption.
6.3 Experimental Results
The up-conversion mixer was fabricated in a low-cost 200 GHz fT and fmax JAZZ
0.18 μm SiGe BiCMOS process. Thin-film microstrip transmission lines with full ground
plane shielding are adopted to maintain good continuous ground potential [12]. The
microphotograph of the fabricated mixer is shown in Figure 6-2. The dimension of the
chip, including the pads, is 820 μm x 810 μm (0.664 mm2). The on-wafer measurement
setup is shown in Figure 6-3. The LO signal is generated with the Agilent vector signal
generator (E8267D) and external 10–40 GHz 180o hybrid junction (HY1040–180). The
on-chip frequency doubler and LO buffer provide adequate LO power up to around 80
95
VCC
TL1 TL2
On Chip Balun RFout
LOBuffer
Gilbert Switching Quad
X2
Multi-TanhGm Stage
LOin+-
+ -IFin
Iout+ Iout-
Output Buffers
A
M1 M2
R1
IFin+
VIF
M2 M2 M2 M1 IFin-
VIF
R2
GND
I1 I2 I1
Iout-
B
Figure 6-1. A) Block diagram of the double-balanced active up-conversion mixer. B) Circuit schematic of the multi-tanh triplet (N=3) transconductance stage.
96
Figure 6-2. Microphotograph of the active up-conversion mixer.
GSSG
GSG
WR-15or
WR-10
E4448 Spectrum Analyzer
Downconverted RFout
HP 83650BSynthesized Sweeper
180o Hybrid
180o Splitter
Agilent E8267DVector Signal
Generator
IF
LO RF
DC
DC
HP 83650ASynthesized SweeperDGSSGD
DDDD
HY1040-18010-40 GHz
ZFSCJ-2-4+
X4 or X6
V-band/W-band Mixer
Composite
Figure 6-3. Measurement setup for active up-conversion mixer.
IF+
DC Bias
LOin+
RF Balun
IF-
X2 and Buffer
Mixer Core
LOin-
97
GHz. The IF signal is generated by the synthesized sweeper (HP 83650A) and
converted from single-ended to differential using the 50–1000 MHz 180o power splitter
(ZFSCJ-2-4+). Due to the limitation of the spectrum analyzer (PSA E4448), the up-
converted RF output is fed to the external V/W-band down-converter which is driven by
the multiplier (X4/X6) and synthesized sweeper (HP 83650B). The losses due to the
input/output probes, cables, and external V/W-band down-converter modules are
calibrated. To account for the different conversion losses of the external down-converter
modules at upper sideband (USB) and lower sideband (LSB), a small IF frequency of 10
MHz is used to keep the output powers of the two sidebands nearly identical.
The measured SSB power conversion gain is 5.1 dB and 3.8 dB at 77 GHz and 80
GHz, respectively as shown in Figure 6-4. The calibrated LO drive level at the on-chip
frequency doubler input is between -8.5 dBm to -4.2 dBm from 70 to 82 GHz. The LO to
RF isolation is better than 20 dB from 70 to 84 GHz and is limited by the off-chip
measurement setup which includes the 10–40 GHz 180o hybrid junction, 180o power
splitter at IF input, and cables. The actual LO rejection should be better. Figure 6-5
shows the measured OP1dB is -4.2 dBm at 77 GHz and -5.8 dBm at 80 GHz. Note that
the measurement results beyond 80 GHz are limited by the 10–40 GHz 180o hybrid
junction and available LO drive. The active up-conversion mixer including the output
buffer draws 32.5 mA from a nominal 3.3 V supply while it dissipates a total DC power
of 365 mW including the on-chip LO generation.
6.4 Chapter Summary
In this chapter, a W-band highly linear double-balanced active up-conversion
mixer implemented in a low-cost 0.18 μm SiGe BiCMOS technology was presented. By
applying multi-tanh triplet technique, the up-conversion mixer has achieved high OP1dB
98
70 72 74 76 78 80 82 84 86-6
-4
-2
0
2
4
6
8
10
5
10
15
20
25
Conversion Gain
LO
to
RF
Is
ola
tio
n (
dB
)
SS
B C
on
vers
ion
Gai
n (
dB
)
RF Output Frequency (GHz)
Limited by LO drive Rejection
Figure 6-4. Measured SSB conversion gain and LO to RF isolation.
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2-6
-4
-2
0
2
4
6
-16
-14
-12
-10
-8
-6
-4
-2
0
77 GHz 80 GHz
RF
Po
ut
(dB
m)
SS
B C
on
vers
ion
Gai
n (
dB
)
Baseband Pin (dBm)
Figure 6-5. Measured mixer linearity characteristics at 77 GHz and 80 GHz.
99
Table 6-1. Performance of prior published silicon-based up-conversion mixers
Ref Technology fT/fmax (GHz)
Type Topology IF Input RF Output
On-Chip Balun LO/RF
Output Frequency (GHz)
Conversion Gain (dB)
LO to RF Isolation (dB)
OP1dB (dBm)
Pdiss (mW) @ VDC
[65] 65 nm CMOS N.A./N.A.
Passive Differential Single
Yes/No 60 -13.5 34 -19 0
[63] 130 nm CMOS N.A./N.A.
Active Differential Differential
No/No 18–28 -2 ~ -0.7 30 -7 ~ -5.2 [email protected]
[64] 0.18 μm SiGe BiCMOS 150/180
Active Differential Differential
No/No 28 1.2 ~20 -5.6 [email protected]
[58] 90 nm CMOS 150/N.A.
Active Differential Differential
Yes/Yes 51 -11 26.5 -10 [email protected]
[59] 130 nm CMOS 90/140
Active Differential Differential
No/No 59–65 -0.7 ~ 4 37 -5.6a [email protected]
[60] 0.18 μm SiGe BiCMOS 120/130
Active Differential Differential
Yes/Yes 35–65 -7±1.5 40 -16b 14@4
[61] 65 nm CMOS 230/N.A.
Active Differential Differential
No/No 60 -6.5 30c -5 [email protected]
[62] 0.25 μm SiGe HBT 200/200
Active Single Differential
Yes/Yes 60 -6.5 33 -6 82.5 @3.3
This work [67]
0.18 μm SiGe BiCMOS 200/200
Active Differential Differential
Yes/Yes 77 80
5.1 3.8
21.7 21.1
-4.2 -5.8
adenotes double sideband (DSB) output power. bdenotes measurement result at RF=41 GHz. cdenotes measurement result at 50 GHz. ddenotes Pdiss of the mixer including output buffers. of -4.2 dBm and -5.8 dBm at 77 GHz and 80 GHz, respectively. The mixer has achieved
SSB power conversion gain of 5.1 dB at 77 GHz and 3.8 dB at 80 GHz. To the best of
author’s knowledge, this is the first W-band active up-conversion mixer based on multi-
tanh triplet that has demonstrated the highest characterized operating frequency and
shown better OP1dB performance compared to the prior published silicon-based up-
conversion mixers reported to date as shown in Table 6-1.
100
CHAPTER 7 INTEGRTATED WIDEBAND LINEAR RECEIVER
7.1 Introduction
Until recently, low-cost millimeter-wave (mm-wave) integrated radio systems are
emerging thanks to the rapid evolution of advanced SiGe and CMOS technologies. In
particular, SiGe technology has been identified as a well-suited technology for both
active and passive imaging applications such as high-resolution automotive radars and
concealed weapon detections due largely to its superior performance in gain, NF, output
power, phase noise, and variability over temperature compared even with today’s
CMOS. To further maintain the low production cost advantage, efficient technology
sharing suggests the key components should be universal. Therefore, it is an attractive
effort to integrate multiple standards that include lower E-band 71–76 GHz high speed
point-to-point links, 76–77 GHz long-range and 77–81 GHz short-range automotive
radars into a single chip. Moreover, high dynamic range performance is essential as
these systems are required to operate under all-weather conditions. To date, numerous
research efforts have been undertaken to realize SiGe HBT/BiCMOS automotive
phased array radar [68], [69], radar transceivers [70], [71], individual receivers [72]–[76]
and down-converter [77] at ~77 GHz. However, no integrated receiver front-end
addressing the complete 71–81 GHz band has been reported.
In this paper, we present the first fully integrated, universal, wideband, and linear
receiver covering the entire 71–81 GHz band that can be used in a direct-conversion
zero-IF or low-IF architecture. The simplified block diagram of the wideband receiver
with on-chip active frequency doubler is shown in Figure 7-1.
101
Balun
Ext. LO
RFin IF+IF-
X2 Buffer
LNA
On-Chip
IFAmp
Int. LO
Figure 7-1. Simplified block diagram of the wideband receiver with on-chip active
frequency doubler.
7.2 Circuit Blocks Design
The architecture chosen for the low-noise amplifier (LNA) and mixer combination
is crucial in determining the overall RF bandwidth of the receiver front-end. Between
these two important building blocks, the mixer generally gives better bandwidth
performance; therefore optimizing the LNA design becomes the remaining key option to
simultaneously achieve the wideband operation and low noise upon integration.
7.2.1 Low-Noise Amplifier
The schematic of the two-stage LNA is shown in Figure 7-2. The amplifier has an
input cascode stage for higher power gain and better isolation at the expense of higher
NFmin. Common emitter was used for the second stage for improved linearity and wider
output matching bandwidth. Device layout configurations with two base fingers (CBEBC)
were used throughout the LNA design to mitigate the signal loss via device parasitic
capacitance (CBC and CBE) to ground, thereby improving the overall power gain and NF.
Wideband noise input matching technique with low quality factor Q network (~1.3 after
optimization) was employed to achieve high linearity and enhance robustness to PVT
simultaneously. Inductive degeneration at the second stage further improves the
102
linearity of the overall LNA. A standalone version of the LNA has also been
characterized and has a measured peak S21 of 14.5 dB and NF of 6.9 dB at 77 GHz
with a 3 dB bandwidth spanning from 69 to 83.5 GHz [26]. The measured NF is lower
than 8.4 dB from 64 to 84 GHz while the measured input-referred 1 dB compression
point (IP1dB) is -11.4 dBm at 77 GHz. Note the output matching of the standalone LNA
has been modified slightly to facilitate the integration of the receiver front-end.
TL6
TL7
C2
VCC2
Bias2
R3
C5
M2
M1
TL3
TL4
TL2
TL1RFin
C1
R1
VCC1
Bias1
M3
TL5
C6R2
C3
C4
Feed
Vcas1
RFout
Feed
Figure 7-2. Circuit schematic of the 77 GHz two-stage LNA [26].
7.2.2 Down-Conversion Mixer and Integrated Passive Balun
The schematic of the standalone mixer shown in Figure 8-3 consists of two
integrated wideband passive baluns at LO and RF port, a mixer core, emitter followers,
and an IF amplifier. The passive balun features an insertion loss of 1.5–2.2 dB,
amplitude imbalance of <0.27 dB, phase imbalance 180o±2o from 70–84 GHz, and port
return losses better than 10 dB from 60–90 GHz, as reported in [12]. The mixer core
103
RFin
VCC
Vbias
Down-Conversion Mixer Core IF Buffers
M1 M2 M3 M4
M5 M6
M7 M8
TL1
R2
R7
R8 R9
R1
On Chip Balun
VLO
LOin
VRF
R3 R4
On Chip Balun
TL3 TL4
+
-IFOUT
M9 M10
R11
R14
TL2
R5 R6
R10
R12 R13
IF Amplifier
Figure 7-3. Circuit schematic of the standalone down-conversion mixer.
design is based on the Gilbert cell for double-balanced structure for broadband
performance. The selection of the device sizes involves trade-offs among conversion
gain, NF, and linearity. In fact, linearity of the receiver front-end is primarily determined
by the performance of the mixer. There are three main factors to consider for linearity
design. First, large DC bias current therefore large gm is usually required from
transconductor (gm) stage to reduce the noise and the 3rd order intermodulation product
(IM3). However, considering the fmax of the technology and Gmax at operating frequency
range, device sizes cannot be made arbitrarily large so that the gain of the gm stage can
be conserved. Second, small device geometry (CEBEC) which presents the highest fT in
this technology was chosen for fast switching quad. This configuration reduces the
charging and discharging times for complete current steering, thereby reducing the
mixer quad’s contribution to the overall nonlinearity. Moreover, it also relaxes the
104
required LO drive and reduce the overall system power budget. Additionally, for a small
size device the required DC bias current to achieve peak fT is smaller, this allows lower
current noise arising from the switching quad. Note however that this goes against the
large bias current for gm stage necessary for linearity and NF. As an additional benefit,
power conversion gain and LO-to-IF isolation can be improved. During current steering,
the peaking transmission line inductors TL1 and TL2 (60 pH) inserted between CE and
CB stage resonate out the parasitic capacitance associated with collector node of gm
stage (M5 & M6 with emitter length = 7 μm) and emitter node of switching quad (M1–M4
with emitter length = 2.5 μm), thus improving mixer’s power gain, NF, isolation, and
bandwidth all at once. The emitter length of M5 and M6 are intentionally scaled more
than twice the size of M1–M4 such that the gm stage can be biased at the optimal
current density for high linearity while the switching quad is biased close to peak fT. The
selection shows excellent linearity with minimal performance degradation in gain and
NF, with nominal 3.3 V supply. Inductive degeneration transmission lines (TL3 & TL4,
25pH each) further improve the design bandwidth and linearity. The mixer resistive
loads (R5 & R6) are 240 Ω, optimized for conversion gain while satisfying the low-
voltage headroom requirement. Third, in order to interface with the 50 Ω testing
environment and provide adequate gain and output drive to the following circuitry, an IF
buffer amplifier is usually unavoidable after the mixer core. The IF differential amplifier
core comprises large size devices (M9 & M10 with emitter length = 2 x 6 μm) along with
a pair of degeneration resistors (R12 & R13, 27Ω each) to increase the overall linearity.
A major part of the current drained in the mixer design comes from the IF amplifier in
which the individual device has a current density of 6.5 mA/μm2. Two 75 Ω resistors
105
R10 and R11 are used as IF loads for output matching. As a final note, linearity
performance (IP1dB) is usually better without an IF amplifier. The mixer draws a total
current of 36 mA.
7.2.3 Internal LO Generation
The internal LO signal is generated by an on-chip active by an on-chip active
frequency doubler with a power output buffer to relax fundamental signal source phase
noise requirement. The frequency doubler based on Gilbert cell was chosen for its fully
balanced operation, high conversion gain, high output power, and wide bandwidth. The
doubler highlights a wide operable bandwidth from 36–80 GHz with gain and Pout of 0.8
dB and -3.9 dBm, respectively, at 80 GHz. More design insights are available in [57]. A
power output buffer consisting of a differential cascode stage was added to further
increase the output power of the doubler and ensure fast switching of the mixer quad as
described in Section 7.2.2.
7.3 Implementation and Experimental Results
The receiver was fabricated in a low-cost 200/180 GHz fT/fmax 0.18 μm SiGe
BiCMOS process. The emitter width of the HBT is 0.15 μm. All the inductors in the
design were implemented using thin-film microstrip transmission lines with full ground
plane shield to isolate them from the conductive substrate and maintain continuous
ground potential. All interconnects were modeled and accounted for at both design and
layout phases. The microphotograph of the wideband receiver is shown in Figure 8-4.
The overall chip size is 1350 μm x 990 μm (1.34 mm2). All the measurements were
characterized on-wafer. For the receiver conversion gain and linearity test setup, the RF
signals were generated with the external multiplier modules (X4 and X6) with
synthesized sweeper (HP 83650B). The external LO signal was generated with Agilent
106
Figure 7-4. Microphotograph of the wideband receiver.
65 70 75 80 8510
15
20
25
30
4
6
8
10
12
14
16
18
20
No
ise
Fig
ure
(d
B)
Co
nve
rsio
n G
ain
(d
B)
Frequency (GHz)
Receiver Mixer
Figure 7-5. Measured receiver and down-conversion mixer conversion gain and noise figure (IF fixed at 100 MHz).
LNA
Balun Mixer & IFAmp
X2 and LO Buffer
DC Bias
RFin
IF+ IF-
LOin-
LOin+
107
vector signal generator (VSG) (E8267D) and external 10–40 GHz 180o hybrid junction
(HY1040–180). The on-chip active frequency doubler and LO buffer together provide
adequate LO power up to about 80 GHz. The IF outputs were fed through a 50–1000
MHz 180o power combiner. The standalone mixer characterization has a similar setup
except that the LO signal is generated by a V- or W-band source module and VSG. Port
matching and port-to-port isolation of the mixer were measured with Agilent 110 GHz
mm-wave network analyzer (PNA series). The noise figure measurement was done with
the calibrated V- and/or W-band noise source in conjunction with spectrum analyzer
(PSA E4448). All the off-chip losses were corrected and de-embedded from the
measurement results. As shown in Figure 7-5, the receiver achieves a measured power
conversion gain of 28.1 dB and NF of 8 dB at 77 GHz with at least 14 GHz 3 dB RF
bandwidth from 68 to 82 GHz. The NF of the receiver is between 8 and 10 dB across
the 3 dB BW.
Note that all the measurements were performed with IF fixed at 100 MHz unless
otherwise specified. The measured power conversion gain and single sideband (SSB)
NF of the mixer are 13.7 dB and 15.5 dB respectively, at 77 GHz. The SSB NF is ≤
16.5 dB over the frequency range from 67 to 82 GHz. Both gain and NF measurements
of the mixer include the loss of passive balun. The calibrated LO drive level at the input
of active frequency doubler is between -9.5 dBm and -4.5 dBm from 67 GHz to 82 GHz.
The measurement results beyond 80 GHz are limited by the 10–40 GHz 180o hybrid
and available LO drive, therefore the actual 3 dB RF BW of the receiver is expected to
be even larger.
108
-16 -14 -12 -10 -8 -6 -4 -2 0 2 40
5
10
15
20
25
Co
nv.
Gai
n a
nd
SS
B N
F (
dB
)
LO Input Power (dBm)
Conversion Gain SSB NF
RF = 77 GHzLO = 76.9 GHzIF = 100 MHz
Figure 7-6. Measured mixer conversion gain and SSB NF vs. LO input power.
Figure 7-6 shows conversion gain and SSB NF of the mixer versus LO input power
at 77 GHz. The mixer gain saturates at about -2 dBm LO input drive while the SSB NF
reached its minimum at 2 dBm. Degradation in both gain and NF performance can be
observed when the LO power level is dropped to below -4 dBm. Both RF and LO port
return losses are better than 10 dB while LO-to-RF and RF-to-LO isolation are better
than 40 dB and 30 dB, respectively over the target BW as shown in Figure 7-7. Figure
8-8 depicts the measured linearity characteristics of the mixer and receiver described by
input P1dB. At RF = 77 GHz and IF = 100 MHz, the mixer and receiver feature an input
P1dB of -10.3 dBm and -23.6 dBm, respectively. The measured input return loss of the
receiver is better than 9 dB across the 3 dB BW. The total power consumption is 413
mW. Table 7.1 and Table 7.2 outline the performance of this work and several recently
109
10 20 30 40 50 60 70 80 90 100 110-60
-50
-40
-30
-20
-10
0
Po
rt M
atc
hin
g a
nd
Iso
lati
on
Frequency (GHz)
RF LO LO-to-RF RF-to-LO
Figure 7-7. Measured RF and LO port matching and port-to-port isolation of the mixer.
-30 -25 -20 -15 -10 -55
10
15
20
25
30
IP1dB = -23.6 dBm
IF O
utp
ut
Po
wer
(d
Bm
)
RF Input Power (dBm)
Co
nve
rsio
n G
ain
(d
B)
RF = 77 GHzLO = 76.9 GHzIF = 100 MHz
IP1dB = -10.3 dBm
-20
-15
-10
-5
0
5
10
Receiver Mixer
Figure 7-8. Measured linearity characteristics of IF output power and conversion gain of
the mixer and receiver at RF = 77 GHz.
110
published state-of-the-art 77 GHz down-conversion mixers and ~77 GHz receivers
realized in SiGe HBT/BiCMOS technologies. The mixer FoM defined in equation (8-1)
has been computed for comparison. Besides, more than 14 GHz 3 dB RF bandwidth
achieved by this receiver is the largest among all.
PWRLINMIXER MixerNFMixerNFCGFoM )()( (8-1)
7.4 Chapter Summary
In this Chapter, a highly integrated wideband linear receiver with a 3 dB RF
bandwidth from 68 GHz to 82 GHz was presented. The receiver, fabricated in a low-cost
200/180 GHz fT/fmax SiGe BiCMOS process, achieved a maximum gain of 28.1 dB, a NF
of 8 dB, and an input P1dB of -23.6 dBm at 77 GHz and dissipates 413 mW. The distinct
advantage of wideband operation along with excellent linearity performance
accomplished in this radio receiver allows applications within the band, such as 71–76
GHz high speed point-to-point links, 76–77 GHz long-range and 77–81 GHz short-range
radar sensors to share and reuse the same front-end chip.
Table 7-1. Performance of prior published SiGe HBT/BiCMOS 77 GHz down-covnversion mixers
Ref Technology fT/fmax (GHz)
Topology IF Freq (MHz)
Conv. Gain (dB)
NF (dB)IP1 dB (dBm)
IF Amp.Pdiss (mW) @ VCC
Chip Area (mm2)
FoM
[78]* 0.13 μm SiGe BiCMOS 200/240
Single-Balanced 8800 20 12.8 -14.7 Yes 360@3 3.63 N.A
[79]** 0.18 μm SiGe:C HBT 200/275
Double-Balanced Gilbert
10 11.5 15.8 -0.3 No [email protected] 0.63 -78.5
[80] 0.18 μm SiGe:C HBT 200/200
Double-Balanced Gilbert
500 22 14 -30 Yes 300@-5 0.25 -93.6
[81]** 0.14 μm SiGe:C HBT 200/275
Double-Balanced Gilbert
1 15 11.2 2.5 No [email protected] 0.68 -60.2
[82]** 0.14 μm SiGe:C HBT 225/330
Micromixer 10 15 16 -3 No [email protected] 0.53 -72.21
[73] 0.13 μm SiGe BiCMOS 200/290
Double-Balanced Gilbert
N.A. 26 12-14 -26 Yes [email protected] N.A. -79.3
[83] 0.25 μm SiGe BiCMOS 180/200
Micromixer 100 13.4 18.4 -12 Yes [email protected] 0.28 -89.07
This work [84]
0.18 μm SiGe BiCMOS 200/180
Double-Balanced Gilbert
100 13.7 15.5 -10.3 Yes [email protected] 0.58 -78.4
*denotes superheterodyne down-converter. **denotes down-conversion mixer with no IF buffer.
111
Table 7-2. Performance of prior published SiGe HBT/BiCMOS 77 GHz receivers
Ref. Technology fT/fmax (GHz)
3 dB RF BW (GHz)
RX Gain (dB)@ Freq. (GHz)
RX NF (dB)
IP1dB (dBm)
Pdiss (mW)Chip Area(mm2)
Receiver Integration Levl
[68], [69]
0.13 μm SiGe BiCMOS 200/290
76–80 35@ 77 GHz
8–10 -27.5 161 2.25 LNA/Mixer/IF Amp/VCO (4X Array)
[70] 0.13 μm SiGe BiCMOS 170/200
76–81 25.6@ 78 GHz
9 -24 740 1.17 LNA/Mixer/IF Amp/VCO
[71] 0.18 μm SiGe BiCMOS 200/180
76–81 31@ 79 GHz
7.5–9.5 -30.7 601 7.4 LNA/Quadrature Mixer/PLL
[72] 0.18 μm SiGe:C HBT 200/275
75–82 ~32@ 77 GHz
11 (SSB) -16 1073 1.1 LNA/Quadrature Mixer/Branchline Coupler/LO Buffer
[73] 0.13 μm SiGe BiCMOS 200/290
73–81 46@ 77 GHz
7–10.5 -38 195 1.7 LNA/Mixer/IF Amp/VCO
[74] 0.13 μm SiGe BiCMOS 220/250
68–76 24@ 77 GHz
4.8 -21.7 120 0.23 LNA/Mixer/IF Amp/VCO
[75] 0.25 μm SiGe BiCMOS 180/200
79 21.7@ 79 GHz
10.2 (sim) -35 595 1.26 LNA/Mixer/VCO
[76] 0.14 μm SiGe:C HBT 225/330
75.5–77.5 30@ 77 GHz
11.5 (SSB)
-26 440 1.16 LNA/Active Balun/Mixer
This work [84]
0.18 μm SiGe BiCMOS 200/180
68–82 28.1@ 77 GHz
8–10 -23.6 413 1.34 LNA/Passive Balun/Mixer/ /IF Amp/Doubler/LO Buffer
112
CHAPTER 8 SUBMILLIMETER-WAVE HIGH-POWER HARMONIC SIGNAL GENERATION
8.1 Introduction
Submillimeter-wave voltage-controlled oscillators (VCOs) with high output power,
wide tuning range, and low phase-noise are essential building blocks for ultra-high
resolution imaging, remote sensing, biological, chemical sensors, and next-generation
optical communication systems. Several techniques for signal generations at
submillimeter-wave regime include fundamental oscillator design, integrated VCO and
frequency doubler, or harmonic oscillator design. The first approach, as mentioned in
Chapter 5, typically limited by the marginal device power gain and maximum oscillation
frequency (fmax) is hard to produce stable oscillation and good output power at
submillimeter-wave. Further, the phase noise is usually restricted by the NFmin of the
device as well as quality factor Q of the varactor, this indicates that having a high
spectral purity signal source with this technique is impractical. The second approach
using VCO and frequency doubler architecture seems to be a better option provided
that the power consumption of the active frequency doubler can be kept small. If,
however power consumption is a concern, passive frequency doublers can also be used
instead at the cost of higher input drive.
Note that high Q filters are sometimes needed to further enhance the suppression
of the undesired harmonic tones [85]. A more practical approach that can significantly
relax the aforementioned technical challenges can be realized with the harmonic VCO.
The push-push topology (2nd harmonic oscillator), in which the outputs of two sub-
oscillators coupled in anti-phase are combined to yield a strong second harmonic output
[86]-[89]. By using push-push design technique which extends the useful frequency
113
range of the available active device technologies even beyond fmax, the two fundamental
sub-oscillators only oscillate at half of the desired output frequency [90]. Owing to this,
the requirements on Q of the resonators are also relaxed therefore low phase-noise
designs become more feasible. It is also understood that the tuning range of a push-
push VCO is also doubled compared to the fundamental counterpart. Furthermore, a
frequency locked source can be realized by locking the oscillator in a phase-locked loop
(PLL) using a static or dynamic divider operating at the fundamental frequency instead
of at the second harmonic output frequency, reducing divider speed requirements by
half. In addition, the loading pulling is suppressed effectively due to the separation of
internal and external frequency.
However, large signal non-linear analysis for odd-mode operation of the sub-
oscillators is needed, which makes the design complicated. The bias network also has
to be properly designed with respect to two critical frequencies associated with the even
and odd modes of operation [91]. The output of a push-push VCO is single-ended;
therefore single-ended to differential conversion is needed if the circuit is to drive a
subsequent fully differential stage, e.g. double-balanced mixer.
In this Chapter, section 8.2 first presents the submicron InP HBT device
technology. Section 8.3 addresses push-push oscillator design including the
generalized Nth harmonic oscillators analysis. Experimental results and high frequency
measurement techniques will be discussed in section 9.4.
8.2 Submicron Indium Phosphide (InP) D-HBT Technology
InP/InGaAs double-heterojunction bipolar transistors (D-HBTs) have demonstrated
impressive cutoff frequencies while maintaining a high breakdown voltage with a large
band gap collector. HBTs have been considered as the most suited technology due to
114
its inherently superior low frequency 1/f characteristic. The push-push oscillators were
fabricated in a scaled i-line stepper-defined 0.5 μm InP D-HBT technology developed in-
house at Bell Laboratories, Alcatel-Lucent Technologies [92]. Dry-etched mesas are
used to replace the wet etched emitter, base and collector definition to ensure accurate
submicron emitter geometry and to enhance the device yield and uniformity. A narrow-
base layout is used to reduce the parasitic base-collector capacitance (Cbc). The back-
end integration of the InP D-HBT MMIC process includes thin-film capacitors and
resistors, as well as three levels of gold interconnect with low k inter-layer planarizing
dielectric layers [93]. Figure 8-1 shows the SEM of a dry-etched D-HBT before
planarization.
Figure 8-1. Dry etched D-HBT before planarization [92].
The HBTs fabricated on the same wafer have maximum extrapolated fT and fmax of
405 GHz and 335 GHz, respectively at current density of 600 kA/cm, as shown in Figure
8-2. The measured device breakdown voltage (VCEO) is 3.5–4 V.
115
Figure 8-2. Extrapolated fT and fmax of 0.5 x 4.0 μm2 emitter InP D-HBT measured as a function of collector current [93].
Maximum oscillation frequency (fmax), being one of the most important design
metrics, can be extrapolated from maximum transducer gain, GT,max. However, the slope
of GT,max changes depending on the stability factor K, decreases at a rate of 10
dB/decade when K < 1 and 20 dB/decade when K > 1. An alternative way to
characterize the fmax of the device is by extrapolating from unilateral Mason’s gain (GU)
which is defined as the maximum gain that can be obtained by unilateralizing the device
by compensating Y21 with a lossless feedback network.
GU is also used as a good indicator of the speed of the transistor. Figure 9-3
shows current gain (|h21|2) and unilateral Mason’s gain (GU) plotted against frequency.
As can be observed, the Mason’s gain GU drops at a rate of 20 dB/decade and is ~11
dB and ~5 dB at 100 GHz and 200 GHz, respectively. As frequency increases, the gain
becomes marginal to sustain oscillation. The push-push oscillator topology takes the
advantage of the additional 6 dB gain from the device to oscillate at the fundamental
116
Figure 8-3. Current gain (|h21|2) and unilateral Mason’s gain (GU) plotted against
frequency [92].
while producing twice the frequency at the output. This makes submillimeter-wave
oscillators practical and possible.
8.3 Push-Push Oscillator Circuit Design
8.3.1 General Nth Harmonic Oscillators Analysis
Figure 8-4 shows the block diagram of the push-push architecture with phase
coupling network. Qualitatively, the push-push oscillator (N = 2) operates as a second
harmonic oscillator in which two fundamental sub-oscillators are operating anti-
symmetrically at half of the desired frequency 2fo. When the two out-of-phase
fundamental signals which are achieved with the phase coupling network are combined
through the output network, the fundamental components are destructively cancelled
out while the second harmonic components are enhanced constructively at the load
ZLoad. The phase coupling network maintains the necessary phase difference between
the two sub-oscillators to facilitate harmonic generation. The phase coupling networks
can be realized by double-sided microstrip resonators, dielectric resonator (DRs), and
transmission lines with appropriate electrical length.
117
Fundamental Sub-Oscillator 1
Fundamental Sub-Oscillator 2
Phase Coupling Network
Output Network
Vout(t), Push-Push
ZLoad
V1(t), Fundamental
V2(t), Fundamental
I1(t), Fundamental
I2(t), Fundamental
Differential (Odd) Mode
Common (Even) Mode
Common (Even) Mode
Line of Symmetry
Figure 8-4. Block diagram of the push-push architecture with phase coupling network.
The push-push oscillator can also be described by Figure 9-5 using a fundamental
differential oscillator instead of phase coupling network. The fundamental differential
oscillator produces two 180o out-of-phase signal currents, upon combining through the
output network, the fundamental is cancelled and the push-push output is enhanced at
the load. In this design, the push-push oscillator can be more easily and clearly
perceived as described.
FundamentalDifferential Oscillator
Output Network
Vout(t), Push-Push
ZLoad
V1(t), Fundamental
V2(t), Fundamental
I1(t), Fundamental
I2(t), Fundamental
Differential (Odd) Mode
Common (Even) Mode
Common (Even) Mode
Line of Symmetry
Figure 8-5. Block diagram of the push-push architecture with fundamental differential
oscillator.
Due to the symmetry of push-push configuration, the line of symmetry observed in
Figure 8-4 and Figure 8-5 clearly defines the boundary for two modes of operations,
namely, differential (odd) mode and common (even) mode. At fundamental fo, the
118
undesired common mode oscillation should be suppressed while the desired differential
mode should be supported to in order to enhance the second harmonic oscillation at 2fo.
The half circuit common mode and differential mode equivalent circuits will be
discussed in Chapter 8.3.2.
Quantitatively, the two time-varying signals of the two sub-oscillators are given by
n
tjnn
tjtjtjtjtjnn
oooooo eAeAeAeAeAeAtV ...)( 44
33
221
)(1 (8.1)
)(33
)(22
)(1
)(2
0000)( ttjttjttj
n
ttjnn eAeAeAeAtV )()(4
400 ... ttjn
nttj eAeA
(8.2)
n
ttjnn
n
tjnnout
oo eAeAtVtVtV )]([21 )()()( (8.3)
...]1[]1[]1[)( 000 333
2221 tjtjtjtjtjtj
out eeAeeAeeAtV ooo (8.4)
If the phase difference at the fundamental between V1(t) and V2(t) is
to (8.5)
The push-push output becomes
...222)()(2
1
66
44
22
000
n
tjtjtjnPushPushout eAeAeAtVtV (8.6)
Equation 9.6 shows the cancellation of all the odd harmonics including the
fundamental while the even harmonics are added constructively. The higher order
harmonic terms (4ωo and 6ωo...) are filtered out.
Alternatively, the mathematical analysis can also be presented in another form in
terms of sinusoidal function. The two signals from the sub-oscillators can be expressed
as
0
1 )sin()(n
non tnatV (8.7)
0
2 )sin()(n
non ntnatV (8.8)
119
Note that V1(t) and V2(t) are differ by nπ where n is the harmonic index. The output
signal is the superposition of V1(t) and V2(t) at the load and is given by
...4,2
)sin(2)(n
nonPushPushout tnatV (8.9)
It is shown V1(t) and V2(t) are cancelled out when n = odd harmonics (1, 3, 5…)
while Vout(t)Push-Push is obtained when n = even harmonics (2, 4, 6…).
For triple-push oscillator (N = 3), the time-varying signals of each sub-oscillator
can be given by
n
tjnn
tjtjtjtjtjnn
oooooo eAeAeAeAeAeAtV ...)( 44
33
221
)(1 (8.10)
n
tjtjtjtjn
n
oooo
eAeAeAeAtV)
3
2(3
3
)3
2(2
2
)3
2(
1
)3
2(
2 )(
)3
2()
3
2(4
4 ...
tjn
n
tj oo
eAeA (8.11)
n
tjtjtjtjn
n
oooo
eAeAeAeAtV)
3
4(3
3
)3
4(2
2
)3
4(
1
)3
4(
3 )(
)3
4()
3
4(4
4 ...
tjn
n
tj oo
eAeA (8.12)
The output of the triple-push oscillator is given by
...)()(3
1
99
66
33
000
n
tjtjtjnPushTripleout eKeKeKtVtV (8.13)
Equation (9.13) shows the constructive addition of the third harmonic while the higher
order harmonic terms (6ωo and 9ωo...) are filtered out.
Similarly, for quadruple-push oscillator (N = 4), the time-varying signals of each
sub-oscillator can be given by
n
tjnn
tjtjtjtjtjnn
oooooo eAeAeAeAeAeAtV ...)( 44
33
221
)(1 (8.14)
n
tjtjtjtjn
n
oooo
eAeAeAeAtV)
2(3
3
)2
(2
2
)2
(
1
)2
(
2 )(
)2
()2
(4
4 ...
tjn
n
tj oo
eAeA (8.15)
n
tjtjtjtjnn
oooo eAeAeAeAtV )(33
)(22
)(1
)(3 )(
120
)()(44 ... tjn
ntj oo eAeA (8.16)
n
tjtjtjtjn
n
oooo
eAeAeAeAtV)
2
3(3
3
)2
3(2
2
)2
3(
1
)2
3(
4 )(
)2
3()
2
3(4
4 ...
tjn
n
tj oo
eAeA (8.17)
...)()(4
1
1212
88
44
000
n
tjtjtjnPushQuadrupleout eKeKeKtVtV (8.18)
Equation (8.18) shows the constructive addition of the fourth harmonic while the
fundamental, second, and third harmonics are suppressed due to the phase relations.
The higher order harmonic terms (8ωo and 12ωo...) are filtered out.
The analysis of the relative improvement in phase noise of the fundamental
oscillator, oscillator with frequency doubler, and Nth harmonic oscillator can be found in
[94] and can be highlighted as follows:
1. The phase noise of the fundamental oscillator operating at double the
oscillating frequency 2fo would incur additional 12 dB/octave degradation with respect to
the fundamental oscillator operating at fo.
2. The phase noise of the integrated oscillator and frequency doubler is degraded
by 6 dB/ octave with respect to the fundamental frequency.
3. The phase noise of the push-push oscillator has a relative improvement of 9 dB
with respect to the fundamental oscillator oscillating at twice the operating frequency. It
is only degraded by 3 dB when compared to the fundamental oscillator operating at fo.
For Nth harmonic oscillator, there is an improvement in phase noise in comparison with
the single oscillator by a factor of 10log (N) where N is the number of sub-oscillators.
However, the analysis is based on the assumption that the active device, low
frequency equivalent circuit is approximately constant in the low frequency noise
121
frequency range. In practice, the improvement may not be all that optimistic due to the
Q of the varactor and layout of the device, therefore the power gain and NFmin of the
device.
8.3.2 160 GHz and 200 GHz Push-Push Oscillators Design
The push-push oscillator based on differential Colpitts topology in this work
focuses on the signal output extraction from the base node instead of from the emitter
or collector node. Upon comparing among the three different push-push topologies, the
single-ended push-push output extraction from the emitter or collector node results in a
higher available power than that from the base node. In fact, the highest power is shown
to be extracted from the collector node [95], [96]. However, topology with the output
taken from the base node allows simultaneous the single ended push-push output and
differential fundamental outputs which enable phase locking at fundamental, making the
integrated high speed PLL system possible.
Figure 8-6 shows the schematic of the push-push oscillator in this design. As
mentioned in 8.3.1, due to the symmetry of push-push configuration, there exist two
modes of operation: one in-phase common (even) mode and one out-of-phase
differential (odd) mode. In common mode, the currents and voltages at each node are in
phase while in differential mode, the currents and voltages are 180o out of phase. For
the circuit to work, the undesired even mode oscillation should be quenched; only the
wanted odd mode should be excited so that the fundamental odd mode currents cancel
out while the second harmonic is constructively combined in phase. Figure 8-7(a) and (b)
show the equivalent sub-oscillator circuits of the push-push oscillator in differential
mode and common mode, respectively.
122
The sub-oscillator core is based on the common collector Colpitts oscillator as
shown in Figure 8-7(a). Large signal virtual grounds are stemmed from the differential
operation of the circuit, and they are present for odd harmonics. The bypass capacitor
CB shunting CBE of M1 is used to bypass the base-emitter diode and limits the non-linear
upconversion of noise at the base node. The value of it is typically larger than CBE to see
the improvement in phase noise. The negative resistance in this Colpitts is generated
by CB and a fixed capacitance CE. The resonant tank and oscillation frequency to first
order are set by CBE, CB, CE, and the base inductor LB. The emitter inductor LE provides
large impedance when looking into the emitter of M1 and is mainly used for biasing.
-VEE
M1
LC
REE
M2
RB
LC
LE LE
LB LB
CE CE
CB CB
Push-Push Output
-VBias
Fundamental Differential
Output
RLoad
Figure 8-6. Schematic of the push-push oscillator based on differential Colpitts topology.
123
However, it still contributes to the resonance if the impedance is not large enough.
Finally, inductive load LC is used to maintain the loop gain at high frequencies. The LC
gives another degree of freedom to optimize the fundamental differential output power
and second harmonic output power. However, the value of LC to first order has
negligible effect on oscillation frequency since it is not considered as part of the core.
Resistor REE is used instead of current mirror to improve common mode rejection at
submillimeter-wave. The push-push output is extracted at the differential large signal
ground at the base which is also biased with the resistor RB. Negative power supplies
are used in the design to facilitate a cleaner and more accurate signal ground.
LC
LB
CB
Differential Mode Output
M1
CELE
IBias
Large SignalVirtual Ground
Large SignalVirtual Ground
Large SignalVirtual Ground
A
-VEE
LC
LE
LB
CE
CB
Common Mode Output
2RLoad
2REE
Open
M1
B
Figure 8-7. Equivalent sub-oscillator circuits in A) Differential mode. B) Common mode (Bias not shown).
In the common mode operation, the push-push oscillator can be represented by its
half circuit equivalence. The output of the push-push is now terminated with twice the
124
load impedance RLoad which damps out the unwanted in-phase oscillation at the
fundamental frequency. Therefore the sub-oscillator should oscillate in the odd mode
while it should remain stable in the even mode.
All the inductors in the design are implemented by inverted thin-film microstrip
transmission lines with top metal acting as ground plane and bottom metal as signal
conductor. Figure 8-8 shows the cross section of the inverted thin-film microstrip
transmission line. The inverted thin-film microstrip is chosen over the regular one since
there are no breaks in ground plane. This allows excellent average ground potential
throughout the chip. However, as a drawback, it suffers from substrate radiation and
losses.
Figure 8-8. Inverted thin-film microstrip transmission line cross section.
Two push-push oscillators operating at 160 GHz and 200 GHz were designed in
which the component values are scaled proportionally. Non-linear large signal Harmonic
Balance simulation is necessary to accurately obtain the output power and oscillation
frequency. As an additional benefit of the push-push architecture, the accuracy of the
device model up to the fundamental (up to 100 GHz in this design) is sufficient.
125
8.4 Experimental Results
The layout view and chip microphotograph of the 200 GHz and 160 GHz push-
push oscillator are shown in Figure 8-9 and Figure 8-10, respectively. As discussed,
since the transmission lines are implemented by inverted thin-film microstrip, majority of
the chip layout cannot be seen. For proprietary purpose, this could be a good way to
prevent the design from revealing. On-wafer measurement at these frequencies is
challenging. Figure 8-11 shows the on-wafer measurement setup for push-push
oscillators. The downconverted output spectrum of the 200 GHz push-push oscillator is
measured using a GGB Industries Model 220 WR-05 waveguide probe and a Millitech
170–200 GHz downconverter block, consisting of an active multiplier (X6) feeding a
second harmonic mixer. The external LO is set at 15.62 GHz and the effective LO
frequency of 187.44 GHz is then mixed with the push-push output. The device under
test (DUT) in the setup serves as the RF source which completes the downconversion.
Figure 8-9. Layout view and microphotograph of the 200 GHz push-push oscillator.
Push-Push Output
126
Figure 8-10. Layout view and microphotograph of the 160 GHz push-push oscillator.
Ext LOFrom VSG
X6
DUT
Spectrum Analyzer
DC
G S G
WR-05
PGP
K cable
X2 Subharmonic Mixer
K cable
LO
RF
IF
Figure 8-11. Push-push oscillator measurement setup.
Push-Push Output
127
2.0 2.5 3.0 3.5 4.0
194
196
198
200
202
Co
rrec
ted
Ou
tpu
t P
ow
er (
dB
m)
Oscillation Frequency Output Power
Negative Supply Voltage -VEE (V)
Osc
illa
tio
n F
req
uen
cy (
GH
z)
-8
-6
-4
-2
0
Figure 8-12. Measured second harmonic frequency and output power as a function of
negative supply VEE for 200 GHz push-push oscillator.
1.0 1.2 1.4 1.6 1.8 2.0199
200
201
202
203
Co
rrec
ted
Ou
tpu
t P
ow
er
(dB
m)
Oscillation Frequency Output Power
Negative Supply Voltage -VB (V)
Osc
illat
ion
Fre
qu
ency
(G
Hz)
-4
-2
0
Figure 8-13. Measured second harmonic frequency and output power as a function of
negative supply VB for 200 GHz push-push oscillator (VEE fixed at 3.2 V).
128
The conversion loss of the mixer alone varies between 10 dB to 12 dB. The
additional losses due to the waveguide probe, downconverter, and cabling are
estimated to be about 15 dB in this frequency range. Figure 8-12 and Figure 8-13 show
the measured second harmonic frequency and corrected output power of the 200 GHz
push-push oscillator as a function of VEE and VB, respectively.
As shown, the oscillation frequency can be tuned from about 194 GHz to 202 GHz
by varying VEE from -2.1V to -4 V, showing a tuning range of 6 GHz. The measured
output power varies from -7.5 dBm to a maximum of -0.8 dBm which is achieved at VEE
= -3.2 V. By fixing VEE at -3.2 V while sweeping VB, it is found that the maximum output
power is achieved at VB = 1.35 V which draws a total current of 14.6 mA giving the
corresponding power consumption of 46.7 mW. The downconverted spectrum of the
200 GHz push-push oscillator is shown in Figure 8-14. The detailed downconverted
spectrum of the same oscillator is shown Figure 8-15. As can been seen from the 400
MHz detailed spectrum, a relatively clean output spectrum is obtained. Unfortunately,
accurate phase noise measurements using a spectrum analyzer are difficult.
Same measurement setup is used to measure the 160 GHz push-push oscillator
except the 140 – 170 GHz downconverter block is used instead. The external LO for
this measurement is set at 13 GHz with an effective LO of 156 GHz. The conversion
loss of the mixer alone varies between 11 dB to 17.5 dB. The estimated losses due to
the waveguide probe, cabling, and mixer are between 13 dB to 20.5 dB. Figure 8-16
and Figure 8-17 show the measured second harmonic frequency and corrected output
power the 160 GHz push-push oscillator as a function of VEE and VB, respectively. The
tuning range of about 9 GHz is achieved by varying VEE from -1.5 V to -3.2 V. The
129
Figure 8-14. Downconverted spectrum of the 200 GHz push-push oscillator. (Not yet corrected for the losses).
Figure 8-15. Detailed downconverted spectrum of the 200 GHz push-push oscillator. (Not yet corrected for the losses).
130
1.5 2.0 2.5 3.0
158
160
162
164
166
168
Co
rrec
ted
Ou
tpu
t P
ow
er (
dB
m)
Oscillation Frequency Output Power
Negative Supply Voltage -VEE
(V)
Osc
illa
tio
n F
req
uen
cy (
GH
z)
-10
-8
-6
-4
-2
0
2
Figure 8-16. Measured second harmonic frequency and output power as a function of
negative supply VEE for 160 GHz push-push oscillator.
1.0 1.2 1.4 1.6 1.8 2.0158
159
160
161
Co
rrec
ted
Ou
tpu
t P
ow
er (
dB
m)
Oscillation Frequency Output Power
Negative Supply Voltage -VB (V)
Osc
illa
tio
n F
req
uen
cy (
GH
z)
-2
0
2
Figure 8-17. Measured second harmonic frequency and output power as a function of
negative supply VB for 160 GHz push-push oscillator (VEE fixed at 3.0 V).
131
Figure 8-18. Downconverted spectrum of the 160 GHz push-push oscillator. (Not yet corrected for the losses).
Figure 8-19. Detailed downconverted spectrum of the 160 GHz push-push oscillator. (Not yet corrected for the losses).
132
measured output power from -9 dBm to the maximum of 2 dBm which is accomplished
at VEE = -3 V. From Figure 8-17, the maximum output power is found at VB = -1.6 V. The
oscillator draws 9.84 mA and the corresponding power consumption of 29.5 mW. The
downconverted spectrum of the 160 GHz push-push oscillator is shown in Figure 8-18.
The 300 MHz detailed downconverted spectrum of the same oscillator is shown Figure
8-19. A relatively clean downconverted spectrum is again observed.
8.5 Chapter Summary
In this chapter, two push-push oscillators operating at 160 GHz and 200 GHz are
reported. The two oscillators were realized in a 0.5 μm emitter InGaAs/InP D-HBT with a
fmax of 335 GHz and a breakdown voltage (VCEO) of 4 V. The common collector
based Colpitts push-push oscillator with the output taken at the base node allows
simultaneous single ended second harmonic output and differential fundamental output,
simplifying the PLL design. The push-push oscillator has been shown to perform better
than the fundamental oscillator at the same frequency in terms of robustness, output
power, phase noise, and tuning range. The experimental results of both push-push
oscillators have exhibited very impressive output powers of 2 dBm and close to 0 dBm
at 160 GHz and 200 GHz, respectively. While push-push oscillator designs were also
reported in 130 nm and 90 nm CMOS technology [97], [98], however, due to the
reduced breakdown voltage of the highly scaled silicon CMOS technologies, a
significant reduction in output power is observed for oscillators beyond 100 GHz. The
lack in the output power might not be sufficient for many millimeter- or submillimeter-
wave source applications such as high performance imaging, remote sensing and next
generation optical systems.
133
The simulations indicate that by further reducing the length of the resonator and
the capacitor size, harmonic oscillators with higher operating frequencies and even
beyond the device fmax are possible. This implies the high power THz signal generations
can be expected in the very near future.
134
CHAPTER 9 SUMMARY AND FUTURE WORKS
9.1 Summary
In this Ph.D. dissertation, new circuit architectures and combined analog and
microwave design techniques were studied. The individual circuit blocks such as, low-
power linear 77 GHz low-noise amplifier (LNA), down-conversion mixer, passive balun,
tunable quadrature power splitter (QPS), and 100 GHz regenerative frequency divider
(RFD), and 80 GHz active frequency doubler were independently characterized and
fabricated in a low-cost 0.18 μm SiGe BiCMOS technology. A 68–82 GHz highly
integrated, wideband linear receiver is experimentally demonstrated. The receiver
achieves a maximum gain of 28.1 dB, a NF of 8 dB, and an input-referred 1 dB gain
compression point (IP1dB) of -23.6 dBm at 77 GHz while dissipating 413 mW. This
integrated receiver enables applications within the band to share and reuse the same
front-end chip. To further explore the opportunity at higher frequency, an 81–92.6 GHz
low-noise amplifier is demonstrated with a gain of 21 dB, a NF of 9 dB, and an IP1dB of
-18.8 dBm.
On the other hand, critical transmitter building blocks, such as an up-conversion
mixer has also been investigated. A highly linear double-balanced active up-conversion
mixer based upon multi-tanh triplet technique has been validated to show a single
sideband (SSB) power conversion gain of 5.1 dB and an output-referred 1 dB gain
compression point (OP1dB) of -5.8 dBm at 77 GHz.
Finally, a high power signal generation at submillimeter-wave is demonstrated and
fabricated in InGaAs/InP D-HBT technology. The second harmonic push-push oscillator
shows an output power of 0 dBm at 200 GHz which opens a new frontier for
135
applications such as weather observation radar, chemical, and tumor detections, and
next generation optical system. By using even higher order harmonic generation, THz
signal sources can be expected in the very near future.
9.2 Future Works
9.2.1 Wideband Direct-Conversion Transmitter Front-End
The block diagram of a wideband direct-conversion transmitter front-end is shown
in Figure 9-1. By making use of the tunable quadrature generation along with other
wideband building blocks in the transmitter design, wideband operation could be
achieved. The transmitter front-end consists of two tunable quadrature power splitters,
two up-conversion mixers, an 180o power combiner, a power combined power amplifier,
and an active frequency doubler with a power buffer.
PowerBuffer
PA0/
180
0/90
RFoutX2
Ext LO
0/90
LOI+
LOI-
LOQ+
LOQ-
IFI+ IFI-
IFQ+ IFQ-
Figure 9-1. Block diagram of the wideband direct-conversion transmitter front-end.
9.2.2 Other Opportunities in Bulk CMOS
Millimeter-wave wideband active balun with enhanced common-mode rejection
The active balun first proposed and later patented by Dr. Jenshan Lin was designed at
1.5 GHz and fabricated in 0.25 μm CMOS for proof-of-concept. The enhanced common-
136
mode rejection ensures that excellent amplitude and phase balance over a very wide
bandwidth. Compared to the traditional passive baluns which are implemented by lossy
transformer, power splitter, or rat-race, it is noticed that this active balun technique at
mm-wave is favorable because it can provide gain which is sacred at mm-wave. In
addition, the circuit size can be made much more compact. Further, the impact on NF of
the overall receiver could be improved depending on the circuit and system design. The
design tradeoffs among noise, linearity, and bandwidth shall be investigated.
137
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BIOGRAPHICAL SKETCH
Austin Ying-Kuang Chen was born in Taipei, Republic of Taiwan in December
1982. He received the Bachelor of Science degree in electrical and computer
engineering from Purdue University, West Lafayette, Indiana. in May 2003. He received
the Master of Science and Professional degrees in electrical engineering from Columbia
University, New York City, New York, in May 2004 and May 2007, respectively. In May
2010, he was awarded his Ph.D. degree in electrical and computer engineering from
University of Florida, Gainesville, Florida. His broad research interests include
RF/microwave/millimeter-wave integrated active and passive components and Gb/s
wireless transceivers, high speed mixed-signal electronics, THz signal generations, and
on-chip antenna designs using CMOS, SiGe BiCMOS, and InP HBT technologies. His
experience also includes the design and development of millimeter-wave power
amplifiers and high speed PLL synthesizers. In addition, he enjoys all kinds of water
sports including surfing, kiteboarding, stand-up paddle boarding (SUP), wakeboarding,
kneeboarding, and scuba diving.