optimal electronic circuits and microsystems networked designer optimal electronic circuits and...
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OPTIMAL ELECTRONIC CIRCUITS and OPTIMAL ELECTRONIC CIRCUITS and
MICROSYSTEMS NETWORKED MICROSYSTEMS NETWORKED DESIGNERDESIGNER
Prof. ANATOLY PETRENKO National Technical University of Ukraine
“Kiev Polytechnic Institute”, Tel./FAX +380 44 280 90 46,
e-mail: [email protected]
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OutlineOutline
• Networked CAD tools • International co-operation
Experience• ALLTED – All Technology
Designer • Novel numerical methods• Results of solving the
benchmark circuits • Optimization example• AND Logical Circuit on OET • Possible co-operation
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Networked CAD tools
• Remote access to CAD tools and collectively execution the joint Projects ;
• Meeting different requirements to hardware of a server and a client ;
• New level of functional cooperation via GRID infrastructure;
• Possibilities for Small and Middle enterprises to take a part in international work force distribution developing competitive products.
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ALLTED – All Technology Designer
Previous versions of this system (named SPARS, PRAM-01, PRAM-PK, PRANS for EC and SM computers) were used in the former Soviet Union as the branch Ministry of the Defense industry standard OST V3-4776-80 for circuit design automation and similar standards for the Ministries of General and Average Machinobuilding and Radio industry.
ALLTED is especially useful in the development of new products which combine various physical phenomena in one device
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International co-operation ExperienceInternational co-operation Experience• Digital (Alpha Processor simulation)
• Intel (Parallel computation, Formal verification, Layout extraction, VLSI Interconnects Model-Order Reduction ,ALOE to Cadence / Cadence to ALOE converters )
• General Electric (MEMS Model design)
• Motorola ( Signal Processors implementation)
• Sun ( Layout verification)
• Panasonic (Remote Access to Networked Appliances )• Melexes (VLSI design with 0.25 u)
• HPC –Germany ( RF circuits design)
• EC Projects ( Tempus, Inco- Copernicus)
• STCU Projects ( Remote Simulation, MEMS Design)
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Layout visualizationLayout visualization
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PostGL-3D Open GL ViewerPostGL-3D Open GL Viewer
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ALLTED – All Technology Designer
• ALLTED is an acronym for ALL TEchnology Designer. It was developed not only for simulation and analysis, but for processing project procedures such as: – parametric optimization tasks;– optimal tolerance assignments;– centering availability regions;– yield maximization;– design of Nonlinear Dynamic Systems composed of
either/and electronic, hydraulic, pneumatic, mechanical, electromagnetic, and other elements.
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ALLTED – All Technology Designer
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ALLTED – Shematic editor
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ALLTED in distributed Web environment
Allted Studio
ComputationCoordinator
Workstation
The Internet/message exchange
protocol
Librarian
Postprocessor
Calculation module
Wrapper
Local Data
ResourceCatalog
DirectoryService
DBMS
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ALLTED usage examplesALLTED usage examples
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ALLTED usage examplesALLTED usage examples
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ALLTED usage examplesALLTED usage examples
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ALLTED usage examplesALLTED usage examples
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ALLTED usage examplesALLTED usage examples
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ALLTED usage examplesALLTED usage examples
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System on a ChipSystem on a Chip
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System on a ChipSystem on a Chip
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ALLTED offers:
• Faster simulation speed and improved numerical convergence;• Sensitivity analysis for frequency and transient analyses; • Comprehensive optimization procedure and optimal
tolerances assignment ;• Alternative approach to the secondary response parameters
determination (delays, rise and fall times, etc.); • Powerful user-defined modeling capability .• Original way of generating a system-level model of MEMS
from FEM component equations.
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Novel numerical methods
• The new solution curve-search method for Steady State (DC) Analysis which provides the quick descent to
the solution point region from any starting point
• The Diagonal Modification Method which helps considerably preserve convergence of linearized equations solution without re-ordering when matrix element values change from one iteration to another iteration .
• The Optimization Variable-order Methods which is equivalent to taking into consideration five terms of Tailor’s series for the Goal function which considerably improve determination of a direction to the optimal point
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Novel numerical methods
• The Implicit Linear Multi-step Variable-order Integration Method for Transient Analysis(TR) which uses high order back differences that allows to select the proper one resulting in minimization of solution time for prescribed accuracy .
• The Optimal Tolerances Assignment Method which is based on applying Optimization procedures and takes into account the prescribed deviations of Controlled Output Parameters
• Statistical Yield Maximization Method which provides “centering” the solution point in the region of acceptable solutions
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DC Method Example 1DC Method Example 1
EVVRIVVf T 13 ex pD i o d e c i r c u i t e x a m p l e
f ( V )
V
N e w t o n ’ s s t e p
C S - p a t hS t a r t
VE
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Diagonal modification methodDiagonal modification method
It helps considerably preserve convergence of linearized equations solution without re-ordering : Ajx=b
Let during calculation jkk
a ,
tkekgkejAjA , where 0100ke ...... .
From two solutions kezjA and bXjA
we shall get the initial solution in hand:
ZXX
qzx
k
k
k
1
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TR solution approachTR solution approach
1 . P o s s i b l e e r r o r s a r e e s t i m a t e d f o r 1 , 2 , . . . , k + 1 o r d e r s o f i m p l i c i ti n t e g r a t i o n m e t h o d :
D D Dk
E E E1 2 1, , . . . , ,
1 6 kw h i c h a r e i n t h e f o r m :
T
n n knk
nh
t t X
1
11
1 .
2 A t e a c h t i m e s t e p m a x i m u m p o s s i b l e e r r o r v a l u e i s s e l e c t e d a n dc o r r e s p o n d e d o r d e r k i s u s e d .3 . N e w t i m e s t e p i s m o d i f i e d b y
j ji
D
kh h eE
1 1 .
w h e r e ( = E h / T ) - a n e r r o r , w h i c h c h o o s i n g b y c u s t o m e r
4 . C o m p o s e I m p l i c i t - E x p l i c i t p r o c e d u r e s ( E x p l i c i t P E C E m e t h o d a n d I m p l i c i t N e w t o n ’ s i n t e r p o l a t i o n f o r m u l a a s H i g h o r d e r b a c k d i f f e r e n c e s m e t h o d )
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Optimization Variable order methodOptimization Variable order method
It allows:
to generalize existing methods (steepest descent method, damped Newton's method, etc.) ;
to decrease weight of a line search in determine next point during optimization procedure.
X X X X X X X
X X X X
t
0 0 0
03
04
1
2
9''''
The matrices of fourth and fifth terms are determined through Hessian and Jacobian matreces
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INTEL AWARD
Конкурс исследовательских проектов области автоматизации Проектирования интегральных схем
награждается
ПЕТРЕНКО АНАТОЛИЙ ИВАНОВИЧ
Национальный Технический Университет Украины «Киевский политехнический институт
ПРОЕКТ
Разработка эффективных численных методов моделирования и оптимизации схемотехнических решений для СБИС
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Results of solving the benchmark circuits of the Microelectronics Center in North
Carolina
Circuit ALLTED PSPICE Gain
Iteration Iteration
INPUT 358 755 2.11
CHARGE 4682 7625 1.63
FADD32 873 2280 2.61
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CHARGE Circuit with BISIM 49 ModelsCHARGE Circuit with BISIM 49 Models
M12
M1 M2
M13 M14
M3 M4
M15
M5
M16 M17
M6 M7
M18
M8
M19 M20
M9 M10
M21
M11
Out
Ecc
M22
M23Evin
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ALLTEDALLTED and PSPICE v.9.2 outputs: and PSPICE v.9.2 outputs:
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FADD32FADD32 Circuit (288 transistors) Circuit (288 transistors)
Cin
A1
B1
Cout
Out
FullAdddd1
Cin
A1
B1
Cout
Out
FullAdd2
Cin
A1
B1
Cout
Out
FullAdd3
Cin
A1
B1
Cout
Out
FullAdd4
M1
M3
M2
M4
VSS
VDD
Out
InputB
InputA
InA InB
Out
CNAND1 A1
A2
Out
FullAd
Cin
R1 R2 Out
HALFADD1 S3
R1 R2 Out
HALFADD2
S3
Cout
InA InB
Out
CNAND1
InA InB
Out
CNAND2
InA InB
Out
CNAND3 InA InB
Out
CNAND4
RAMP1
RAMP2
S3
Out
HALFADD
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ALLTED and PSPICE v.9.2 outputsALLTED and PSPICE v.9.2 outputs
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Simulation results obtained by ALLTED and Simulation results obtained by ALLTED and HSPICEHSPICE
Circuit DC Iteration number, ALLTED
DC Iteration number, HSPICE
TR Iteration number, ALLTED
TR Iteration number, HPSPICE
Bjtinv 95 96 1340 3239
Gm3 80 185 149 219
Make2 12 10 527but 256 steps
327outputs aredistorted
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MIKE2 Circuit with bsim13 models:MIKE2 Circuit with bsim13 models:
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ALLTED and HSPICE outputs for ALLTED and HSPICE outputs for Mike2_bisim13:Mike2_bisim13:
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ALLTEDALLTED statistics of the transient analysis statistics of the transient analysis of of Mike 2Mike 2
• S t a t i s t i c s• Number of steps = 256• Number of iterations = 528• Number of steps per order:• order - 0 - = 26• order - 1 - = 46• order - 2 - = 90• order - 3 - = 71• order - 4 - = 19• order - 5 - = 4• order - 6 - = 0• Number of rejected steps = 23• HSPICE uses only 2-d order integration formula
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Optimization example 1
Circuit: Operational Amplifier
RCA 3040 with 11 transistors
Task: calculate the resistances R1, R3
and R4 values in such a way, that the
output impulse amplitude on resistor
R11 would be equal to 8 V.
0.1 <= R1 <= 10
0.1K <= R3 <= 10
0.1K <= R4 <= 10K
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Optimization example 1Task file:• tr;• optim;• const DCERR=1.e-6;• const tmax=90, MINSTEP=1e-4,
ERR=0.01, LERR=0.1, REVAL=3;
• # TR OUTPUT parameters• fix T3=MINF(UR11); • fix T4=MAXF(UR11); • INT DURF=T4-T3;• const method=120;• varpar R1(0.01,10), R3(1,100),
R4(1,100);• of DIF1 = F1(8/DURF);• plot Ur11;
Objective function DIF1 = .3146487870E-07• R E S U L T S O F O P T I M I Z A T
I O N Variable parameters R1 = .1000000000E+01 R3 = .6778549874E+01 R4 = .6778549874E+01
Directive F I X output characteristics• T3 = 2.47580528 • T4 = 10.4756279 Directive I N T output characteristics
• DURF = 7.99982262
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Optimization example 2Circuit: Active RC filter RAD• Task;• dc;• ac;• optim;• const lfreq=0.0025,
ufreq=0.005,METHOD=152;• TF K1=V6/UE1; • plot MA.K1; • fix f1=MAXA(MA.K1); • fix f2=MAXF(MA.K1)• func f5=F7(1/f2);• of error=f5(1/f5);• varpar Alpha.OP1(3E1,4E3),
Alpha.OP2(0.6E1,1E3);• limit Lim2=F2(0.003734/f1);
RESULTS OF OPTIMIZATION
ERROR = 0.1786038652D-01 Variable parameters ALPHA.OP1 = 0.3709765013D+04 ALPHA.OP2= 0.1000000000D+04
ALPHA.OP1ALPHA.OP2
= 0.3709765013D+04= 0.1000000000D+04
Constraints
LIM2
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Interactive Tasks formationInteractive Tasks formation
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Optimal tolerance assignment example:
Circuit: Operational Amplifier RCA 3040 with 11 transistors
Task: calculate the resistances R2, R3 and voltage source E2 tolerances values
for which the output minimal voltage UR11 changes +/- 5% of its value.task;
dc;
tr;
tolas;
const tmax=90 ,ERR=0.01,
LERR=0.1, REVAL=3;
FIX UM=minf(UR11);
const TOLERR=0.001;
control UM(5,5);
varpar E2(10),R2,R3(10);
O P T I M A L T O L E R A N C E S
***********************************
Parameter Nominal Tolerance
value % abs
E2 .1200000000E+02 +- 19.682 +- -.2361829758E+01
R2 .1000000015E+00 +- 4.614 +- .4613934550E-02
R3 .1000000000E+01 +- 3.697 +- .3696829081E-01
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Mixed Analyses example
Macromodel 2-input AND Cell (0,1,2,3);
j1(1,0)=f300(ut,rbx/uj1);
j2(2,0)=f300(ut,rbx/uj2);
e1(3,0)=f310(u1,u0,f1,d1,f0,d0,r1,r0,-1/ue1,ie1);
list m1.icand;
rbx=50; ut=1; u0=0.3; u1=2.4; f1=-1; d1=10;
f0=-1; d0=10; r1=0.1; r0=0.02;
Now we are going to provide possibilities
for users to access NetALLTED resources through the Internet for optimal
Microsystems design.
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The example of Micro-machined Ultrasonic Transducer simulation
Model Membr00 ( Vin, Center, Base ); • Jcap (Vin, Base) = F253 ( eps_0, area, dred / UJcap, UJvel, UJx); • Ls(Center,Base) = compl; • Ga(Center,Base) = damp; • Cm(Center,Base) = mass; • Jst(Center,Base)=F42(10., gap, 128, 0.1 / UJx, UJvel); • Jel(Base,Center) = F252 ( 8.842e-12, 1963., 1.06 / UJcap, UJx ); • Jvel(Center,Base)=0; • Jdx(Base,x)=f249(1/UJvel); • Cx(x,Base)=1; • Jx(x,Base)=0; • Jfqs(Base,x) = f250( 1. / IJel ); • Jfss(x,Base) = f250( stiff / UJx ); • Jfst(Base,x) = f251( 10., gap, 1000. / UJx );
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AND Logical Circuit on OETAND Logical Circuit on OET
One-electron transistor model
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Microwave Devices in ALLTEDMicrowave Devices in ALLTED
• Model of transmission line with a negative inductance
H
W
ErT
L
Fig. 8 The
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ALLTED adaptation to a new applicationALLTED adaptation to a new application
• New components mathematical models incorporating ( in equations form)
• New graphical symbols for components, if any• New sections in library with components parameters• OF, LIMIT and FUNC libraries upgrading
if any• Numerical procedures constants adjusting for new types of
tasks
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MEMS Simulation levelMEMS Simulation level
System levelSystem level
Components levelComponents level
Circuit levelCircuit level
Model Order reductionModel Order reduction
( ) ( ) ( )
( ) ( )T
X t AX t Bv t
Y t C X t
( ) ( ) ( )
( ) ( )T
x t Ax t Bv t
y t C x t
(Krylov- Arnoldi Method)(Krylov- Arnoldi Method)
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Circuit model reduction methodCircuit model reduction method
( )T T
Mx Dx Kx BF t
y Q x R x
,Y v F Y C G L
1
, , 1(1) ,
, 1(1) .
ij ij
N
ii ijj
C m i j N i j
C m i N
1
1/ , , 1(1) ,
1/ , 1(1) .
ij ij
N
ii ijj
L k i j N i j
L k i N
1
, , 1(1) ,
, 1(1) .
ij ij
N
ii ijj
G d i j N i j
G d i N
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Y/∆ transformationY/∆ transformation
* ,ji ikjk jk
ii
y yy y
Y
1
k
2
i
y1
yk
y2
1
2
k
y1 y2
yk
L
R
Ci
/RCi i iC G
/RCi i iC G /LCi i iC B
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Y/∆ transformationY/∆ transformation
Для складних 2-х і 3-х вимірних компонентів схемні моделі можуть мати дуже велику розмірність, ґтак що їхпорядок теж треба скорочувати
RCi LCi LCi RCi
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Y/∆ transformationY/∆ transformation
Для складних 2-х і 3-х вимірних компонентів схемні моделі можуть мати дуже велику розмірність, ґтак що їхпорядок теж треба скорочувати
RCi LCi
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MicroaccelerometerMicroaccelerometer
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The finite element model of the The finite element model of the accelerometeraccelerometer
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Eigenfrequencies of MicroaccelerometerEigenfrequencies of Microaccelerometer
n = 1; f = 181,36 kHz n = 2; f = 1018,1 kHz
n = 3; f = 1018,1 kHz n = 4; f = 3427,8 kHz
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Electrical Circuit Reduction ResultsElectrical Circuit Reduction Results
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Possible Project TasksPossible Project Tasks
• ALLTED facilities Testing on Samsung Examples (optimization, tolerance assignment, yield maximization, DC conversion, RF design etc.)
• Adaptation and enrichment of ALLTED component models Library (including new ones, say, for CCD , MEMS and IP Solutions), using semantic formats
• Developing parallel numerical simulation algorithms for a supercomputer
• Implementation of parallel ALLTED version in Grid environment and providing possibilities of remote its executing through Internet
• Development of the methodology of IC energy consumption minimization based on ALLTED optimization procedures (say, by varying W and L of transistors and keeping the given frequency value).
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Thanks you very much !Thanks you very much !