opamp

Analog Integrated Circuits and Signal Processing, 20, 111±118 (1999)

10 mA Quiescent Current Opamp Design for LCD Driver ICs

TETSURO ITAKURA,{ Member AND HIRONORI MINAMIZAKI,{{ Nonmember{Research and Development Center, Toshiba Corporation, Kawasaki-shi, 210-8582 Japan

{{Semiconductor System Engineering Center, Toshiba Corporation, Yokohama-shi, 247-8585 Japan

Received June 19, 1997; Revised September 10, 1997

Abstract. This paper examines the design considerations for an opamp to be used in a low-power consumption

LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation

with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The

experimental results support our opamp design approach and indicate the feasibility of 10 mA quiescent current

opamp.

Key Words: analog circuits and signal processing integrated electronics, CMOS opamp, low power

1. Introduction

This paper examines the design considerations for an

operational ampli®er (opamp) to be used in a low-

power 256 gray-scale LCD (liquid crystal display)

driver IC. The driver IC contains 120±384 opamps as

output buffers, as shown in Fig. 1; it is very important

to reduce the power consumption of the individual

opamps, and especially their quiescent current,

without increasing a settling time.

To improve the lifetime of a liquid crystal, the

polarity of the applied signal should be alternated. A

common-inversion drive method is widely adopted in

driver ICs to reduce power consumption, i.e., to

reduce the required output amplitude of the driver ICs

by alternating the potential of the common electrode,

COM, of the LCD panel as shown in Fig. 2, where the

load of the opamp is assumed as capacitor CL. In the

common-inversion drive method, a settling time of 1±

3 msec is inevitable because the potential of COM

alternates.

To realize 256 grays, the equivalent input offset

voltage of the opamp should be within + 5 mV. Since

the offset voltage of the opamp is + 10±+ 20 mV,

offset-cancelation is necessary to satisfy this offset

requirement. Offset-cancelation also requires a time

of 3±5 msec to complete.

Considering the offset-cancelation time and the

settling time resulting from the common-inversion

drive method, the overall settling time should be less

than 7 msec, assuming a horizontal interval of about

15 msec for SVGA. The necessary slew rate is then

greater than 1 V/msec, assuming a power supply

voltage of 3±5 V.

The target opamp speci®cations are summarized in

Table 1, where 70 dB DC gain is required to reduce

the error between buffer input and output.

The quiescent current is reduced to 10 mA or less

by simply reducing the bias current, but this causes the

settling time longer. Settling time of 8 msec was

reported, but the quiescent current is about 16 mA [1].

This trade-off between low quiescent current and

short settling time should be overcome in the opamp.

In this paper, the conventional design approach is

reviewed and the design policy is clari®ed in Section

2. The proposed opamp is shown in Section 3. The

techniques to achieve low quiescent current and the

short settling time are described. Experimental results

are presented in Section 4. Improvement of the

settling time and a rail-to-rail input stage suitable

for the opamp are discussed in Section 5.

2. Conventional Design Approach

Fig. 3 shows a conventional opamp incorporating a

precharge switch, where a two-stage structure is

necessary to achieve a DC gain of more than 70 dB.

The rising slew rate is limited by the ratio of the bias

M9258 Kluwer Academic Publishers Analog Integrated Circuits and Signal Processing (ALOG) Tradespools Ltd., Frome, Somerset

Copyright, 1998, IEICE, reprinted with permission from IEICE.

current supplied from mp3 to the capacitance of the

signal line on the LCD panel. To avoid this rising slew

rate limitation and the resulting long settling time, a

precharge switch at the output is turned on; This

precharges the capacitance to Vdd before buffer

operation. This precharge operation consumes unne-

cessary power and causes high instantaneous current

consumption because the outputs of all opamps in

the driver IC are simultaneously precharged;

Consequently, the power supply unit must be of

greater capacity. To reduce the instantaneous current,

the on-resistance of the switch can be increased;

however, this makes the precharging time longer. The

on-resistance, i.e. the size of the switch transistor,

should be carefully determined taking into account the

trade-off between precharging time and instantaneous

current.

The quiescent current is determined by the bias

current Ibias. By reducing Ibias, the quiescent current

could be reduced to 10 mA. However, since the slew

rate is also limited by the ratio of the bias current

supplied from mp4 to the phase compensation

capacitor, CF, the slew rate would fall by the same

ratio and the settling would not be satis®ed. The

reduction of Ibias also leads to a decrease of gain-

bandwidth product, i.e. an unity gain frequency; the

settling time would become longer. Recently, an 8 mA

quiescent opamp for a 6-bit LCD driver IC was

reported [1]; however, quiescent current of 16 mA is

required to achieve a settling time of 8 msec even with

a slew rate enhancement in an analog LCD driver IC

[1]. Thus, a conventional opamp design cannot be

used to achieve a 10 mA quiescent current and 7 msec

settling time opamp. In order to realize the opamp, the

following improvements must be achieved simulta-

neously: (1) slew rate enhancement; (2) improved

phase margin with reduced compensation capacitance

to increase an unity gain frequency; and (3) limitation

of instantaneous current consumption to alleviate

power requirements.


Table 1. Target speci®cations.

Parameter Requirements

Power supply voltage 3±5 V

DC gain 4 70 dB

Max. load capacitance 150 pF

Settling time 5 7msec

Slew rate 4 1 V/msec

Quiescent current consumption 5 10mA

Fig. 3. Conventional opamp.Fig. 1. LCD driver IC.

Fig. 2. Common-inversion drive method.

112 I. Itakura and H. Minamizaki

3. Design of 10 mA Opamp

Fig. 4 shows the proposed opamp. Some slew rate

enhancement techniques have been proposed [2±4]. In

techniques [2,3], a change in input voltage is detected

at the input by another ampli®er. The opamp [1] uses

the technique [2]. Considering the application of the

slew rate enhancement techniques to a rail-to-rail

input voltage, the techniques [2,3] cannot be simply

applied as it is and must be modi®ed to use both n-

type and p-type of differential pairs. On the other

hand, the technique [4] can be applied as it is because

the change in input voltage is detected at the output of

the input stage. Therefore, the slew rate enhancement

technique [4] is used. To limit instantaneous current

during slew rate enhancement, the maximum slew rate

is held to the required value by limiting the maximum

current added to the bias current by current sources

mn12 and mn13, respectively.

The phase compensation capacitance also needs to

be reduced in order to achieve a higher unity gain

frequency; thus improved phase compensation and

enhanced transconductance of the output stage should

be considered.

A technique for improving phase compensation has

been proposed [7,8]. This technique is based on the

idea of feeding back a current proportional to the time

derivative of the output voltage to the output of the

opamp's ®rst stage. It requires a common-gate stage

to provide a low-impedance node. However, a

common-gate stage consumes additional current.

Further, the number of current sources to be controlled

by the slew enhancement circuit is increased when the

common-gate stage is included in the input stage.

Here, a cascode structure is applied to the active

load of the ®rst stage, where the gate bias of mn1B and

mn2B is applied to the cascode transistor. In this

structure, mn1B and mn2B operate in non-saturation

region. However, the impedance of the source node of

mn2A can be made suf®ciently low compared with the

output impedance of mn2B by having the ratio of

channel width to channel length of mn1A and mn2A,

�W=L�mn1A and �W=L�mn2A larger than �W=L�mn1B

and �W=L�mn2B, respectively. In the case that

�W=L�mn2A is 4 times larger than �W=L�mn2B, the

impedance of the source node of mn2A is about one

fourth of the output impedance of mn2B; about 80%

of the feedback signal through the compensation

capacitor to ¯ow into mn2A. The phase margin is

improved suf®ciently as described in the reported

techniques using common-gate transistors. With this

cascode structure used in the active load, the slew rate

enhancement technique can be applied.

As discussed in [8], this type of phase compensa-


Fig. 4. 10mA opamp.

10mA Quiescent Current Opamp Design 113

tion technique may cause gain-peaking of the

frequency response, especially when the load capaci-

tance is small. To avoid gain peaking, a conventional

phase compensation capacitor, CF1, is also used. The

slew rate depends on the sum of CF2 and CF1. Keeping

the sum constant, the ratio CF2=CF1 is determined,

considering the range of the load capacitance CL. CL

depends on the size of the LCD panel and is assumed

to be about 10 pF to 150 pF. Figs. 5 and 6 show the

frequency responses for CF2=CF1 � 0 to 4 with

CL � 150 pF and CL � 10 pF, respectively, where

the sum of CF2 and CF1 is kept constant. Larger

phase margin is achieved for larger CF2=CF1 in the

case of CL � 150 pF; however, larger CF2=CF1 causes

gain peaking in the case of CL � 10 pF. Here,

CF2=CF1 of 1 is used.

To increase the transconductance of the output

stage with limited quiescent current, a class AB output

stage with a push-pull structure, as shown in Fig. 7, is

adopted, since the transconductance of the output

stage is the sum of the transconductances of the

NMOSFET and the PMOSFET. The deriver ampli®er

of mp3, however, operates as an additional gain stage.

The gain B should be around one, since a large gain

reduces the phase margin.

Here, the push-pull output stage reported in [9] is

adopted since the quiescent current at the output stage

is well controlled. Note that gm of mn9 should be

increased to limit the gain of the driver of mp3 to

around one. In this output stage, mn10 wastes current

during the falling edge. The current is reduced by

making the ratio of �W=L�mn10 to �W/L�mn3 small.

This structure also enables the precharge switch to be

removed, since mp3 can supplies suf®cient current to

the output corresponding to the change in input

voltage of the output stage.

4. Experimental Results

In order to demonstrate the low-power opamp design,

the proposed opamp was fabricated using standard

0.6 mm CMOS technology. A micrograph of the chip

is shown in Fig. 8. The opamp size is 50mm6275 mm.

The measured results are summarized in Table 2.

A quiescent current consumption of 10.1 mA and a

DC gain of more than 70 dB are achieved at


Fig. 5. Frequency responses for CF2=CF1 � 0 to 4 with CL �150 pF.

Fig. 6. Frequency responses for CF2=CF1 � 0 to 4 with CL �10 pF.

Fig. 7. Push-pull output stage.


Vdd � 3 V. Figs. 9 and 10 show the measured

frequency responses when load capacitor CL is

150 pF and 10 pF, respectively. For CL � 10 pF, no

gain peaking is observed; for CL � 150 pF, however,

the phase margin is 39� and is not suf®cient for fast

settling.

Fig. 11 shows the currents supplied from Vdd and to

Vss for CL � 150 pF. These currents were monitored

as voltages across resistors of 510O inserted into the

Vdd and Vss lines. The maximum currents ¯owing

through the Vdd and Vss lines are 130 mA and 160 mA,

respectively, and are well controlled.

Figs. 12 and 13 show the input and output

waveforms. The measured settling times for

CL � 150 pF are 10.2 msec for rising and 5.8 msec

for falling, respectively. These settling times do not

satisfy the target speci®cations because of the

insuf®cient phase margin and smaller rising slew

rate than expected. Fig. 14 shows the waveforms at

the input, at the output, and at the COM node. No

instability is observed in common-inversion opera-


Fig. 8. Chip micrograph.

Table 2. Summary of results.

Parameter CL � 150 pF CL � 10 pF

DC Gain 4 70 dB 4 70 dB

Quiescent current 10.1mA 10.1mA

Unity gain freq. 169 kHz 257 kHz

Phase margin 39� 73�

Current consumption(1) 26.4mA 13.2mA(2) 33.6mA 14.0mA

Settling time(3) (rising) 10.2msec 3.3msec

Slew rate (rising) 0.5 V/msec 1.6 V/msec

Settling time(3) (falling) 5.8msec 3.1msec

Slew rate (falling) 1.5 V/msec 1.6 V/msec

(1) Current consumption was measured for a 30 msec period, 1.5 Vpp

square wave input.

(2) A 30msec period. 3 Vpp square wave was applied to the COM

node.

(3) Settling time is the time for the output to settle down within

+ 5 mV.

Fig. 9. Frequency response �CL � 150 pF�.

Fig. 10. Frequency response �CL � 10 pF�.

Fig. 11. Current monitoring waveform �CL � 150 pF�.


tion. Due to small rising slew rate, an additional time

of about 2 msec is needed for settling, which should be

also reduced by re®ning the circuit and improving the

slew rate.

5. Discussion

The rising slew rate is not limited by the current

source mn13, in the slew rate enhancement circuit, but

rather by the maximum output current of the class AB

output stage. This is due to the limitation of the

maximum gate voltage of mn11, which is bounded by

the gate voltage of mn9. An increase in the gate

voltage of mn9 by increasing the bias current supplied

from mp11 causes a higher quiescent current in the

class AB output stage; the gate voltage of mn9 should

be adaptively controlled. This can be implemented by

the additional transistor mn16 as shown in Fig. 15,

where the current supplied from mp11 is the same as

before adding mn16. �W/L�mn7 and �W/L�mn8 are

reduced to a half, and �W/L�mn16 is the same as

�W/L�mn7. About a half of the current from mp11¯ows into mn8 and mn7; the gate voltage of mn9 is not

increased in the quiescent state and the quiescent

current of the opamp is the same as before introducing

mn16. During the rising edge, mn16 senses the output

voltage of the input stage and supplies current to mn8and mn7. When the input �� rises, the output of the

input stage falls and turns off mn16; then, all the

current from mp11 ¯ows into mn8 and mn7 and the

gate voltage of mn9 goes up.


Fig. 12. Input/output waveform �CL � 150 pF�.

Fig. 13. Input/output waveform �CL � 10 pF�.

Fig. 14. Input/output waveform with common inversion

�CL � 150 pF�.

Fig. 15. Improvement of class AB output stage.


The phase margin can be improved by increasing

the ratio CF2=CF1 without increasing total capaci-

tance. In Fig. 15, the ratio CF2=CF1 is modi®ed from 1

to 1.2. Figs. 16 and 17 show the input and output

waveforms without and with a COM signal as

obtained by simulation. By modifying the ratio

CF2=CF1 and improving the maximum output current

of the class AB output stage, the ampli®er is made

stable and a settling time of 4.5 msec for no common-

inversion operation and of 5.5 msec for common-

inversion operation can be achieved. The quiescent

current is 10 mA. By improving the rising slew rate,

the additional time needed for common-inversion

operation is reduced to 1 msec.

A rail-to-rail input stage is not necessary for driver

ICs using a capacitor array in a digital-to-analog

converter; it is necessary for driver ICs using a

resistive divider in a digital-to-analog converter since

the input amplitude of the opamp is almost rail-to-rail,

i.e. Vdd ÿ Vss. When applying the rail-to-rail input

stage [6], the overall schematic of the opamp is shown

in Fig. 18.

A conventional rail-to-rail circuit such as [5]

cannot be applied as it is, due to the following

problems: (1) the slew rate depends on the common-

mode input voltage; (2) the rail-to-rail input stage

complicates the slew rate enhancing circuit. The rail-

to-rail input stage reported in [6] is suitable. The sum

of the output differential current of the input stage is

constant over the common-mode input range; the slew

rate is independent of the common-mode input

voltage. Only the current source, mp4, needs to be

controlled by the slew rate enhancing circuit; this

requires no additional change for slew rate enhance-

ment in applying the rail-to-rail input stage. The


Fig. 17. Input/output waveform with common inversion

(simulation).

Fig. 16. Input/output waveform (simulation).

Fig. 18. Low-power opamp with rail-to-rail input stage.


additional circuit for the rail-to-rail input stage

consumes around 1 mA.

6. Conclusion

Low-quiescent-current opamp design for an LCD

driver IC has been described. The experimental results

support our opamp design approach and indicate the

feasibility of a 10 mA quiescent current opamp with a

high slew rate and short settling times on both rising

and falling edges.

Acknowledgments

The authors wish to thank T. Maruyama for his

valuable suggestions and support. They are grateful to

Dr. T. Shima and Dr. H. Tanimoto for stimulating

discussion and comments. They also thank the

referees for their careful review and many sugges-

tions.

References

1. T. Omori, O. Sarai, T. Kuno, K. Nishi, J. Iizuka, and H. Kimura,

``Color TFT-LCD driver LSls.'' National Technical Report42(6), pp. 728±735, 1996.

2. R. Klinke, B. J. Hosticka, and H.-J. P¯eiderer, `À very-high-

slew-rate CMOS operational ampli®er.'' IEEE J. Solid-StateCircuits 24(3), pp. 744±746, 1989.

3. K. Nagaraj, ``CMOS ampli®ers incorporating a novel slew rate

enhancement technique.'' Proc. IEEE CICC pp. 11.6.1±11.6.5,

1990.

4. T. Itakura, `À high slew rate operational ampli®er for an LCD

driver IC.'' IEICE Trans. Fundamentals E78-A(2), pp. 191±195,

1995.

5. K. L. Burson, S. H. Early, and A. Ganeasan, CMOS operationalampli®er. US Patent 4554515, 1985.

6. H. Minamizaki, T. Taguchi, T. Itakura, S. Iwamoto, J. Sato, T.

Suyama, and I. Abe, ``Low output offset, 8 bit signal drivers for

XGA/SVGA TFT-LCDs.'' Proc. Euro-Display '96 pp. 247±250,

1996.

7. B. K. Ahuja, `Àn improved frequency compensation technique

for CMOS operational ampli®er.'' IEEE J. Solid-State CircuitsSC-18(6), pp. 629±633, 1983.

8. D. B. Ribner and M. A. Copeland, ``Design techniques for

cascoded CMOS Op amps with improved PSRR and common-

mode input range.'' IEEE J. Solid-State Circuits SC-19(6),

pp. 919±925, 1984.

9. H. Tanimoto, M. Hayashibara, and T. Kato, `À low-voltage

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Proc. IEEE CICC pp. 473±476, 1987.

Tetsuro Itakura received the B.E. degree in

electronics engineering from Tokyo University of

Agriculture and Technology, Tokyo, Japan, in 1981,

and the M.S. degree in electrical engineering from

Stanford University, CA, U.S.A. in 1989. In 1981 he

joined Toshiba Corporation, Kawasaki-shi, Japan. He

has been involved in the design of opamp for LCD

driver ICs and the design of analog ®lter for

telecommunication. His current interests are in

linear MOS circuits and signal processing.

Hironori Minamizaki received the B.E. and M.E.

degrees in electronics engineering from Kumamoto

University, Kumamoto, Japan, in 1984 and in 1986,

respectively. In 1986 he joined Toshiba Corporation,

Kawasaki, Japan. He was involved in the development

of LEDs from 1986 to 1987, and was involved in the

development of electro-luminescence driver LSIs

from 1987 to 1989. Since 1989 he has been engaged

in the development of LCD driver ICs.



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