A mere six years of microprocessor evolution have yielded athree-orders-of-magnitude performance improvement.

Intel Microprocessors-

800)8 to 8086

ntel introduced its first microprocessor in November1971 with the advertisement, "Announcing a New Era inIntegrated Electronics." The fulfillment of this prophecyhas already occurred with the delivery of the 8008 in 1972,the 8080 in 1974, the 8085 in 1976, and the 8086 in 1978.During this time, throughput has improved one-hundred-fold, the price of a CPU chip has declined from $300 to$3, and microcomputers have revolutionized designconcepts in countless applications. They are now enteringour homes and cars.

Each successive product implementation depended on

fabrication innovations, improved architecture, bettercircuit design, and more sophisticated software, and

throughout this development, upward compatibility not

envisioned by the first designers was maintaiped. Here,we will try to provide an insight into the evolutionaryprocess that transformed the 8008 into the 8086 and givedescriptions of the various processors, emphasizing the8086.

Historical setting. In the late 1960's it became clear thatthe practical use of LSI circuits depended on definingchips having

* a high gate-to-pin ratio,* a regular cell structure, and* a large standard part market.

In 1968, Intel Corporation was founded to exploit thesemiconductor menlory market, which uniquely fulfilledthese criteria. Early semiconductor RAM, ROMs, andshift registers were welcomed wherever small memorieswere needed, especially in calculators and CRT terminals.

*Curretntly with Language Resources, Sunnyvale, California.

In 1969, Intel engineers began to study ways ofintegratingand partitioning the control logic functions of thesesystems into LSI chips.At this time, other companies (notably Texas Instru-

ments) were exploring ways to reduce the time needed todevelop custom integrated circuits. Computer-aideddesign of custom ICs was a hot issue then. Custom ICs are

making a comeback today, this time, in the high-volumeapplications that typify the low end of the microprocessormarket.An alternate approach was to think of a customer's

application as a computer system, requiring a. controlprogram, I/O monitoring, and arithmetic routines,rather than as a collection of special-purpose logic chips.Drawing on its strength in memory, Intel partitionedsystems into RAM, ROM, and single controlier chips,i.e., CPUs.

Intel embarked on the design of two customer-sponsored microprocessors-the 4004 for a calculatorand the 8008 for a CRT terminal. The 4004 replaced whatotherwise would have been six customized chips usable byonly one customer. Because the first microcomputer ap-plications were known and easy to understand, instruc-tion sets and architectures were defined in a matter ofweeks. As programmable computers, their uses could beextended- indefinitely.Both microprocessors were complete CPUs on a chip

and had similar characteristics. But because the 4004 wasdesigned for serial BCD arithmetic and the 8008 for 8-bitcharacter handling, their instruction sets differed.The succeeding years saw the evolution that eventually

led to the 8086. Table I summarizes the progression offeatures that took place during these years.

2. 0018-9162/80/1000-0042$00.75 1980 IEEE

Stephen P. Morse,-*Intel Corporation

Bruce W. Raveiel, * Stanley Mazor, and William B. Pohiman

42 COMPUTER

The 8008

Late in 1969, Computer Terminal Corporation (todaycalled Datapoint) contracted Intel to do a pushdownstack chip for a processor to be used in a CRT terminal.Datapoint had intended to build a bit-serial processor in

TTL logic, using shift register memory. Intel counter-proposed that the entire processor be implemented on onechip. This processor was to become the 8008 and, alongwith the 4004, was to be fabricated using PMOS, the then-current memory fabrication technology. Due to the longlead time required by Intel, Datapoint proceeded tomarket the serial processor, and thus compatibility con-

straints were imposed on the 8008.Most of the instruction set and register organization

were specified by Datapoint. Intel modified the instruc-tion set so the processor would fit on one chip and addedinstructions to 'make it more general-purpose. Foralthough Intel was developing the 8008 for a specificcustomer, they wanted to have the option of selling it toothers. And since Intel was using only 16- and 18-pinpackages in those days, they chose to use 18 pins for the8008 rather than design a new package for what was

believed to be a low-volume chip.

8008 instruction set processor. The 8008 processor ar-chitecture is quite simple compared to that of today'smicroprocessors. The data handling facilities provide forbyte data only. The memory space is limited to 16K bytes,and the stack is on the chip and limited to a depth of eight.The instruction set is small but symmetrical, with only afew operand addressing modes available. An interruptmechanism is provided, but there is no way to disable in-terrupts.

Memory and I/O structure. The 8008 addressablememory space consists of 16K bytes. That seemed like alot back in 1970 when memories were expensive and LSIdevices were slow. It was inconceivable in those days thatanybody would want to put more than 16K of this pre-cious resource on anything as slow as a microprocessor.The memory size limitation was imposed by the lack of

available pins. Addresses are'sent out in two consecutiveclock cycles over an 8-bit address bus. Two controlsignals, which would ha-ve been on dedicated pins if suchwere available, are sent out with every address instead,thereby limiting addresses to 14 bits.The 8008 supports eight 8-bit input ports and 24 8-bit

output ports. Each port is directly addressable by the in-

Table 1.Feature comparison-Intel microprocessors, 1972-1978.

80801974

111

5

16K BYTES

8 INPUT24 OUTPUT

16

8*

64K BYTES

256 INPUT256 OUTPUT

40

16

80851976

113

5

64K BYTES

256 INPUT256 OUTPUT

40

16

8

8-BIT UNSIGNED

REGISTERIMMEDIATE**

8-BIT UNSIGNJD16-BIT UNSIGNED

(LIMITED)

PACKED BCD(LIMITED)

MEMORY DIRECT(LIMITED)

MEMORY INDIRECT(LIMITED)

REGISTERIRA KIfln A T* *vi lYI L UI1

*ADDRESS AND DATA BUS MULTIPLEXED.**MEMORY CAN BE ADDRESSED AS A SPECIAL CASE BY USING REGISTER M.

October 1980

8

8-BIT UNSIGNED16-BIT UNSIGNED

(Li M ITED)

PACKED BCD(LIMITED)

MEMORY DIRECT(LIMITED)

MEMORY INDIRECT(LIMITED)

REGISTERIM MEDIATE**

16*

8-BIT UNSIGNED8-BIT SIGNED16-BIT UNSIGNED16-BIT SIGNEDPACKED BCDUNPACKED BCD

MEMORY DIRECTMEMORY INDIRECTREGISTERIMMEDIATEINDEXING

43

80081972

66

4

INTRODUCTIONDATE

NUMBER OFINSTRUCTIONS

NUMBER OFFLAGS

MAXIMUMMEMORY SIZE

I/O PORTS

NUMBER OFPINS

ADDRESS BUSWIDTH

80861978

133

9

1M BYTES

64K INPUT64K OUTPUT

40

20*

8*DATA BUSWIDTH

DATA TYPES

-ADDRESSINGMODES

I/A IL

struction set. The chip's designers felt that output portswere more important than input ports because input portscan always be multiplexed by external hardware undercontrol of additional output ports.One of-the interesting things about that era was that,

for the first time, users were given access to the memorybus and could define their own memory structure; theywere not confined to what the vendors offered, as theyhad been with minicomputers. The user had the option,for example, of putting I/O ports inside the memory ad-dress space instead of in a separate I/O space.

Register structure. The 8008 processor contains tworegister files and four 1-bit flags. The register files are thescratchpad and the address stack.

Scratchpad. The scratchpad file contains an 8-bit ac-cumulator calledA and six additional 8-bit registers calledB,C,D,E,H, and L. All arithmetic operations use the ac-cumulator as one ofthe operands and store the result backin the accumulator. All seven registers can be used inter-changeably for on-chip temporary storage.

There is one pseudoregister, M, which can be used in-terchangeably with the scratchpad registers. M is, in ef-

Saving and restoring flags in the 8008

Interrupt routines must leave all processor flags and registersunaltered so as not to contaminate the processing that was inter-rupted. This is most simply done by having the interrupt routinesave all flags and registers on entry and restore them prior to ex-iting. The 8008, unlike its successors, has no instruction for directlysaving or restoring flags. Thus, 8008 interrupt routines that alterflags (practically every routine does) must conditionally test eachflag to obtain its value and must then save that value. Since thereare no instructions for directly setting or clearing flags, the flagvalues must be restored by executing code that will put the flags inthe saved state.The 8008 flags can be restored very efficiently if they are saved in

a byte in memory in the following format:

7 6 5 4 3 2 1 0

c ls lolo Z I P1most significant bit = bit 7 = original value of CARRY

bit 6 = original value of SIGNbit 5 = original value of SIGNbit 4 = 0bit 3 = 0bit 2 = complement of original value of ZERObit 1 = complement of original value of ZERObit 0 = complement of original value of PARITY

With the formatted information saved in a byte called FLAGS, thefollowing two instructions will restore all the saved flag values:

LDA FLAGS load saved flags into accumulatorADD A add the accumulator to itself

This instruction sequence loads the saved flags into the ac-cumulator and then doubles the value, thereby moving each bit oneposition to the left. This causes each flag to be set to its originalvalue for the following reasons:

* The original value of the CARRY flag, in the leftmost bit, will bemoved out of the accumulator and wind up in the CARRY flag.

* The original value of the SIGN flag, in bit 6, will wind up in bit 7and will become the sign of the result. The new value of theSIGN flag will reflect this sign.

* The complement of the original value of the PARITY flag willwind up in bit 1, and it alone will determine the parity of theresult (all other bits in the result are paired up and have no

net effect on parity). The new setting of the PARI-TY flag will be the complement of this bit (flagdenotes even parity) and therefore will take on theoriginal value of the PARITY flag.

* Whenever the ZERO flag is 1, the SIGN flag mustbe 0 (zero is a positive 2's-complement number)and the PARITY flag must be 1 (zero has evenparity). Thus, an original ZERO flag value of 1 willcause all bits of FLAGS, with the possible excep-tlon of bit 7, to be 0. After the execution of theADD instruction, all bits of the result will be 0 andthe new value of the ZERO flag will therefore be 1.

* An original ZERO flag value of 0 will cause twobits in FLAGS to be 1 and will wind up in the resultas well. The new value of the ZERO flag willtherefore be 0.

The above algorithm relies on consistent flagvalues; i.e., the SIGN flag cannot be a 1 when the ZEROflag is a 1. This is always true in the 8008, since theflags come up in a consistent state whenever the pro-cessor is reset and since flags can be modified only byinstructions which always leave the flags in a consis-tent state. The 8080 and its derivatives allow the pro-grammer to arbitrarily modify the flags by popping avalue of his choice off the stack and into the flags.Thus, the above algorithm will not work on those pro-cessors.

A code sequence for saving the flags in the requiredformat is as follows:

MVI A,0 move zero in accumulatorJNC Li ; jump if CARRY not setORA 80H OR accumulator with 80H hex

(set bit 7)Li: JZ L3 ; jump if ZERO set (and SIGN

not set and PARITY set)ORA 06H OR accumulator with 03 hex

(set bits 1 and 2)JM L2 jump if negative (SIGN set)ORA 60H ; OR accumulator with 60 hex

(set bits 5 and 6)L2: JPE L3 ; jump if parity even (PARITY set)

ORA 01 H OR accumulator with 01 hex(set bit 0)

L3: STA FLAGS store accumulator in FLAGS

44 COMPUTER~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~..rL i.

44 COMPUTER

fect, that particular byte in memory whose address is cur-rently contained in H and L (L contains the eight low-order bits of the address andH contains the six high-orderbits). Thus, M is a byte in memory and not a register;although instructions addressM as if it were a register, ac-cesses to M actually involve memory references. The Mregister is the only mechanism by which data in memorycan be accessed.Address stack. The address stack contains a 3-bit stack

pointer and eight 14-bit address registers providingstorage for eight addresses. The programmer cannotdirectly access these registers; instead, he manipulatesthem with control-transfer instructions.Any one of the eight address registers in the address

stack can serve as the program counter; the current pro-gram counter is specified by the stack pointer. The otherseven address registers permit storage for nesting ofsubroutines up to seven levels deep. The execution of acall instruction causes the next address register to becomethe current program counter, and the return instructioncauses the address register that last served as the programcounter to again become the program counter. The stackwill wrap around if subroutines are nested more thanseven levels deep.

Flags. The four flags in the 8008 are CARRY, ZERO,SIGN, and PARITY. They reflect the status of the latestarithmetic or logical operation. Any flag can be used toalter program flow through the use of the conditionaljump, call, or return instructions. There is no directmechanism for saving or restoring flags, which places asevere burden on interrupt processing (see box at left fordetails).The CARRY flag indicates if a carry-out or borrow-in

was generated, thereby providing a multiple-precisionbinary arithmetic capability.The ZERO flag indicates whether or not the result is

zero. This provides the ability to compare two values forequality.The SIGN flag reflects the setting of the leftmost bit of

the result. The presence of this flag creates the illusionthat the 8008 is able to handle signed numbers. However,there is no facility for detecting signed overflow on addi-tions and subtractions. Furthermore, comparing signednumbers by subtracting them and then testing the SIGNflag will not give the correct result if the subtractionresulted in signed overflow. This oversight was not cor-rected until the 8086.The PARITY flag indicates whether the result is ofeven

or odd parity. This permits testing for transmission er-rors, an obviously useful function for a CRT terminal.

Instruction set. The 8008 instructions are designed formoving or modifying 8-bit operands. Operands are con-tained in the instruction itself (immediate operand), in ascratchpad register (register operand), or in theM register(memory operand). Since the M registers can be used in-terchangeably with the scratchpad registers, there are on-ly two distinct operand addressing modes-immediateand register. Typical instruction formats for these modesare shown in Figure 1.The instruction set consists of scratchpad-register in-

of-control instructions, input/output instructions, andprocessor-control instructions.The scratchpad-register instructions modify the con-

tents of theM register or any scratchpad register. This can

NO OPERANDS

OPCODE

ONE OPERAND

OPCODE REG OPERAND IN REGISTER

OPC REG OPCOD IOPERAND IN REGISTER

OCRP |OPODE OPERANDINREGISTERPAIR(80800NLY)

LOPCI RP | OPCODE |INDIRECTADDRESSING(8080ONLY)

OPCODE DATA IMMEDIATE OPERAND

DIRECTF 1FPCOD||ADDR-LO IE ADDR 1X|(800ADDRESSINGJ OPjjjE [ ADDRLO ,jj ADDR-H1j (8080

ONLY)

TWO OPERANDS

OPC REG REG BOTH OPERANDS IN REGISTER

OPC I REG OPC DATA ONE OPERAND IN REGISTER,L2IIILJ ~ OTHER IS IMMEDIATE OPERANDONE OPERAND

1 9 1 0 1 I f I IN REGISTER~~~~~~~~~ ~~~~~~~~PAIR, OTHEROPCIRPOPCODEDATA-LO t 'DATA-Hi' IS IMMEDIATE

OPERAND(8080 ONLY)

INPUT/OUTPUT

OPC PORT (8008 ONLY)

0 OPCODE |I PORT 1(80800NLY)JUMPS AND CALLS

OPCODE ADDR-LO I ADDR-HI (8008ONLY)

OPCODE ADDR-LO ADDR-HI (8080ONLY)

8008OO0:A001:B010:C

REG = 011:D100:E101:H1 10:L111:M

8080000:8001:C010:D

REG = 011:E100: H101:L110:M1 1 1:A

8080

00:8CRP = 01:DE

10:HL11 SP

structions, accumulator-specific instructions, transfer-- Figure 1. Typical 8008 and 8080 instruction formats.

October 1980 45

involve moving data between any two registers, movingimmediate data into a register, or incrementing ordecrementing the contents of a register. The incrementingand decrementing instructions were not in Datapoint'sspecified instruction set; they were added by Intel to pro-vide for loop control, thereby making the processor moregeneral-purpose.Most of the accumulator-specific instructions perform

operations involving the accumulator and a specifiedoperand. The operand can be any one of the scratchpadregisters, including M, or it can be immediate data. Theoperations are add, add-with-carry, subtract, subtract-with-borrow, logical AND, logical OR, logical exclusive-OR, and compare. Furthermore, there are four unit-rotate instructions that operate on the accumulator.These instructions perform either an 8- or 9-bit rotate (theCARRY flag acts as a ninth bit) in either the left or rightdirection.

Transfer-of-control instructions consist of jumps,calls, and returns. Any transfer can be unconditional, orconditional based on the setting of any one of the fourflags. Making calls and returns conditional was done onlyto preserve the symmetry with jumps. A short one-byte

form of call-which will be discussed with interrupts-isalso provided.Each jump and call instruction (with the exception of

the one-byte call) specifies an absolute code address in thesecond and third byte of the instruction. The second bytecontains the six high-order bits of the address and thethird byte the eight low-order bits. This inverted storage,which was to haunt all processors evolved from the 8008,was a result of a need for compatibility with the Datapointbit-serial processor, which processes addresses from lowbit to high bit. This inverted storage did have a virtue inthose early days when 256 x 8 memory chips were popular:It allowed all memory chips to select a byte and latch it foroutput while waiting for the six high-order bits whichselected the chip. This speeded up memory access.

There are eight input and 24 output instructions usingup 32 opcodes. Each I/O instruction transfers a byte ofdata between the accumulator and a designated I/O port.The processor-control instructions are halt and no-op.

Halt puts the processor into a waiting state. The processorremains in that state until an interrupt occurs. No-op isactually one of the move instructions; specifically, itmoves the contents of the accumulator into the ac-cumulator, thereby having no net effect (move instruc-tions do not alter flag settings).

Interrupts. Interrupt processing was not a requirementfor the 8008. Hence, only the most primitive mechanismconceivable-not incrementing the program counter-was provided. Such a mechanism permits an interruptingdevice to jam an instruction into the processor's instruc-tion stream. This is accomplished by having the interrupt-ing device, instead of memory, respond to the instructionfetch; since the program counter isn't incremented, theinstruction in memory that didn't get fetched won't beskipped. The instruction typically supplied by the inter-rupting device is a call, so that an interrupt service routinecan be entered and then the main program can be resumedafter interrupt processing is complete (a jump instructionwould result in the loss of the main program return ad-dress). To simplify the interrupting device's task ofgenerating an instruction, the 8008 instruction set pro-vides eight one-byte subroutine calls, each to a fixed loca-tion in memory.

There are no instructions for disabling the interruptmechanism; thus, this function must be realized with ex-ternal hardware. More important, there are no instruc-tions for conveniently saving the registers and flags whenan interrupt occurs.

The 8080

By 1973, memory fabrication technology had ad-vanced from PMOS to NMOS. As an engineering exer-cise, Intel decided to use the 8008 layout masks with theNMOS process to obtain a faster 8008. After a shortstudy, the company determined that a new layout was re-quired. It therefore decided to enhance the processor atthe same time and to utilize the new 40-pin package madepractical by high-volume calculator chips. The result wasthe 8080 processor.

COMP-UTER

In a1;e «egtnnin.

3in the beginnring Intel created the 4004 and the 8008. Arid theseprocessors were without enough memory and throughput. And In-tel said, "Let there be an 8080," and there was an 8080 and Intel'sawthat it was good. And Intel separated the 8008 market from the 8080market.-ind Intel said-, "Let there be an 8085 with an oscillator on the

same chip as the processor, and let an on-chip systerm controllerseparate the data from the control. lines. And Intei made a firma-ment ahd divided the added instructions which were under the fir-mament from the added instructions which wereabove the firma-ment. And Intel called the first set of instructions RIM and SIM.And the other instructions Intel never announced.

Ziard Intel said, "Let the market below the 8085 market be servedwith a processor and let on-chip ROM appear." And Intel called thenew processor the 8048. And the market it served Intel called thelow end. And Intel saw that it was good.Zind Intel said, "Let a new-generation processor serve the mid-

range market. And let there be true 16-bit facilities in the mid-range.And let there be one megabyte of memory and efficient interrupt'-ible byte-string instructions: and full decimal arithmetic."-And Intelsaw the collection of all these things, that it was good, and Intelcalled it the 8086.

ind Intel said, "Now let us make a processor in our image, afterour likeness, and let it have dominion over the high-end market."So Intel created the APX 432 in his own image, in the image of Intelcreated he it, data processor and IIO processor created he them.And Intel blessed them and said unto them be fruitful andmultiprocess and revolutionize the microprocessor market andhave dominion over the Z8000 and the M68000 and over every com-petitor that enters the market.Zind Intel saw everything that he had made and, behold, it was

good.

-S.P. Morse

r

L

46

The 8080 was the first processor designed specificallyfor the microprocessor market. It was constrained to in-clude all the 8008 instructions, but not necessarily with thesame encodings. This meant that a-user's software wouldbe portable, but that the actual ROM chips containing theprograms would have to be replaced. The main objectiveof the 8080 was to obtain a ten-to-one improvement inthroughput,- eliminate many of the 8008 shortcomingsthat had by then become apparent, and provide new pro-cessing capabilities not found in the 8008. The latter in-cluded handling of 16-bit data types (mainly for addresscomputations), BCD arithmetic, enhanced operand ad-dressing modes, and improved interrupt processing.Memory costs had come down and processing speed wasapproaching TTL, so larger memory spaces seemed morepractical. Hence, another goal was direct addressing ofmore than 16K bytes. Symmetry was not a goal becausethe benefits to be gained from making the extensions symn-metric would not have justified the resulting increase inchip size and opcode space.

The 8080 instruction set processor. The 8080 architec-ture is an unsymmetrical extension of the 8008. The bytehandling facilities are augmented with a limited numberof 16-bit facilities. The memnory space is 64K bytes and thestack is virtually unlimited.

Various alternatives for the 8080 were considered. Thesimplest involved merely adding a memory stack andstack instructions to the 8008. An intermediate strategywas to augment the above with 16-bit arithmetic facilitiesthat could be used for explicit address manipulation aswell as for 16-bit data manipulation. The most difficultalternative involved a symmetric extension which re-placed the one-byte M-register instructions with three-byte generalized memory access instructions. The last twobytes of tfiese instructions contained two address modebits specifying indirect addressing and indexing (using HLas an index register) and a 14-bit displacement. Althoughthis would have been a more versatile addressingmechanism, it would have resulted in significant code ex-pansion on existing 8008 programs. Furthermore, thelogic needed to implement this solution would haveprecluded 16-bit arithmetic; such arithmetic would nothave been needed for address manipulations under thisenhanced addressing facility, but would still have beendesirable for data manipulations. For these reasons, theintermediate approach was finally taken.

of inverted storage already noted in thetransfer instruc-tions of the 8008.The 8080 extends the 32-port capacity ofthe-8008 to256

input ports and 256 output ports. Here, the 8080 is actual-ly miore symmetrical than the 8008. Like the 8008, the8080 instruiction set can directly address all the ports.

-egister structure. The 8080 processor contains a file ofseven 8-bit general registers, a 16-bit program counter(PC) and stack pointer (SP), and five l-bit flags. A com-parison between the 8008 and 8080 register sets is showninFigure 2.-

General registers. The 8080 registers are the same seven8-bit registers that were in the 8008 scratchpad-namely,A,EBC,D,E,H, and L. In order to incorporate 16-bit data

SCRATCHPAD

7 0

ADDRESS STACK

13

8080

GENERAL REGISTERS

'A

B C

D E

H L

A

B

c

D

E -

-HLL:

STACK POINTER AND PROGRAM COUNTER

15 0

15 0

PC.w .~~~~~~~~~~~~~~~~~~~~~~~~~~~

FLAGS

7 0

LELEEWII

Memory and I/O structure. The 8080 can address pi to _ _ _64K bytes of memory, a four-fold increase over the 8008-(the 14-bit address stack of the 8008 was eliminated). Theaddress bus of the 8080 is 16- bits wide (in contrast to eightbits--for the 8008), so an entire address can be sent downFLAGSthe bus in one memory cycle. Although the data handlingfacilities of the 8080 are primarily byte-oriented (the 8008was exclusively byte-oriented), certain operations permittwo consecutive bytes of memory to be treated as a singledata item..The two bytes are called a word. The data busof the 8080 is only eight bits wide, and hence, word ac-cesses require an extra memory cycle.The most significant eight bits of a word are located at

the higher memory address. This results in the same kind Figure 2. 8008 and 8080 registers.

2 0.

_ ,. . ...

October1980

7

A

8008

7 0 7 0

47

facilities in the 8080, certain instructions operate on theregister pairs BC, DE, and HL.The seven registers can be used interchangeably for on-

chip temporary storage. The three register pairs are usedfor address manipulations, but their roles are not inter-changeable; there is an 8080 instruction that allows opera-tions on DE and not BC, and there are address modes thataccess memory indirectly through- BC or DE but notthrough HL.As in the 8008, the A register has a unique role in

arithmetic and logical operations: It serves as one of theoperands and is the receptacle for the result. The HLregister again has its special role of pointing to thepseudoregister M.

Stack pointer and program counter. The 8080 has a

single program counter instead of the floating programcounter of the 8008. The program counter is 16 bits (twobits more than the 8008's program counter), thereby per-mitting an address space of 64K.The stack is contained in memory instead of on the

chip, a strategy which removes the restriction of onlyseven levels of nested subroutines. The entries on thestack are 16 bits wide. The 16-bit stack pointer is used tolocate the stack in memory. The execution of a call in-struction causes the contents of the program counter to bepushed onto the stack, and the return instruction causesthe last stack entry to be popped into the programcounter. The stack pointer was chosen to run "downhill"

Decimal arithmetic

Packed BCD

Addition. Numbers can be represented as a sequence of decimaldigits by using a 4-bit binary encoding of the digits and packingthese encodings two to a byte. Such a representation is calledpacked BCD (unpacked BCD would contain only one digit per byte).In order to preserve this decimal interpretation when performingbinary addition on packed BCD numbers, the value 6 must be addedto each digit of the sum whenever (1) the resulting digit Is greaterthan 9, or (2) a carry occurs out of this digit as a result of the addi-tion. This must be done because the 4-bit encoding contains sixmore combinations than there are decimal digits. Consider thefollowing examples (for convenience, numbers are written in hex-adecimal instead of in binary):

Example 1: 81 + 52

d2 dl dO8 1

+ 5 2D 3

names of digit positionspacked BCD augendpacked BCD addend

+ 6 adjustment because dl greater than 9

1 3 3 packed BCD sum

Example 2: 28 + 19

d2 dl dO names of digit positions2 8 packed BCD augend

+ _ 1 9 packed BCD addend4 1 carry occurred out of dO

+ 6 adjustment for above carry4 7 packed BCD sum

For such adjustments to be made, carries out of either digit posi-tion must be recorded during the addition operation. The 4004,8080, 8085, and 8086 use the CARRY and AUXILIARY CARRY flagsto record carries out of the leftmost and rightmost digits, respec-tively. All these processors provide an instruction for performingthe adjustments. Furthermore, they all contain an add-with-carry in-struction to facilitate the addition of numbers containing more thantwo digits.

Subtraction. Subtraction of packed BCD numbers isperformed in a similar manner. However, none of theIntel processors prior to the 8086 provides an instruc-tion for performing decimal adjustment following asubtraction (Zilog's Z-80, introduced two years beforethe 8086, has such an instruction). On processorswithout the subtract adjustment instruction, subtrac-tion of packed BCD numbers is accomplished bygenerating the 10's complement of the subtrahendand adding.

Multiplication. Multiplication of packed BCDnumbers can also be adjusted to give the correctdecimal result if the out-of-digit carries occurring dur-ing the multiplication are recorded. The result ofmultiplying two one-byte operands is two bytes long(four digits); out-of-digit carries can occur on any of thethree low-order digits, all of which must be recorded.Furthermore, the carries out of any digit are no longerrestricted to unity, so counters rather than flags are re-quired to record the carries. This is illustrated in thefollowing example (again, numbers are written in hex-adecimal instead of in binary):

Example 3: 94 * 63

d3 d2 dl dO names of digit positions9 4 packed BCD multiplicand

* 6 3 packed BCD multiplier1 B C

3 7 8

3 9 3 C+ 6 6+ 6 6+ _ 6 _

4 C 5 C

+ 6 6

5 2 B C+ 6

5 8 B C+ 6

5 80C2

carry occurred out of dlcarry occurred out of dl,three out of d2carry occurred out of dladjustment for ...

... above six . ..

... carries

carry occurred out of dl andout of d2adjustment for above twocarries

carry occurred out of d2adjustment for above carry

adjustment because dO isgreater than 9

48 OMPTE

I

LCOMPUTER48

(with the stack advancing toward lower memory) to below for details). This facility can be traced back to thesimplify both indexing into the stack from the user's pro- 4004 processor. AUXILIARY CARRY has no purposegram (positive indexing) and displaying the contents ofthe stack from a front panel.The programmer can directly access the stack pointer in

the 8080, unlike that in the 8008. Furthermore, the stackitself is directly accessible, and instructions are providedthat permit the programmer to push and pop his own16-bit items onto the stack.

Flags. A fifth flag, AUXILIARY CARRY, augmentsthe 8008 flag set. AUXILIARY CARRY indicateswhether a carry was generated out of the four low-orderbits. This flag, in conjunction with a decimal-adjust in-struction, makes possible packed BCD addition (see box

other than BCD arithmetic, and hence the conditionaltransfer instructions were not expanded to include testson the AUXILIARY CARRY flag.

It was proposed too late in the design that the PARITYflag double as an OVERFLOW flag. Although thisfeature didn't make it into the 8080, it did show up twoyears later in Zilog's Z-80.

Instruction set. The 8080 includes the entire 8008 in-struction set as a subset. The added instructions providesome new operand addressing modes and some 16-bitdata manipulation facilities. These extensions have in-

6 adjustment because dl isgreater than 9

5 9 2 2 packed BCD product

The most significant digit of the most significant byte is 1, in-dicating that there was one out-of-digit carry from the low-orderdigit when the 9*2 term was formed. The adjustment is to add 6 tothat digit.

This example illustrates two facts. First,BCD multiplication adjustments are possiblinecessary out-of-digit carry information is recothe multiply instruction. Second, the facilitiescessor needs to record this information and a,:correction are nontrivial.Another approach to determining the out-

carries is to analyze the multiplication procedigit-by-digit basis:

let xl and x2 be packed BCD digits in multiplilet yl and y2 be packed BCD digits in multipli

binary value of multiplicand = 16*xl + x2binary value of multiplier = 16*yl + y2

binary value of product = 256*xl *y1 + 16*(xx2*yl) + yl*y2

= xl *yl in most signibyte,yl *y2 in least signilbyte,(xl*y2 + x2*yl).strboth bytes

If there were no cross terms (i.e., xl or y2 is zix2 or yl is zero), the number of out-of-digitgenerated by the xl *y1 term is simply the mostcant digit in the most significant byte of the pSimilarly, the number of out-of-digit carries-gerby the yl *y2 term is simply the most significain the least significant byte of the product. Thlustrated in the following example:

Example 4: 90 * 20

d3 d2 dl dO

9 0

2 0

0 0 0

1 2 0

1 2 0 0

9*2 0* 0

names of digit posil

packed BCD'multiplpacked BCD multipl

packede if therded bythe pro-pply the

-of-digitss on a

cand

1*y2 +

ficant

1 2 0 0+ 6

1 8 0 0adjustmentpacked BCD product

So, in the absence of cross terms, the number of out-of-digit car-ries occurring during a multiplication can be determined by examin-ing the binary product. The cross terms, when present, overshadowthe out-of-digit carry information in the product, thereby makingsome other carry-recording mechanism essential. None of the Intelprocessors incorporate such a mechanism. (Prior to the 8086,multiplication itself was not even supported.) Having decided notto support packed BCD multiplication in the processors, Intekdesigners made no attempt to analyze packed BCD division.

Unpacked BCD

ficant Unpacked BCD representation of numbers consists of storingicant the encoded digits in the low-order four bits of consecutive bytes.

string digits isaspecial unpacked BCD,high-order four bits of each byte containing 0110.

Arithmetic operations on numbers represented as unpackedero and BCD digit strings can be formulated in terms of more primitive BCDcarries operations on single digit (dividends and products are two digits)signifi- unpacked BCD numbers.roduct. Addition and subtraction. Primitive unpacked additions and sub-nerated tractions follow the same adjustment procedures as packed addi-nt digit tions and subtractions.lis is il- Multiplication. Primitive unpacked multiplication involves

multiplying a one-digit (one-byte) unpacked multiplicand by a one-digit (one-byte) unpacked multiplier to yield a two-digit (two-byte)unpacked product. If the high-order four bits of the multiplicandand multiplier are zero (instead of don't cares), the multiplicand as

tions well as the multiplier represent the same value interpreted as a

licand binary number or as a BCD number. A binary multiplication yields alier two-byte product, with the high-order byte being zero. The low-

order byte of this product has the correct value when interpreted asa binary number; that byte can be adjusted to a two-byte BCDnumber as follows:

high-order byte = binary product / 10low-order byte = binary product modulo 10

Continued on overleafOctober 1980 49~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

+

October 1980 49

troduced a good deal of asymmetry. Typical instruction structions, expanded I/O instructions, and interrupt in-formats are shown in Figure 1. structions.The 8080 can access operands in memory only via theM The load/store instructions load and store the ac-

register. The 8080 has certain instructions that access cumulator register and the HL register pair, using thememory by specifying the memory address (direct ad- direct and indirect addressing mode. Both modes can bedressing) and also certain instructions that access memory used for the accumulator but, due to chip size constraints,by specifying a pair of general registers in which the only the direct mode was implemented for HL.memory address is contained (indirect addressing). In ad-dition, the 8080 includes the register and immediate The register-pair instructions provide for theoperand addressing modes of the 8008. A 16-bit im- manipulation of 16-bit data items. Specifically, registermediate mode-is also included. pairs can be loaded with 16-bit immediate data and in-The added instructions can be classified as load/store cremented, decremented, added to HL, pushed on the

instructions, register-pair instructions, HL-specific in- stack, or popped off the stack. Furthermore, the flag set-structions, accumulator-adjust instructions, carry in- tings themselves can be pushed and popped, thereby

Cont'd from p.49

This is illustrated by the following: 0 70 3

Example 5: 7 * 5

dl dO0 70 52 3

2 30 A0 3

2modulo. 0

o

names of digit positions

unpacked BCD multiplicandunpacked BCD multiplierbinary product

binary productadjustment for high-order byte (/10)'unpacked BCD product (higher-order byte)

3 binary productA adjustment for low-order byte (modulo 10)5 unpacked BCD product (low-order byte)

Division. Primitive unpacked division involves dividing a two-digit (two-byte) unpacked dividend by a one-digit (one-byte) un-packed divisor to yield a one-digit (one-byte) unpacked quotient anda one-digit (one-byte) unpacked remainder. If the high-order fourbits' in each byte of the dividend are zeroes (instead of don't cares),the dividend can be adjusted to a one-byte binary number:

binary dividend = 10 * high-order byte + low-order byte

If the high-order four bits of the divisor are zero, the divisorrepresents the same value interpreted as a binary number or as aBCD number. A- binary division .of the adjusted (binary) dividendand BCD divisor yields a one-byte quotient and a one-byte re-mainder, each representing the same value interpreted as a binarynumber or as a BCD number. This is illustrated by the following:

Example 6: 45/6

dl dO names of digit positions0 4 unpacked BCD dividend

(high-order byte)0 5 unpacked BCD dividend

(low-order byte)

2 D adjusted dividend (4*10+5)0 6 unpacked BCDdivisor

unpacked BCD quotientunpacked BCD remainder

Adjustment instructions. The 8086 processor pro-vides four adjustment. instructions for performingprimitive unpacked BCD arithmetic-one for addition,one for subtraction, one for multiplication, and one fordivision.The addition and subtraction adjustments are per-

formed on a binary sum or difference assumed to beleft in the one-byte AL register. Whenever AL is alteredby the addition or subtraction adjustments, the ad-justments will also do the following to facilitatemultidigit arithmetic:

* set the CARRY flag (this facilitates multidigit un-packed additions and subtractions) and

* consider the one-byte AH register to contain thenext most significant digit, and increment ordecrement it as appropriate (this permits theaddition adjustment to be used in a multidigit un-packed multiplication).

The multiplication adjustment assumes that ALcontains a binary product and places-the two-digit un-packed BCD equivalent in AH and AL. The divisionadjustment assumes that AH and AL contain a two-digit unpacked BCD dividend and-places the binaryequivalent in AH and AL.The following al.gorithms show how,the adjustment

instructions can be used to perform multidigit un-packed arithmetic.

ADDITION

let augend = a(N]a[N-11 .. . a[2]a(1llet addend = b[N] b[N - 11 . . . b[21 b[l]let sum = c[NJ c[N - 11 ... c[2] c1]

0 - >(CARRY)DO i = 1 to N

(a[i]) -> (AL)(AL) + (b[i]) ->(AL)

where "+ " denotes add-with-carryadd-adjust (AL) -> (AX)(AL) - > (c[i])

COMPUTER,50

simplifying saving the environment when interrupts occur(this was not possible in the 8008).

The HL-specific instructions include facilities fortransferring HL to the program counter or to the stackpointer, and for exchanging HL with DE or with the topentry on the stack. The last of these instructions was in-cluded to provide a mechanism for (1) removing asubroutine return address from the stack so that passedparameters can be discarded, or (2) burying a result-to-bereturned under the return address. This became thelongest instruction in the 8080 (five memory cycles); itsimplementation precluded the inclusion of several otherinstructions already proposed for the processor.

SUBTRACTION

let minuendlet subtrahendlet difference

= aNa[N - 1] ... a[2J a[1]= b[N] b[N-1 ] ... b[21 b[1]= c[N] c(N-1] ... c[2] c [1 ]

0 - > (CARRY)DO = 1 to N

(all]) - >(AL)(AL) - (b[i) ->(AL)

where denotes subtract-with-borrowsubtract-adjust (AL) - > (AX)(AL) - > (c[i])

MULTIPLICATION

let multiplicand = a[N]a[N-11] a[2]a[1]let multiplier = blet product = c[N +,11 c[N] ... c[2] c(1]

(b) AND OFH - > (b)0 -> (c[1I])DO i = 1 to N

(a[i]) AND OFH - > (AL)(AL) * (b) - > (AX)multiply-adjust (AL) -> (AX)(AL) + (c[i]) ->(AL)add-adjust (AL) -> (AX)(AL) - > (c[i])(AH) - > (c[i + 1])

DIVISION

let dividendlet divisorlet quotient

= a[N] a[N - 1] ... a[2J a[1 ]= b= c[N] c[N -1] .. c[2] c[l]

(b) and OFH - > (b)0 -> (AH)DO i = N to 1

(a[i]) AND OFH - > (AL)divide-adjust (AX) -> (AL)(AL) I (b) - > (AL)

with remainder going into (AH)(AL) -> (cli])

Two accumulator-adjust instructions are provided.One complements each bit in the accumulator, and theother modifies the accumulator so that it contains the cor-rect decimal result after a packed BCD addition is per-formed.The carry instructions provide for setting or com-

plementing the CARRY flag. No instruction is providedfor clearing the CARRY flag. Because of the way theCARRY flag semantics are defined, the CARRY flag canbe cleared simply by ORing andANDing the accumulatorwith itself.The expanded I/O instructions permit the contents of

any one of 256 8-bit ports to be transferred either to orfrom the accumulator. The port number is explicitlystated in the instructions; hence, the instruction is twobytes long. The equivalent 8008 instruction is only onebyte long. This is the only instance in which an 8080 in-struction requires a different number of bytes than its8008 counterpart. The 8080's designers did this more tofree up 32 opcodes than to increase the number of I/Oports.The 8080 has an interrupt mechanism identical to that

of the 8008 but includes instructions for enabling ordisabling the mechanism. This feature, along with theability to push and pop the processor flags, makes the in-terrupt mechanism practical.

The 8085

In 1976 advances in technology allowed Intel to con-sider enhancing the 8080. The objective was a processorset utilizing a single power supply and requiring fewerchips (the 8080 required both an oscillator chip and asystem controller chip). The new processor, called the8085, was constrained to be compatible with the 8080 atthe machine-code level. This meant that extensions to theinstruction set could use only the 12 unused opcodes ofthe 8080.

Architecturally, the 8085 turned out to be not muchmore than a repackaging of the 8080. The major dif-ferences' were added features such as an on-chiposcillator, power-on reset, vectored interrupts, decodedcontrol lines, a serial I/O port, and a single power supply.Two new instructions, RIM and SIM, were added tohandle the serial port and the interrupt mask. Severalother instructions that had been included were never an-nounced because of their ramifications on the 8085 sup-port software and because of the compatibility con-straints they would have placed on the forthcoming 8086.

The 8086

The 8086 was designed to provide an order-of-magnitude increase in processing throughput over the8080. The processor was to be compatible with the 8080 atthe assembly language level, so that existing 8080 softwarecould be reassembled and correctly executed on the 8086.To allow for this, the 8080 register and instruction setswere to appear as logical subsets of the 8086 registers andinstructions. By utilizing a general-register structure, In-

October1980 51

tel could capitalize on its experience with the 8080 to ob-tain a processor with a higher degree of sophistication.Strict 8080 compatibility, however, was not attempted,especially in areas where it would have compromised thefinal design.The goals of the 8086 architecture were the symmetric

extension of existing 8080 features and the addition ofprocessing capabilities not found in the 8080. Newfeatures and capabilities included 16-bit arithmetic,signed 8- and 16-bit arithmetic (including multiply anddivide), efficient interruptible byte-string operations, im-proved bit-manipulation facilities, and mechanisms toprovide for re-entrant code, position-independent code,

Figure 3. Addressing one million bytes requires a 20-bit memory ad-dress. This 20-bit address is constructed by offsetting the effective ad-dress four bits to the right of the segment address, filling in the fourlow-order bits of the segment address with zeroes, and then adding thetwo.

and dynamically relocatable programs.By now memory had become inexpensive and micro-

processors were being used in applications requiring largeamounts of code and data. Thus, another design goal wasdirect addressing of more than 64K bytes and support ofmultiprocessor configurations.

The 8086 instruction set processor. The 8086 processorarchitecture comprises a memory structure, a registerstructure, an instruction set, and an external interface.The 8086 can access up to one million bytes of memoryand up to 64K input/output ports. The 8086 has three filesof registers. One file contains general registers that holdintermediate results; the second contains pointer and in-dex registers used to locate information within specifiedportions of memory; the third contains segment registersused to specify these portions of memory. The 8086 hasnine flags that are used to record the state ofthe processorand to control its operations.The 8086 instruction set and addressing modes are

richer and more symmetric than the 8080. And the 8086external interface, consisting of such things as interrupts,multiprocessor synchronization, and resource sharing,goes way beyond the facilities provided in the 8080.

Memory structure. The input/output space and thememory space of the 8086 are treated in a parallel fashionand are collectively called the memory structure. Codeand data reside in the memory space whereas (non-memory-mapped) peripheral devices reside in the l/Ospace.

Memory space. The memory in an 8086 system is a se-quence of up to one million bytes (a 64-fold increase overthe 8080). An 8086 word is any two consecutive bytes inmemory. Like the 8080, words are stored in memory withthe most significant byte at the higher memory address.The data bus of the 8086 is 16 bits wide, so, unlike the8080, a word can be accessed in one memory cycle(however, words starting at odd byte addresses still re-quire two memory cycles).

Since the 8086 can address up to one megabyte ofmemory, it would seem that, within the 8086 processor,byte and word addresses must be represented as 20-bitquantities. But the 8086 was designed to perform 16-bitarithmetic, and thus the address objects it manipulatescan only be 16 bits in length. An additional mechanism istherefore required to build addresses. The one-megabytememory can be conceived of as an arbitrary number ofsegments, each containing at most 64K bytes. The startingaddress of each segment is evenly divisible by 16. In otherwords, the four least significant bits of each segment'sstarting address are 0. At any moment, the program canimmediately access the contents of four suchsegments-the current code segment, the current datasegment, the current stack segment, and the current extrasegment. Each of these segments can be identified by plac-ing the 16 most significant bits of the segment starting ad-dress into one of the four 16-bit segment registers. By con-trast, the 8080 memory structure is simply the 8086memory structure with all four of the current segmentsstarting at 0.

52 COMPUTER

An 8086 instruction can refer to bytes or words within asegment by using a 16-bit offset address within a 64K-bytesegment. The processor constructs the 20-bit byte or wordaddress by adding the. 16-bit offset address to the contentsof a 16-bit segment register, with four low-order zeroesappended (Figure 3).

Various alternatives for extending the 8080 addressspace were considered. One such alternative consisted ofappending eight rather than four low-order zero bits tothe contents of a segment register, thereby providing a

24-bit physical address capable of addressing up to 16megabytes of memory. This was rejected because

* segments would be forced to start on 256-byteboundaries, resulting in excessive memory fragmen-tation,

* the four additional pins that would be required werenot available, and

* the designers felt that a one megabyte address spacewas sufficient.

Figure 4. The 8080 registers as a subset of the 8086

registers.

October 1980

Input/output space. The 8086 I/O space consists of64K ports (a 256-fold increase over the 8080). Ports are

addressed in the same manner that memory bytes or

words are addressed, except that there are no port seg-

mnent registers. In other words, all ports are considered tobe in one segment. Like memory, ports maybe 8 or 16 bitsin size.The first 256 ports are directly addressable (address in

the instruction), whereas all 64K ports are indirectly ad-dressable (address in a register). Such indirect addressingpermits consecutive ports to be accessed in a program

loop.

Register structure. The 8086 processor contains a totalof thirteen 16-bit registers and nine 1-bit flags. Fordescriptive purposes; the registers are subdivided intothree files of four registers each. The thirteenth register,namely the instruction pointer (called the program

counter in the earlier processors), is not directly accessibleto the programmer; it is manipulated with control,transfer instructions. The 8080 register set is a subset ofthe 8086 register set (Figures 4 and 5). In order to unify the

Figure 5. The 8086 register structure.

53

GENERAL REGISTERS

7 0 7 0

- AHL: H L

BC B C

DE1D E

POINTER AND INDEX REGISTERS

15 0

SP

SEGMENT REGISTERS

1 5 0

INSTRUCTION POINTER AND FLAGS

15 O

PC:FLAGS: S P.IC

U = PRESENT IN 8086 BUT NOT IN 8080

GENERAL REGISTERS

7 0 7 0

AX: AH AL |ACCUMULATOR"BX: BH I BL "BASE"CX: CH | CL "COUNT"DX: DH | DL DATA"

POINTER AND IN DEX REGISTERS

15 0

SP: "ISTACK POINTER''BP: ''BASE POINTER"

Sl: 'SOURCE INDEX"''DESTINATION

DI: INDEX'

SEGMENT REGISTERS

15 0

CS: ''CODE''

DS: "DATA"

SS: '"STACK"

ES: ''EXTRA'

INSTRUCTION POINTERAND FLAGS

15 0

"INSTRUCTION

LP: POINTER''FLAGS: 001 TSIZ JAI P IC.

8086 register names, corresponding registers in the 8080and 8086 do not necessarily have the same names.

General registerfile. The general register file comprisesthe seven 8-bit registers of the 8080, with an eighth registeradded so that the registers can be paired up to form four16-bit registers. The general registers can be addressed aseither 8- or 16-bit registers, whereas the registers in thenext two files can- be addressed only as 16-bit registers.The dual nature of these registers permits them to handleboth byte and word quantities with equal ease. The 16-bitregisters are named AX, BX, CX, and DX; when con-sidered as 8-bit registers, they are named AL, AH, BL,

PCODE D |W| REG Z R/M Ir---r --- -1- SEG

(OPTIONAL)

. DISP-LO(OPTIONAL)

FIRST OPERAND IS REGISTER OR MEMORY SPECIFIED BY SEG, MOD, R/M.DISP-LO, DISP-HI

MOD = 00,01 10: FIRST OPERAND IS MEMORY (SEE TABLE 2)11 FIRST OPERAND IS REGISTER (SEE TABLE 3)

SEG IS OVERRIDING SEGMENT REGISTER

SECOND OPERAND IS REGISTER SPECIFIED BY REG

W = 0 OPERANDS ARE 8 BITS1: OPERANDS ARE 16 BITS

D = 0: DESTINATION IS FIRST OPERAND1 DESTINATION IS SECOND OPERAND

DISP-HI j

(OPTIONAL)

Figure 6. Typical format of 8086 two-operand operation, when secondoperand is register.

Figure 7. Typical format of 8086 two-operand operation, when secondoperand Is a constant (immediate data).

54

BH, CL, CH, DL, and DH (the L or H suffix designateshigh-order or low-order byte).For the most part, contents of the general registers can

participate interchangeably in the arithmetic and logicaloperations of the 8086. However, there are a few instruc-tions (e.g., string instructions) that dedicate certaingeneral registers to specific uses. These uses are indicatedby the mnemonic phrases "accumulator," "base,""count," and "data" in Figure 5.

Pointer and index register file. The pointer and indexregisters of the 8086 consist of the 16-bit registers SP, BP,SI, and DI. These registers usually contain offset ad-dresses for addressing within a segment. They reduce thesize of programs by not requiring each instruction tospecify frequently used addresses. But they serve another(and perhaps more important) function; they provide fordynamic effective-address computations as described inthe section on operand addressing below. In order to ac-complish this, the 8086 permits the pointer and indexregisters to participate in arithmetic and logical opera-tions along with the 16-bit general registers.

This file is divided into the pointer subfile (SP and BP)and the index subfile (Stand DI). The pointer registers areintended to provide convenient access to data in the cur-rent stack segment as opposed to the data segment. Thus,unless a segment is specifically designated, offsets con-tained in the pointer registers are assumed to refer to thecurrent stack segment, whereas offsets contained in theindex registers are usually assumed to refer to the currentdata segment.

In certain instances, specific uses of these four registersare indicated by the mnemonic phrases "stack pointer,""base pointer,'" "source index," and "destinationindex," as shown in Figure 5.Segment registerfile. The segment registers of the 8086

are the 16-bit registers CS, DS, SS, and ES. Theseregisters are used to identify the four segments that arecurrently addressable. Each register identifies a particularcurrent segment and hence has an associated mnemonicphrase such as "code," "data," "stack," and "extra"(Figure 5).

All instruction fetches are taken from the current codesegment using the offset specified in the instructionpointer (IP) register. The segment for operand fetches canusually be designated by appending a special one-byteprefix to. the instruction. This prefix, as well as otherprefixes described later, has a unique encoding that per-mits it to be distinguished from the opcodes. In theabsence of such a prefix (the usual case), the operand isusually taken from the current data segment or currentstack segment, depending on whether the offset addresswas calculated from the contents of a pointer register.Programs can be dynamically relocated by changing

the segment register values, provided the program itselfdoes not load or manipulate the contents of the segmentregisters.A set of eight segment registers was at first proposed for

-the 8086, along with a field in a program status wordspecifying which segment register was currently CS,which DS, and which SS. The other five would haveserved as extra segment registers. Such a scheme wouldhave resulted in virtually no thrashing of segment register

COMPUTER

F r- -r-SEG

(OPTIONAL)

DISP-LO ~~DISP-HIL_____ J L__f___1(OPTIONAL) (OPTIONAL)

DATA-LO DATA-HI(OPTIONAL)

FIRST OPERAND IS REGISTER OR MEMORY SPECIFIED BY SEG, MOD. R/M,DISP-LO, DISP-HI

MOD = 00,01,10: FIRST OPERAN IS M,EMORY (SEE TABLE 2)11: FIRST OPERAND IS REGISTER (SEE TABLE 31

SEG IS OVERRIDING SEGMENT REGISTER

SECOND OPERAND IS IMMEDIATE DATA SPECIFIED BY S, W, DATA-LO, DATA-HI

W = 0: DATA = DATA-LO (DATA-HI IS ABSENT)1. S 0: 'DATA = DATA-HI, DATA-LO

1 DATA = DATA-LO SIGN EXTENDED (DATA-HI IS ABSENT)

OPCODE Is lwl OD OPC R/M

contents; start addresses of all needed segments wouldhave been loaded initially into one of the eight segmentregisters and the roles of the various segment registerswould have varied dynamically during program execu-tion. However, concern over the size of the resulting pro-cessor chip forced the number of segment registers to bereduced to the minimum number necessary, namely four.With this minimum number, each segment register can bededicated to a segment type (code, data, stack, and extra)and the specifying fields in the program status word are nolonger needed.

Flag register file. Six flags record processor status in-formation. Five are the 8080 flags and usually reflect thestatus of the latest arithmetic or logical operation. Thesixth, an OVERFLOW flag, reflects a signed overflowcondition.The 8086 also contains three flags that control pro-

cessor operations. These are the DIRECTION flag,which controls the direction of the string manipulations(auto-increment or auto-decrement); the INTERRUPTflag, which enables or disables external interrupts; andtheTRAP flag, which puts the processor into a single-stepmode for program debugging.

Instruction set. The 8086 instruction set is not a super-set of the 8080 instruction set. Although most of the 8080instructions are included in the 8086, some of the infre-quently used ones (e.g., conditional calls and returns) arenot. The operand addressing modes ofthe 8080 have beengreatly enhanced.

Operand addressing. Instructions in the 8086 usuallyperform operations on one or two source operands, withthe result overwriting one of the operands. The firstoperand of a two-operand instruction can be usuallyeither a register or amemory location; the second operandcan be either a register or a constant within the instruc-tion. (The terms first and secohd operand are used todistinguish the operands only-their use does not implyany directionality for data transfers.) Typical formats fortwo-operand instructions are shown in Figure 6 (secondoperand is a register) and Figure 7 (second operand is aconstant). Single-operand instructions generally alloweither a register or a memory location to serve as theoperand. Figure 8 shows a typical one-operand format.Virtually all 8086 operators may specify 8- or 16-bitoperands.Memory operands. An instruction may address an

operand residing in memory in one of the following ways,as determined by the "mod" and "r/m" fields in the in-struction (see Table 2):

* direct (16-bit offset address), or* indirect (optionally with an 8- or 16-bit displacement)

-through a base register (BP or BX),-thro'ugh an index register (SI or DI),-through the sum of a base register and an index

register.

Auto-incrementing and auto-decrementing addressmodes are not included, in general, since their use is main-ly oriented t'oward gtring processing. hs oe rncluded on the string primitive instructions.

October 1980

Register operands. An instruction may address anoperand residing in- one of the general registers or in oneof the pointer or index registers. Table 3 shows the registerseiection as determined by the "r/m" field (first operand)or the "res" field (second operand) in the instruction.Immediate operands. In general, one of the two

-operands of a two-operand instruction can be immediatedata appearing within the instruction. These operands arerepresented in 2's-complement form and may be ab-breviated to 8 bits (instead of the usual 16) if the high-order byte is the sign extension of the low-order byte.

Addressing mode usage. The addressing modes weredesigned to permit efficient implementation of high-levellanguage features. For example, a simple variable is

Figure 8. Typical forniat of 8086 one-operand operation.

Table 2.Determining 8086 offset address of a memory operand.

MOD SPECIFIES HOW DISP-LO AND DISP-HI ARE USED TO DEFINE A DISPLACEMENTAS FOLLOWS:

00: DISP=O (DISP-LO AND DISP-HI ARE ABSENT)MOD = 01: DISP= DISP-LO SIGN EXTENDED (DISP-HI IS ABSENT)

10: DISP=DISP-HI, DISP-LO

R/M SPECIFIES WHICH BASE AND INDEX REGISTER CONTENTS ARE TO BE ADDED TOTHE DISPLACEMENT TO FORM THE OPERAND OFFSET ADDRESS AS FOLLOWS:

000: OFFSET=(BX) + (SI) +DISP00i: OFFSET=(BX) + (Dl) + DISP010: OFFSET=(BP) + (SI) + DISP INDIRECT

R/M = 011: OFFSET-(BP) + (DI) + DISP ADDRESS100: OFFSET= (SI) + DISP MODE101: OFFSET= (DI) + DISP110: OFFSET=(BP) +DISP111: OFFSET=(BX) +DISP

MEANS "CONTENTS OF"

THE FOLLOWING SPECIAL CASE IS AN EXCEPTION TO THE ABOVE RULES:

MOD=00IF AND DIRECT

R/M = 100 ADDRESSMODE

TH-EN OFFSET= DISP-HI, DISP-LO J

USE THIS TABLE WHEN MOD #11; OTHERWISE USE TABLE 3.THIS TABLE APPLIES TO THE FIRST OPERAND ONLY; THE SECOND OPERAND CAN NEVER BE AMEMORY OPERAND.

55

L -_,SEG OPCODE M o OCOD R/M

(OPTIONAL)

DISP-LO J L DISP-HI(OPTIONAL) (OPTIONAL)

OPERAND IS REGISTER OR MEMORY SPECIFIED BY SEG, MOD. R/M,DISP-LO, DISP-HI

MOD = 00,01,10: OPERAND IS MEMORY (SEE TABLE 2)i 1; OPERAND IS REGISTER (SEE TABLE 3)

SEG IS OVERRIDING SEGMENT REGISTER

W = 0: OPERAND IS 8 BITS1 OPERAND IS 16-BITS

Table 3.Determining 8086 register- operand.

FIRST OPERANDR/M 8-BIT 16-BIT000: AL AX001: CL CX010: DL DX011: BL BX100: AH SP101: CH BP110: DH Si111: BH Di

SECOND OPERANDREG 8-BIT 16-BIT000: AL AX001: CL CX010: DL DX011: BL BX100: AH SP101: CH BP110: DH Si111: BH DI

USE THIS TABLE WHEN MOD = 11; OTHERWISE USE TABLE 2.

accessed with the direct mode, whereas an array elementin a based record (record located at a memory addresspointed at by some other variable) is accessed with theindirect-through-BX-plus-SI-plus-offset mode (wherebase register BX contains a pointer to start-of-record, off-set is the start of the array within the record, and indexregister SI contains the index into the array). The address-ing modes involving BP as the base register provide foraccessing data in the stack segment instead of in the datasegment. Data is frequently stored in (activation recordsin) the stack segment when recursive procedures andblock-structured languages are implemented. Addressingmodes used for accessing various data elements are shownin Table 4.Data transfers. The 8086 has four classes of data trans-

fer instructions: general-purpose, accumulator-specific,address-object, and flag.Three of the general-purpose transfers-move, push,

and pop-are derived from the 8080. The 8086 also has anexchange instruction, which was not present in the 8080.The accumulator-specific transfers are input, output,

and translate. The input and output instructions providedirect access to the first 256 ports, just as in the 8080.

Table 4.Addressing modes for accessing data elements.

NOT BASED BASED ACTIVATION RECORDSIMPLEVARIABLE: DIRECT BX BP+ OFFSETARRAYS: SI+ OFFSET BX+SI BP+ SI + OFFSET

DI+ OFFSET BX+DI BP+ DI +OFFSETRECORDS: DIRECT BX+ OFFSET 3P+OFFSETARRAYS OFRECORDS: SI+ OFFSET BX + SI + OFFSET BP+SI+OFFSET

DI + OFFSET BX + DI + OFFSET BP+ DI + OFFSET

56

These instructions also provide indirect access to any ofthe 64K ports, a facility not found in the 8080. Further-more, the 8086 I/O instructions provide access to 8- or16-bit-wide ports, whereas the 8080 I/O instructions pro-vide access to 8-bit-wide ports only. The translate instruc-tion performs a table-lookup byte translation, which isuseful when combined with string operations. Neither thetranslate instruction nor the string operations are presentin the 8080.

Address-object transfers represent another facility notfound in the 8080. These instructions-load effective ad-dress (provide access to the offset address of an operandas opposed to the value of the operand itself) and loadpointer (provide means of loading a segment start addressinto a segment register and an offset address into a generalor pointer register in a single instruction)-provide theprogrammer with some control over the 8086 addressingmechanism.The 8080 treats the collection of all its flags as a single

data item that can be pushed on or popped off the stack.The 8086's flag transfer instructions permit the collectionof all the flags to be loaded or stored as well. However,these load and store operations involve only those flagsthat already exist in the 8080. This is a concession to com-patibility (without these operations, it would take nine8086 bytes of code to perform an 8080 PUSH PSW orPOP PSW instruction).

Arithmetics. The only arithmetic instructions in the8080 are addition and subtraction of 8-bit unsignednumbers and addition of 16-bit unsigned numbers. The8086, on the other hand, provides for all combinations ofaddition, subtraction, multiplication, and division on8-bit and 16-bit signed and unsigned numbers. Signed-number facilities for addition and subtraction consist ofsufficient conditional transfers to allow for signed com-parisons and an OVERFLOW flag to detect signedoverflow (two features missing in the 8080).The designers considered providing separate opera-

tions for signed addition and subtraction which wouldautomatically trap on signed overflow (signed overflow isan exception condition, whereas unsigned overflow isnot). However, lack of room in the opcode space pro-hibited this. As a compromise, a one-byte trap-on-overflow instruction was included to make testing forsigned overflow less painful.The 8080's only binary-coded decimal arithmetic in-

struction is for addition of packed BCD numbers. Thistakes the form ofan adjustment instruction that is appliedafter the numbers are added in the normal way. The 8086provides adjustment instructions for performing both ad-dition and subtraction of packed BCD numbers. Packedmultiply and divide adjustments are not provided becausethe cross terms generated make it impossible to recoverthe decimal result without additional processor facilities(see box on page 48 for details).The 8086 also provides adjustment instructions for per-

forming arithmetic operations on unpacked BCDnumbers. Since ASCII-encoded numbers are a specialcase of unpacked BCD numbers, this facility permitsASCII-encoded numbers to be operated on directly. Un-packed BCD multiplication does not generate crossterms, so multiplication and division adjustments, as well

COMPUTER

as addition and -subtraction adjustments, are provided forunpacked BCD. The multiply adjustment consists of con-verting an 8-bit binary number into two 4-bit BCD digits;the divide adjustment does the reverse. Adjustment fordivision is made before the execution ofthe divide instruc-tion, whereas addition, subtraction, and multiplicationadjustments are made after the execution of the cor-responding arithmetic instruction. In other words, the ad-dition, subtraction, and multiplication adjustments cor-rect a bad (i.e., non-BCD) result, whereas the division ad-justment prevents a bad result from occurring. See, again,the box on page 48 for more details on unpacked BCD ad-justments.

Logicals. The 8086 processor contains the 8080'slogical AND, OR, XOR, and NOT instructions as well asa logical TEST (testing for specific bits) instruction notfound in the 8080. TEST sets the processor's flags exactlyas an AND would but, unlike theAND, does not store theresult. Thus, both source operands are intact after execu-tion of a TEST instruction, whereas one of them wouldhave been overwritten if anAND instruction had been ex-ecuted instead.The 8080 contains four unit-rotate instructions. The

8086 augments this with four unit-shift instructions andwith multibit shift and rotate instructions. The multibitshift and rotate instructions permit the number of bitsover which to shift or rotate to be computed at run time.

String manipulation. A string is simply a sequence ofbytes or words in memory. A string operation is an opera-tion that is performed on each item in a string. Since stringoperations usually involve repetitions, they may take along time to execute. The 8086 has a set of instructionsthat decrease the time required to perform string opera-tions by (1) having a powerful set ofprimitive instructionsso that the time taken to process each item in the string isreduced, and (2) eliminating the bookkeeping and over-head that is usually performed between the processing ofsuccessive items. The 8080 does not provide any stringmanipulation facilities.

Transfer of control. Transfer-of-control instructions(jumps, calls, returns) are of two basic varieties: intraseg-ment transfers, which transfer control within the currentcode segment by specifying a new value for IP; and in-tersegment transfers, which transfer control to an ar-bitrary code segment by specifying a new value for bothCS and IP. Transfers can be either direct or indirect.Direct transfers specify the destination of the transfer(new value of IP and possibly CS) in the instruction; in-direct transfers use the standard addressing modes, asdescribed previously, to locate an operand specifying thedestination of the transfer. The 8086 has all four com-binations of transfers, whereas the 8080 has direct, in-trasegment transfers only.The 8080jump and call instructions specify an absolute

destination address; the corresponding 8086 transfers

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Colorado state University gineering core prograrneering discipline pro|Fort coll ins, CO croprocessors/microcoEducation programs a

Continuing Educationhow microprocessors

co-sponsorend by ~~~~~~~~~~~should be treated in thiIEEE-CS Mini/Microcomputer TC ty and industrial progrformation contact: D

and Department of ElectricThe DISEM Project* orado State Universit)80523, (303) 491-5028.

0 IEEE COMPUTER SOCIETY *Dlgit

THEINSTITUTEOFELECTRICALANDELECTRONICSENGINEERS.INC.Project®THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC.

)ilities of micropro-nputer systems havely since the DISEof 1976 and the

publication ofthe Computer

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She purpose of thisnine: (1) the presentssors play in Elec-rams, Computer En--ience programs, en-ns and/or other engi-grams; (2) how mi-)mputers are beingbased Continuing

nd industrial basedprograms; and (3)

should impact ande different universi-rams. For further in-

Ir. T. A. Brubaker,al Engineering, Col.y, Fort Collins, CO

cational Materials

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32-BITLOAD/STORE

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8 & 16 ALL UPS

MULTIPLY/DIVIDE LOAD/STORE/XCHG/ IMM LOAD

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PACKED BCD 8-BITARITHMETIC ARITH. & LOGICAL

MM/TRI 8-BIT IMMEDIATE(MMETRIC/'GISTERS NONSYMMETRIC ACC ONLY

REGISTERSSYMMETRIC REGISTERS

H & LDIRECT ADDRESS INDIRECT ONLY

FOR24 ADDRESSING ACC, H, AND L 14-BIT

MODES JUMP ADDRESS

ADDRESSARITHMETIC NO DIRECT

ADDRESS

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Figure 9. 8008-8086 evolution.

specify a self-relative destination address. This providesfor code compaction (a shortened jump instruction isavailable for close jumps) as well as for position-independent code.The 8086 return instruction may adjust the SP register

so that stacked parameters are discarded, thereby makingparameter passing more efficient. This is a better solutionto the problem than the 8080 instruction, which ex-changes the contents of HL with the top of the stack.The conditional jump instructions in the 8080 are

useful for determining relations among unsigned

numbers only. The 8086 provides conditional jump in-structions that determine relations among both signedand unsigned numbers. Table 5 shows the conditionaljumps as functions of flag settings.The 8080 provides conditional call and return instruc-

tions merely as accidents of implementation. In order tofree-up valuable opcodes, these seldom-used instructionshave not been incorporated in the 8086.

Interrupts. The 8080 interrupt mechanism is generalenough to permit the interrupting device to supply anyoperation for out-of-sequence execution. However, the

COMPUTER58

only operation that has any utility for interrupt process-

ing is the one-byte subroutine call. This byte comprises

five bits of opcode and three bits that identify one of eightinterrupt subroutines residing at eight fixed locations in

memory. If the unnecessary generalization is removed,the interrupting device does not have to provide the op-

code, and all eight bits can be used to identify the inter-rupt subroutine. Furthermore, if the eight bits are used toindex a table of subroutine addresses, the actual subrou-tine can reside anywhere in memory. The 8086 interruptmechanism reflects this line of thinking.

The six years of evolution traced here encompass

many advances in technology and performance (Figure 9,

Tables 6 and 7). During this period, computing costsdeclined by over three orders of magnitude. By removinga hurdle that had inhibited the computer industry-theneed to conserve expensive processors-the new era hasfreed system designers to concentrate on the applicationsthemselves. *

Table 5.8086 conditional jumps as functions of flag settings.

JUMP ON FLAG SETTINGS

EQUAL.. ..ZF = 1

NOTEQUAL ZF = 0

LESS THAN ........ ........ (SF XOR OF) = 1GREATER THAN ........ ........ ((SF XOR OF) OR ZF) = 0LESS THANOREQUAL ((SF XOR OF) OR ZF) = 1

GREATER THAN OR EQUAL ................ (SF XOR OF) = 0BELOW ........ ........ CF = 1ABOVE. ..(CF OR ZF) = O

BELOW OR EQUAL ................ (CF OR ZF) = 1ABOVE OR EQUAL ............... CF = 0

PARITY EVEN PF = 1

PARITY ODD PF = 0

OVERFLOW OF = 1

NOOVERFLOW OF = 0

SIGN .................SF= 1

NO SIGN ...... ........ SF = 0

Table 6.Performance comparison.

8008' 8080 (2 MHZ) 8086 (8 M HZ)(1972) (1974) (1978)

REGISTER-REGISTER TRANSFER 12.5 2 0.25JUMP 25 5 0.875REGISTER-IMMEDIATE OPERATION 20 3.5 0.5SUBROUTINE CALL 28 9 2.5I.NCREMENT (16-BIT) 50 2.5 0.25ADDITION (16-.BIT) 75 5 0.375TRANSFERS (16-BIT) 25 2 0.25ALL TIMES ARE IN MICROSECONDS.

Table 7.Technology comparison.

8008 8080 8085 8086(1972) (1974) (1976) (1978)

SILICON P-CHANNEL N-CHANNEL N-CHANNEL SCALEDGATE ENHANCEMENT ENHANCEMENT D-EPLETION N-CHANNELTECHNOLOGY LOAD DEVICE LOAD DEVICE LOAD DEVICE (HMOS) DEPLETION

LOAD DEVICE

CLOCK 0.5-0.8 MHz 2-3 MHz 3-5 MHz 5-8 MHzRATE

MIN. GATE DELAY1 30 NS2 15 NS2 5 NS 3NSFO= Fl = 1

TYPICAL SPEED 100 PJ 40 PJ 10 PJ 2 PJPOWER PRODUCT

APPROXIMATE NUMBER 2000 4500 6500 20,0004OF TRANSISTORS3

AVERAGE TRANSISTOR 8.4 7.5 5.7 2.5DENSITY (MIL-SQRDPER TRANSISTOR)NOTES:1. FASTEST INVERTER FUNCTION AVAILABLE WITH WORST CASE PROCESSING.2. LINEAR MODE ENHANCEMENT LOAD.3. GATE EQUIVALENT CAN BE ESTIMATED BY DIVIDING BY THREE.4. THIS IS 29,000 TRANSISTORS, IF ALL ROM AND PLA PLACEMENT SITES AVAILABLE ARE COUNTED.

October 1980 59

BibliographyMany people played significant roles in the develop-

ment of these processors. Hence, it is not possible tosingle out a few for all the credit. However, if forced tochoose those people who played the most significant roleson each chip, we can name the following: M. E. (Ted)Hoff was the architect and Federico Faggin the chipdesigner of the 4004. Stanley Mazor contributed to the4004 architecture as well as to the architectutes ofthe 8008and 8080. Hoff and Hal Feeney were the major con-tributors to the 8008 development. Faggin managed thedevelopment of the 8080 and participated in defining itsarchitecture, with Masatoshi Shima doing the logic andcircuit design. Roger Swanson defined the new instruc-tions for the 8085, while Peter Stoll and Andrew Volk per-fotmed the 8085 logic and circuit design. The 8086 ar-chitecture was defined by Stephen Morse and refined byBruce Ravenel, with James McKevitt and John Baylissresponsible for the logic and circuit design. WilliamPohlman managed both the 8085 and 8086 activities.The authors thank Stephen Hanna for reviewing this

material and providing many helpful suggestions andcomments.

Stephen P. Morse is currently on the staffof Language Resources, a software firminvolved in the development of Pascalcompilers for microprocessors. Previouslyhe was with Intel Corp., where he was re-sponsible for the architectural definitionof the 8086 and served in an advisory staffposition in the high-level language area.Morse has delivered numerous guest lec-

tures on the 8086 (including one in Taiwan)and has recently written a textbook describing the 8086. He haspublished numerous technical articles on microprocessors,language and compiler design, and computer graphics.Morse received a BEE degree from the City University ofNew

York in 1962 and an MS and PhD in electrical engineering fromthe Polytechnic Institute of New York in 1963 and 1967, respec-tively. He is a member of the ACM.

_Bruce W. Ravenel is president ofLanguageResources. Previously at Intel Corpora-tion, he was coarchitect of the 8086microprocessor, architect of the 8087numeric processor, and designer of thePL/M-86 programming language. Beforejoining Intel in 1976, Ravenel earned a BAin economics at the University of Col-orado, Boulder; his computer sciencegraduate studies at Boulder focused on

software portability and compiler construction.Ravenel is cochairman of the Joint ANSI/X3J9-IEEE

Pascal Standards Committee. He is a member of the IEEE andof the IEEE Computer Society.

Bylinsky, G., "Here Comes the Second Computer Revolution,"Fortune, Nov. 1975.Faggin, F., et al., "The MCS-4-An LSI MicrocomputerSystem," IEEE 1972 Region Six Conf., 1972, pp. 8-11.Hoff, M. E., Jr., "The New LSI Components," Digest ofPapers-COMPCON 72, IEEE Computer Society, pp. 141-143.Intel MCS-8 User's Manual, Apr. 1975.Intel MCS-40 User's Manual, third ed., Mar. 1976.Intel MCS-85 User's Manual, Mar. 1977.Intel MCS-86 User's Manual, July 1978.Intel 8080 Microcomputer Systems User's Manual, Sept. 1975.Morse, S. P., The 8086 Primer, Hayden Book Company, NewYork, 1980.

Morse, S. P., W. B. Pohlman, and B. W. Ravenel, "The Intel8086 Microprocessor: A 16-Bit Evolution of the 8080," Com-puter, Vol. 11, No. 6, June 1978, pp. 18-27.

Shima, M., F. Faggin, and S. Mazor, "An N-Channel 8-BitSingle Chip Microprocessor," IEEE Int'l Solid-State CircuitsConf., Feb. 1974, pp. 56-57.Vadasz, L. L., et al., "Silicon Gate Technology," IEEE Spec-trum, Oct. 1969, pp. 27-35.

Stanley Mazor is with Intel Corp., wherehe has participated in the designs of theMCS-4, MCS-8, 8080, and several othermicrocomputers. Prior to joining Intel in1969, he was assistant manager of the com-puter center at San Francisco State Collegeand a principal designer of the Symbolcomputer at Fairchild.Mazor has published 25 articles and

papers on microcomputers and sharespatents on the 8080 and MCS-4. He is a member of the IEEE.

_SSF Wllliam B. Pohbpan was programmanager for mid-railge microprocessors atIntel Corporation. His techhical interestsinclude computer architecture, VLSIstructures and implementation techniques,and multimicroprocessor systems. Beforejoining Intel in 1975, he was responsiblefor the LSI-I1 chip set development atWestern Digital Corporation.

/ Ei. Pohlman received his BSEE from Cali-fornia State University at Northridge in 1966, and his,MSEEfrom the University of Southern California in 1969. He is amember of the ACM and the IEEE.

COMPUTER

Acknowledgments