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30-Aug-2012

Copyright © 2012 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.

MIPI® Alliance Specification for System Power Management Interface (SPMI)

Version 2.0 – 14 March 2012

* NOTE TO IMPLEMENTERS *

This document is a Draft MIPI Specification. MIPI member companies’ rights and obligations apply to this Draft MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.

An updated Frequently Asked Questions (FAQ) document has been prepared by the SPM Working Group for SPMI v2.0 Specification implementers. Also, a SPMI v2.0 Protocol Implementation Conformance Statement (PICS) document has been prepared by the SPM Working Group.

The SPMI v2.0 Specification contains the following major changes with respect to SPMIv1.0:

• Unified memory map for Slave Device.

• Command acknowledgement (ACK/NACK) for Write commands where required.

• System behavior upon detection of a parity error in an RCS Device-initiated Command Frame.

Backwards Compatibility

• SPMI v2.0 devices are not compatible with SPMI v1.0 Master and Request Capable Slave (RCS) devices.

• SPMI v2.0 Master devices are compatible with SPMI v1.0 Non-Request Capable Slave (NRCS) devices, if the Master ignores the value present on SDATA during the ACK/NACK cycle.

Version 2.0 14-Mar-2012 MIPI Alliance Specification for SPMI

Copyright © 2007-2012 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.

MIPI Alliance Specification for System Power Management Interface (SPMI)

Version 2.0 – 14 March 2012

MIPI Board Approved 28-Aug-2012

Further technical changes to this document are expected as work continues in the SPM Working Group.



ii

NOTICE OF DISCLAIMER 1

The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled 2 by any of the authors or developers of this material or MIPI®. The material contained herein is provided on 3 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 4 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 5 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if 6 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of 7 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of 8 negligence. 9

All materials contained herein are protected by copyright laws, and may not be reproduced, republished, 10 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express 11 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related 12 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and 13 cannot be used without its express prior written permission. 14

ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET 15 POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 16 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY 17 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 18 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE 19 GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 20 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER 21 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR 22 ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, 23 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH 24 DAMAGES. 25

Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is 26 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the 27 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; 28 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance 29 with the contents of this Document. The use or implementation of the contents of this Document may 30 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, 31 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI 32 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any 33 IPR or claims of IPR as respects the contents of this Document or otherwise. 34

Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 35

MIPI Alliance, Inc. 36 c/o IEEE-ISTO 37 445 Hoes Lane 38 Piscataway, NJ 08854 39 Attn: Board Secretary 40



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Contents 41

Version 2.0 – 14 March 2012 ..................................................................................................................... i 42

1 Introduction .................................................................................................................................... 11 43

1.1 Scope ...................................................................................................................................... 11 44

1.2 Purpose ................................................................................................................................... 11 45

2 Terminology ................................................................................................................................... 12 46

2.1 Definitions .............................................................................................................................. 12 47

2.2 Abbreviations .......................................................................................................................... 13 48

2.3 Acronyms ............................................................................................................................... 14 49

3 References ...................................................................................................................................... 15 50

4 SPMI Overview .............................................................................................................................. 16 51

4.1 System Overview .................................................................................................................... 16 52

4.2 SPMI Protocol Overview ......................................................................................................... 17 53

5 Physical Interface............................................................................................................................ 18 54

5.1 I/O Structures .......................................................................................................................... 18 55

5.1.1 I/O Configuration with Multiple Slaves and Masters ......................................................... 19 56

5.2 I/O Voltage and Logic Levels .................................................................................................. 19 57

5.2.1 Signaling Voltages ........................................................................................................... 19 58

5.2.2 SPMI I/O Voltage Supply ................................................................................................ 20 59

5.3 Device Classes ........................................................................................................................ 20 60

5.4 SPMI Clock (SCLK) ............................................................................................................... 21 61

5.4.1 Electrical Specifications for the Master SCLK Driver ....................................................... 21 62

5.4.2 Electrical Specifications for SCLK Input .......................................................................... 22 63

5.5 SPMI Data (SDATA) .............................................................................................................. 23 64

5.5.1 Electrical Specifications for the SDATA Driver ............................................................... 23 65

5.5.2 Electrical Specifications for the SDATA Receiver ............................................................ 25 66

5.6 Device Characterization .......................................................................................................... 26 67

5.7 Electromagnetic Interference ................................................................................................... 27 68

6 SPMI Constructs ............................................................................................................................. 28 69

6.1 Bit Ordering ............................................................................................................................ 28 70

6.2 Sequences ............................................................................................................................... 28 71

6.2.1 Bus Arbitration ................................................................................................................ 28 72

6.2.2 Sequence Start Condition ................................................................................................. 28 73

6.2.3 Frames............................................................................................................................. 29 74

6.2.4 Parity Bit ......................................................................................................................... 31 75

6.2.5 ACK/NACK .................................................................................................................... 31 76



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6.2.6 Bus Park Cycle ................................................................................................................ 32 77

6.3 Bus Idle Condition .................................................................................................................. 32 78

6.4 Sequence Priority Classes ........................................................................................................ 33 79

7 Device Enumeration........................................................................................................................ 34 80

7.1 Master Identifier ...................................................................................................................... 34 81

7.2 Unique Slave Identifier ............................................................................................................ 34 82

7.3 Group Slave Identifier ............................................................................................................. 34 83

8 Bus Arbitration ............................................................................................................................... 35 84

8.1 Bus Arbitration Levels ............................................................................................................ 35 85

8.2 Conditions............................................................................................................................... 36 86

8.3 Bus Arbitration Overview ........................................................................................................ 36 87

8.3.1 Connect Sequence ............................................................................................................ 40 88

8.4 Slave Arbitration ..................................................................................................................... 41 89

8.4.1 Slave Request Hold .......................................................................................................... 42 90

8.5 Master Arbitration ................................................................................................................... 43 91

8.5.1 SCLK Handover .............................................................................................................. 45 92

8.6 Determining Master Priority Level for Master Arbitration ........................................................ 46 93

8.7 Bus Arbitration Error Handling................................................................................................ 47 94

9 Master Connection and Disconnection ............................................................................................. 50 95

9.1 Definitions .............................................................................................................................. 50 96

9.2 Master Connecting on the Bus ................................................................................................. 50 97

9.2.1 Connecting by Detecting SSC .......................................................................................... 51 98

9.2.2 Connecting by Detecting Bus Idle .................................................................................... 52 99

9.2.3 Connecting by Detecting Bus Arbitration ......................................................................... 55 100

9.3 Bus Initialization ..................................................................................................................... 57 101

9.4 Disconnecting from the Bus..................................................................................................... 58 102

9.4.1 Bus Monitoring by Disconnected Master .......................................................................... 58 103

10 Slave Communication Request .................................................................................................... 59 104

10.1 Alert bit on an Initialized Bus .................................................................................................. 59 105

10.2 Slave Request Bit on an Initialized Bus .................................................................................... 60 106

10.3 Slave Communication Request on Uninitialized Bus ................................................................ 61 107

11 SPMI Master Requirements ......................................................................................................... 62 108

11.1 Master Operating States........................................................................................................... 62 109

11.1.1 Bus Owner Master ........................................................................................................... 62 110

11.1.2 Connected Master ............................................................................................................ 63 111

11.1.3 Disconnected Master ........................................................................................................ 63 112

11.2 Optional Command Support .................................................................................................... 63 113



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11.3 Master External Control Signals .............................................................................................. 63 114

12 SPMI Slave Requirements ........................................................................................................... 64 115

12.1 Register Map ........................................................................................................................... 64 116

12.2 Slave External Control Signals ................................................................................................ 64 117

12.2.1 RESETN ......................................................................................................................... 64 118

12.2.2 ENABLE ......................................................................................................................... 64 119

12.2.3 PWROK .......................................................................................................................... 64 120

12.2.4 Exceptional Control Inputs ............................................................................................... 64 121

12.2.5 Other Control Inputs and Outputs ..................................................................................... 65 122

12.2.6 Multiple Logical Slaves on a Single Physical Device ........................................................ 65 123

12.3 Slave Operating States ............................................................................................................. 65 124

12.3.1 STARTUP ....................................................................................................................... 66 125

12.3.2 ACTIVE .......................................................................................................................... 66 126

12.3.3 SLEEP............................................................................................................................. 66 127

12.3.4 SHUTDOWN .................................................................................................................. 67 128

12.3.5 Exceptional State Transitions ........................................................................................... 67 129

12.4 Optional Command Support .................................................................................................... 67 130

13 Command Sequences .................................................................................................................. 68 131

13.1 Command Sequence Summary ................................................................................................ 68 132

13.2 Command Sequence Descriptions ............................................................................................ 68 133

13.2.1 Extended Register Write Command Sequence .................................................................. 69 134

13.2.2 Extended Register Read Command Sequence ................................................................... 70 135

13.2.3 Reset, Sleep, Shutdown, Wakeup Command Sequences.................................................... 72 136

13.2.4 Authentication Command Sequence ................................................................................. 72 137

13.2.5 Master Write Command Sequence ................................................................................... 73 138

13.2.6 Master Read Command Sequence .................................................................................... 74 139

13.2.7 Transfer Bus Ownership Command Sequence .................................................................. 75 140

13.2.8 Device Descriptor Block Slave Read Command Sequence ................................................ 76 141

13.2.9 Device Descriptor Block Master Read Command Sequence .............................................. 77 142

13.2.10 Extended Register Write Long Command Sequence ..................................................... 78 143

13.2.11 Extended Register Read Long Command Sequence ...................................................... 80 144

13.2.12 Register Write Command Sequence.............................................................................. 83 145

13.2.13 Register Read Command Sequence .............................................................................. 83 146

13.2.14 Register 0 Write Command Sequence ........................................................................... 84 147

13.3 Error Handling ........................................................................................................................ 84 148

13.3.1 Parity Error in the Command Frame ................................................................................. 85 149

13.3.2 Unsupported Commands .................................................................................................. 85 150



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13.3.3 Parity Error in the Address Frame .................................................................................... 85 151

13.3.4 Parity Error in the Data Frame.......................................................................................... 85 152

13.3.5 Unsupported Address ....................................................................................................... 86 153

Annex A SPMI Reference (informative) ............................................................................................. 87 154

A.1 DC Operating Conditions ........................................................................................................ 87 155

A.2 AC Operating Conditions ........................................................................................................ 87 156

A.2.1 High Speed (HS) Device Class ......................................................................................... 87 157

A.2.2 Low Speed (LS) Device Class .......................................................................................... 88 158

A.2.3 Other Signaling Electrical Specifications .......................................................................... 88 159

A.3 Command Sequence Reference (informative)........................................................................... 89 160

161



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Figures 162

Figure 1 SPMI System Example ............................................................................................................. 16 163

Figure 2 SDATA Master and Slave I/O Cells .......................................................................................... 18 164

Figure 3 SCLK Master and Slave I/O Cells ............................................................................................. 18 165

Figure 4 Clock Driver Output Waveform Constraints .............................................................................. 21 166

Figure 5 Bus Handover Timing ............................................................................................................... 22 167

Figure 6 Received Clock Signal Constraints ............................................................................................ 23 168

Figure 7 Bus Active Data Transmission Timing Specification ................................................................. 24 169

Figure 8 Bus Park Cycle Timing ............................................................................................................. 24 170

Figure 9 Bus Handover Timing ............................................................................................................... 25 171

Figure 10 Bus Active Data Receiver Timing Requirements ..................................................................... 26 172

Figure 11 Device Characterization Circuit ............................................................................................... 26 173

Figure 12 Sequence Start Condition ........................................................................................................ 29 174

Figure 13 Command Frame .................................................................................................................... 30 175

Figure 14 Data Frame ............................................................................................................................. 30 176

Figure 15 No Response Data Frame ........................................................................................................ 31 177

Figure 16 Example ACK/NACK using Register Write Command Sequence ............................................ 32 178

Figure 17 Bus Idle Condition .................................................................................................................. 33 179

Figure 18 New Arbitration Delay ............................................................................................................ 37 180

Figure 19 Bus Arbitration Flow Diagram ................................................................................................ 39 181

Figure 20 Bus Arbitration with and without C-Sequence ......................................................................... 40 182

Figure 21 Slave Arbitration using the A-bit ............................................................................................. 42 183

Figure 22 Slave Arbitration using the SR-bit ........................................................................................... 42 184

Figure 23 Request Capable Slave Hold State Machines for A-bit and SR-bit Slave Arbitration Requests .. 43 185

Figure 24 Master Priority Arbitration Example ........................................................................................ 44 186

Figure 25 Master Secondary Arbitration Example ................................................................................... 45 187

Figure 26 SCLK Handover Sequence ...................................................................................................... 46 188

Figure 27 False Bus Request Detection ................................................................................................... 48 189

Figure 28 Noise During Priority Slots of the Bus Arbitration ................................................................... 48 190

Figure 29 False Slave Arbitration due to Noise ........................................................................................ 49 191

Figure 30 SPMI Bus States ..................................................................................................................... 50 192

Figure 31 Detecting SSC to Connect to Bus Flow Diagram ..................................................................... 52 193

Figure 32 Detecting Bus Idle to Connect to Bus Flow Diagram ............................................................... 54 194

Figure 33 Detecting Bus Arbitration to Connect to Bus Flow Diagram .................................................... 56 195

Figure 34 Bus Initialization ..................................................................................................................... 57 196

Figure 35 Bus Initialization with Pending Bus Arbitration Request by RCS ............................................. 58 197



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Figure 36 Flow Diagram for Slave Communication Request using the A-bit ............................................ 60 198

Figure 37 Flow Diagram for Slave Communication Request using the SR-bit .......................................... 61 199

Figure 38 SPMI Master Operating States ................................................................................................ 62 200

Figure 39 Alternate External Control Signal Configurations .................................................................... 65 201

Figure 40 SPMI Slave State Diagram ...................................................................................................... 66 202

Figure 41 Extended Register Write Command Sequence ......................................................................... 70 203

Figure 42 Extended Register Read Command Sequence .......................................................................... 71 204

Figure 43 Reset, Sleep, Shutdown and Wakeup Command Sequences ..................................................... 72 205

Figure 44 Authenticate Command Sequence ........................................................................................... 73 206

Figure 45 Master Write Command Sequence ........................................................................................... 74 207

Figure 46 Master Read Command Sequence ........................................................................................... 75 208

Figure 47 Transfer Bus Ownership Command Sequence ......................................................................... 76 209

Figure 48 Device Descriptor Block Slave Read Command Sequence ....................................................... 77 210

Figure 49 Device Descriptor Block Master Read Command Sequence ..................................................... 78 211

Figure 50 Extended Register Write Long Command Sequence ................................................................ 80 212

Figure 51 Extended Register Read Long Command Sequence ................................................................. 82 213

Figure 52 Register Write Command Sequence......................................................................................... 83 214

Figure 53 Register Read Command Sequence ......................................................................................... 84 215

Figure 54 Register 0 Write Command Sequence ...................................................................................... 84 216

Figure 55 Command Sequence Formats .................................................................................................. 89 217

218



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Tables 219

Table 1 SPMI Pull-down Resistance Specifications ................................................................................. 19 220

Table 2 Parameters for Components using 1.8 V Signaling ...................................................................... 19 221

Table 3 Static Electrical Characteristics for 1.8 V Signaling .................................................................... 20 222

Table 4 Parameters for Components using 1.2 V Signaling ...................................................................... 20 223

Table 5 Static Electrical Characteristics for 1.2 V Signaling .................................................................... 20 224

Table 6 SCLK Output Timing Characteristics ......................................................................................... 21 225

Table 7 SCLK Bus Handover Timing Parameters .................................................................................... 22 226

Table 8 Clock Input Timing Requirements .............................................................................................. 23 227

Table 9 SDATA Output Timing Characteristics ...................................................................................... 24 228

Table 10 SDATA Release Timing Parameters ......................................................................................... 25 229

Table 11 Data Receiver Timing Requirements......................................................................................... 26 230

Table 12 Bus Arbitration Levels ............................................................................................................. 35 231

Table 13 New Master Priority Level Calculation ..................................................................................... 46 232

Table 14 Round-Robin Arbitration Sequence .......................................................................................... 47 233

Table 15 Connecting Master Priority Level ............................................................................................. 55 234

Table 16 Summary of SPMI Commands ................................................................................................. 68 235

Table 17 SPMI DC Electrical Specifications ........................................................................................... 87 236

Table 18 SPMI HS Device AC Specifications ......................................................................................... 87 237

Table 19 SPMI LS Device AC Specifications .......................................................................................... 88 238

Table 20 SPMI Bus Timeout Specification .............................................................................................. 88 239

240



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Release History 241

Date Release Description

2008-10-27 v1.00.00 Initial MIPI Alliance Board-approved release.

2012-08-30 v2.0 Board-approved release.



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MIPI Alliance Specification for SPMI 242

1 Introduction 243

The complexity and performance requirements of mobile phones and other portable electronic devices are 244 increasing at an ever-accelerating rate. As the demand for new high performance, high data rate features 245 increases system level power management is becomes more critical. The use of advanced power 246 management techniques to reduce power consumption and improve battery life is becoming more important 247 than ever before. 248

Reducing power consumption of digital processors in portable electronic devices can improve the battery 249 life and increase the available power budget for features such as color screens and backlights. These are 250 standard features on portable devices such as wireless handsets, handheld gaming consoles and portable 251 media players. 252

To minimize power consumption of digital processors in portable electronic devices, system and IC 253 designers are now using advanced power management techniques. Advanced hardware and software 254 techniques are now being used to: 255

• Accurately monitor and control processor performance level required for a given workload or 256 application 257

• Control various supply voltages based on the performance level 258

Rapid deployment of such advanced power management techniques requires interface standardization. This 259 System Power Management Interface (SPMI) Specification addresses hardware interface standardization. 260

1.1 Scope 261

This document describes the low-level protocol, communication sequences and arbitration process 262 including device IDs used to implement SPMI. In addition, the bus topology, I/O structures/physical layer 263 and signal timing requirements are also within the scope of this document. Higher level protocols, software 264 driver design and specific device-implementation details are out of scope of this document. 265

1.2 Purpose 266

The purpose of this document is to specify a standard interface between baseband or application processors 267 and peripheral components. The SPMI reduces the time-to-market and design cost of mobile terminals by 268 simplifying the interconnection of products from different manufacturers. 269



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2 Terminology 270

The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the 271 words “shall”, “should”, “may”, and “can” in the development of documentation, as follows: 272

The word shall is used to indicate mandatory requirements strictly to be followed in order 273 to conform to the standard and from which no deviation is permitted (shall equals is 274 required to). 275

The use of the word must is deprecated and shall not be used when stating mandatory 276 requirements; must is used only to describe unavoidable situations. 277

The use of the word will is deprecated and shall not be used when stating mandatory 278 requirements; will is only used in statements of fact. 279

The word should is used to indicate that among several possibilities one is recommended 280 as particularly suitable, without mentioning or excluding others; or that a certain course 281 of action is preferred but not necessarily required; or that (in the negative form) a certain 282 course of action is deprecated but not prohibited (should equals is recommended that). 283

The word may is used to indicate a course of action permissible within the limits of the 284 standard (may equals is permitted). 285

The word can is used for statements of possibility and capability, whether material, 286 physical, or causal (can equals is able to). 287

All sections are normative, unless they are explicitly indicated to be informative. 288

Numbers are decimal unless otherwise indicated. A prefix of 0x indicates a hexadecimal number, while a 289 prefix of 0b indicates a binary number. 290

This document uses the C/Verilog representation for operators where bitwise AND is represented by ‘&’, 291 bitwise OR is represented by ‘|’, bitwise XOR is represented by ‘^’ and 1’s complement (negation) is 292 represented by ‘~’. The modulo operator is represented by ‘%’. 293

2.1 Definitions 294

Address Frame: A series of nine bits with eight bits representing address information and a single parity 295 bit. 296

Bus Arbitration: Bus Arbitration is the process of allocating the bus to one device for the purpose of 297 sending a Sequence. 298

Bus Handover: The transfer of the bus ownership from the present BOM to the next BOM. 299

Bus Idle: The SPMI bus is idle when both the SCLK and SDATA are at a logic level zero between the end 300 of a Sequence and the beginning of Bus Arbitration. 301

Bus Owner Master: The Master that sent the most recent Sequence on the bus and provides SCLK for the 302 subsequent Bus Arbitration. 303

Bus Park Cycle: A single clock cycle that occurs when the SDATA signal control may change between 304 devices during, or at the end of, a Sequence. 305



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Command Frame: A series of thirteen bits with four bits representing a SPMI Master or Slave device 306 address, eight bits representing a SPMI command and a single parity bit. 307

Command Sequence: Part of a Sequence including the Sequence Start Condition (SSC), Command and 308 Data Frames and Bus Park Cycle. 309

Connected Master: A Master that has a Master Priority Level and that is able to initiate Command 310 Sequences on an Initialized Bus. 311

Data Frame: A series of nine bits with eight bits of data and a single parity bit. 312

Disconnected Master: A Master that does not update its Master Priority Level and does not send or 313 respond to Sequences on the bus. 314

Group Slave ID: A 4-bit number assigned to one or more Slave devices identifying them on the SPMI bus 315 as a group. 316

Initialized Bus: The SPMI bus is considered initialized when there is a Bus Owner Master. 317

Master: A device on the SPMI bus that can drive the SCLK line, participate in multi-Master arbitration, 318 and supports the transmission of all Master-specific Sequences. 319

Master Arbitration: A phase of Bus Arbitration between Master devices to allocate the SPMI bus to one 320 Master. 321

Master ID: Unique 2-bit number assigned to a SPMI Master identifying it on the bus. 322

Master Priority Level: A number assigned to each Master that dictates the order in which bus ownership 323 is granted. 324

Non-Request Capable Slave: A Slave device that cannot perform Slave Arbitration or send Sequences. 325

Sequence: A bus transaction on the SPMI bus that begins with Bus Arbitration, contains a SSC, a 326 Command Frame, potentially Data and Address Frames and ends with a Bus Park Cycle. A Sequence may 327 be transmitted by a Master or a Request Capable Slave device. 328

Slave: A device on the SPMI bus that is not capable of driving the SCLK line, i.e. not a Master. 329

Slave Arbitration: A phase of Bus Arbitration between Request Capable Slave devices to allocate the 330 SPMI bus to one Request Capable Slave. 331

Slave ID: A 4-bit number assigned to a SPMI Slave. Can be either Unique Slave ID or Group Slave ID. 332

Request Capable Slave: A device on the bus that is not a Master, but is capable of requesting and 333 participating in Bus Arbitration and sending Sequences. 334

Uninitialized Bus: The SPMI bus is considered uninitialized when there is no Bus Owner Master. 335

Unique Slave ID: Unique 4-bit number assigned to a SPMI Slave identifying it on the bus. 336

2.2 Abbreviations 337

High-Z High impedance 338

SDATA SPMI data 339



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SCLK SPMI clock 340

SCLKint Internal serial clock used within a Master device 341

2.3 Acronyms 342

A Alert 343

BOM Bus Owner Master 344

C Connect 345

EMI Electromagnetic Interference 346

GSID Group Slave Identifier 347

IC Integrated Circuit 348

I/O Input/Output 349

LSB Least Significant Bit 350

MID Master Identifier 351

MPL Master Priority Level 352

MSB Most Significant Bit 353

NRCS Non-Request Capable Slave 354

PC Power Controller 355

PMIC Power Management Integrated Circuit 356

RCS Request Capable Slave 357

SID Slave Identifier 358

SoC System-on-Chip 359

SR Slave Request 360

SSC Sequence Start Condition 361

SPM System Power Management 362

SPMI System Power Management Interface 363

TBO Transfer Bus Ownership 364

USID Unique Slave Identifier 365



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3 References 366

[MIPI01] MIPI Alliance Specification for Device Descriptor Block (DDB), version 1.0, MIPI 367 Alliance, 30 October 2008. 368



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4 SPMI Overview 369

The System Power Management Interface (SPMI) is a two-wire serial interface that connects the integrated 370 Power Controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management 371 Integrated Circuits (PMIC) voltage regulation systems. SPMI enables systems to dynamically adjust the 372 supply and substrate bias voltages of the voltage domains inside the SoC using a single SPMI bus. 373

Within the PC, the SPMI-related functions are referred to as the “Master”. Within a PMIC, the SPMI 374 related functions are referred to as the “Slave”. There may be up to four Master devices and up to sixteen 375 Slaves on a single SPMI bus. Multiple SPMI Masters and Slaves can reside on a single IC, on several 376 separate ICs or any combination of the two. 377

A Slave device that can initiate Sequences on a SPMI bus is called a Request Capable Slave (RCS) device. 378 A Slave device that can not initiate Sequences is called a Non-Request Capable Slave (NRCS) device. 379

This Specification defines the operating states, the command set, the physical interface, and the protocol for 380 data communication between SPMI devices on a SPMI bus to insure the compatibility of command and 381 data transfers. The SPMI Command Sequence set includes Slave and Master addressing, control of the 382 Slave operating state, register read from and register write to Master and Slave devices, as well as 383 commands supporting the use of MIPI Device Descriptor Block data read and bus management. 384

4.1 System Overview 385

The minimum system configuration consists of two SPMI devices one of which shall be a SPMI Master 386 device. 387

A more complex system may include up to four separate SoCs with up to four SPMI Masters. Up to sixteen 388 logical Slaves may be connected to these Master devices. The Slaves may reside on one or more physical 389 devices. The Slave devices may provide supply voltages to the SoCs or perform other functions controlled 390 via the SPMI. Figure 1 shows an example SPMI system. 391

Peripheral Device 1(With one logical interface)

SPMI Slave Interface

SoC 1

SPMI Master

Interface

SPMI Master

Interface

SoC 2

SPMI Master

Interface

SoC 3

SPMI Master

Interface

Peripheral Device 2(Complex multi-function device with two logical

interfaces)

SPMI Slave Logical Interface 1

SPMI Slave Logical Interface 2

SCLK

SDATA

392 Figure 1 SPMI System Example 393

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4.2 SPMI Protocol Overview 394

The SPMI protocol has the following features: 395

• Bus Arbitration –SPMI uses a Bus Arbitration process for allocating traffic on the bus between the 396 Master devices and Request Capable Slave devices. See Section 8. 397

• Master Connection and Disconnection – A process for a Master to connect to, and disconnect 398 from, an Initialized or an Uninitialized SPMI bus. See Section 9. 399

• Slave Initiated Communication – A process for a Request Capable Slave to initiate Sequences to 400 Masters or other Slaves. See Section 10. 401

• ACK/NACK response for robust communication 402

The SPMI protocol has the following requirements: 403

• Enumeration – Each Master or Slave device needs a unique identifier to communicate on using 404 SPMI. See Section 7. 405

• SPMI Master Requirements – A SPMI Master needs to support a minimum set of functions as 406 defined in Section 11 and 13. 407

• SPMI Slave Requirements – A SPMI Slave needs to support a minimum set of functions as 408 defined in Section 12 and 13. 409

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5 Physical Interface 410

5.1 I/O Structures 411

The SPMI is a two-wire interface between SPMI devices that shall have two signals, one serial bi-412 directional data signal (SDATA) and one clock signal (SCLK) controlled by a SPMI Master. Figure 2 413 shows the I/O structures required for the data signal for both Master and Slave. 414

TX DATA

RX DATA

TX DATA

RX DATA

To other SPMI devices

SDATA

SPMI Master SPMI Slave

READ/WRITEREAD/WRITE

Implementation alternatives for pull-down resistance415 416

Figure 2 SDATA Master and Slave I/O Cells 417

Figure 3 shows the I/O structures required for the clock signal for both Master and Slave. 418

SCLK OUT

SCLK OUTENABLE

SCLK IN

SCLK IN

To other SPMI devices

SCLK

SPMI Master SPMI Slave

SCLK INENABLE

Implementation alternatives for pull-down resistance419 420

Figure 3 SCLK Master and Slave I/O Cells 421

SDATA and SCLK pull-down resistors may be implemented using external components instead of 422 integrated resistors. The alternative implementations are shown in red in Figure 2 and Figure 3. A SPMI 423



19

Master device does not have pull-down resistors. See Table 1 for pull-down resistor specifications. Devices 424 shall be implemented such that contention (devices driving different levels at the same time) on SCLK or 425 SDATA does not cause irreversible damage to the line driver. 426

The I/O cells shall be implemented with high impedance input structures and output drivers that are high 427 impedance when not active. I/O cells with typical CMOS structures usually provide these characteristics. 428

5.1.1 I/O Configuration with Multiple Slaves and Masters 429

The SPMI Specification supports up to sixteen logical Slave devices on a single or on multiple physical 430 Slave ICs. Each physical Slave device has one SCLK input and one SDATA bidirectional interface. Each 431 physical Slave device can have pull-down resistors in the I/O cells, or these pull-down resistors can be 432 provided externally. 433

The pull-down resistances of a SPMI Slave and the total system are specified in Table 1. If more than four 434 physical Slave devices are connected to the bus, then the number of individual Slave pull-down resistors 435 shall be adjusted such that the total system pull-down resistance specification is met. 436

Table 1 SPMI Pull-down Resistance Specifications 437

SDATA Pull-down SCLK Pull-down

Units Min Max Min Max

SPMI Slave 0.5 2.0 0.5 2.0 MΩ

Total System 0.125 2.0 0.125 2.0 MΩ

The different physical Slave devices connect to the bus in parallel. Any logical Slave devices inside a 438 physical Slave device share the common I/O structures of the physical device. 439

SPMI allows the use of up to four Master devices and up to sixteen Slave devices on a single bus with the 440 use of Bus Arbitration. 441

5.2 I/O Voltage and Logic Levels 442

SCLK and SDATA are CMOS-like signals, i.e. single-ended, ground referenced, rail-to-rail, voltage mode 443 signals. Therefore, electrical specifications in this document are given relative to the I/O supply voltage, 444 VDD. The SCLK and SDATA terminals shall use the same signaling levels. 445

The signal levels of the external control and status signals (ENABLE, RESETN and PWROK), if they are 446 present as external signals on Slave devices, are user defined. 447

5.2.1 Signaling Voltages 448

This document uses 1.2 V and 1.8 V signaling to describe various parameters. However, other signaling 449 voltage levels can be used, but are out of scope of this document. 450

A Component using 1.8 V signaling shall meet the requirements given in Table 2. 451

Table 2 Parameters for Components using 1.8 V Signaling 452

Symbol Description Min Max Units

VDD SPMI I/O Supply Voltage 1.65 1.95 V

VTP Positive Going Threshold Voltage 0.4*VDD 0.7*VDD V

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VTN Negative Going Threshold Voltage 0.3*VDD 0.6*VDD V

VH Hysteresis Voltage (VTP - VTN) 0.1*VDD 0.4*VDD V

Additionally, the Component shall have the static output electrical characteristics shown in Table 3. 453

Table 3 Static Electrical Characteristics for 1.8 V Signaling 454

Symbol Description Condition Min Max Units

VOL Output Low Voltage IOL = 2mA 0 0.2*VDD V

VOH Output High Voltage IOH = -2mA 0.8*VDD VDD V

A Component using 1.2 V signaling shall meet the requirements given in Table 4. 455

Table 4 Parameters for Components using 1.2 V Signaling 456


VDD SPMI I/O Supply Voltage 1.1 1.3 V

VTP Positive Going Threshold Voltage 0.4*VDD 0.7*VDD V

VTN Negative Going Threshold Voltage 0.3*VDD 0.6*VDD V

VH Hysteresis Voltage (VTP - VTN) 0.1*VDD 0.4*VDD V

Additionally, the Component shall have the static output electrical characteristics shown in Table 5. 457

Table 5 Static Electrical Characteristics for 1.2 V Signaling 458

Symbol Description Condition Min Max Units

VOL Output Low Voltage IOL = 2mA 0 0.2*VDD V

VOH Output High Voltage IOH = -2mA 0.8*VDD VDD V

5.2.2 SPMI I/O Voltage Supply 459

All Components on a single SPMI bus instance shall use the same I/O voltage level. 460

5.3 Device Classes 461

SPMI supports the concept of device classes by categorizing devices according to the range of supported 462 SCLK frequencies. The two defined SPMI device classes are: 463

• High Speed (HS): 32.000 kHz to 26 MHz, with load up to 50 pF 464

• Low Speed (LS): 32.000 kHz to 15 MHz with load up to 50 pF 465

Physical devices from different device classes may be connected to the same SPMI bus instance. However, 466 the combined bus loading shall not exceed the SPMI-specified value. In addition, the maximum bus clock 467 speed shall not exceed the maximum speed supported by the slowest device on the bus. The slowest 468 nominal bus clock frequency allowed for either device class is 32.000 kHz. 469

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5.4 SPMI Clock (SCLK) 470

The BOM shall drive the SPMI clock signal. All clock Sequences shall start and end with the SCLK signal 471 at logic level zero. A Slave device shall not drive the SCLK signal. A Slave device can hold the SCLK 472 signal low with its pull-down resistor. 473

5.4.1 Electrical Specifications for the Master SCLK Driver 474

SCLK shall not toggle during idle and inactive time periods. SCLK shall only run while data is being 475 transferred on the bus; otherwise SCLK is at logic level zero. The Master device may use an internal 476 SCLK, SCLKint, for monitoring the bus activity in a multi-Master system. The SCLKint frequency is 477 assumed to be the same as the SCLK frequency in this document. 478

To reduce active power consumption, the SCLK line is not terminated. To avoid reflections and over 479 voltage problems on such a bus system, the SCLK line shall be transition time controlled for high speed 480 operation. This constraint makes a conventional CMOS I/O unsuitable for driving the SCLK line at high 481 speeds. The SCLK line may be driven at low speeds using a carefully matched CMOS driver with or 482 without transition time control. 483

The bus diameter, i.e. the maximum physical distance between any transmitter and any receiver, is 484 expected to be less than 15 cm. This constraint implies a minimum allowed transition time of 2.1 ns. To 485 allow larger bus diameters, longer transition times or terminated bus topologies may be used, however such 486 bus instances are out of scope for this document. 487

The minimum allowable transition time on the SCLK line is directly related to the bus diameter of the 488 SCLK line. The longer this bus diameter, the longer the transition time needed to generate a reliable clock 489 signal without reflections and voltage over- and undershoot. 490

When driving the test load specified in Section 5.4.1.1 the SCLK line driver shall conform to the timing 491 characteristics shown in Figure 4. 492

VOLmax

VOHmin

TSCLKOH TSCLKOLTSCLKOTR TSCLKOTR TSCLKOTR

493 Figure 4 Clock Driver Output Waveform Constraints 494

Table 6 SCLK Output Timing Characteristics 495

Symbol Description Low Speed Device High Speed Device Units

Min Max Min Max

TSCLKOH Clock Output High Time 22 12 ns

TSCLKOL Clock Output Low Time 22 12 ns

TSCLKOTR Clock Output Transition (Rise / Fall) Time

2.1 8 2.1 5.3 ns

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The rise and fall times of the clock driver constrain both the maximum operating frequency and length of 496 the SCLK line. 497

All timing characteristics are referenced to VOH and VOL. 498

5.4.1.1 Additional SCLK Driver Timing Requirements 499

The Bus Handover as shown in Figure 9 is a special bus condition that facilitates the change of bus 500 ownership. The SDATA line is driven to a logic level zero while the SCLK is at a logic level one. The 501 SDATA and SCLK lines are released on the falling edge of SCLK, or before another device assumes 502 control of either line from the device driving it initially. The Bus Handover cycle is used at the end of the 503 Transfer Bus Ownership Sequence. 504

Bus Handover Cycle

VOLmax

VOHmin

SCLK

TSCLKZ

TSCLKZ is measured from SCLK VOL level for the master device driving SCLK

Signal not driven; pull-down only

Signal driven

505 Figure 5 Bus Handover Timing 506

The SCLK signal shall also conform to the timing characteristics shown in Figure 5 and Table 7. 507

Timing is referenced to the VOH and VOL levels defined in Section 5.2.1. 508

The TSCLKZ data signal specification is measured from the falling edge of SCLK. 509

Table 7 SCLK Bus Handover Timing Parameters 510


Min Max Min Max

TSCLKZ Clock drive release time 18 10 ns

5.4.2 Electrical Specifications for SCLK Input 511

A SPMI device's set of timing requirements for correct operation shall meet the constraints given in Table 512 8. Its respective Min limits shall be no higher than the values in the table. A glitch rejection filter may be 513 used on the SCLK input. The clock receiver shall be capable of receiving slowly changing edges without 514 glitching. A SPMI device shall implement hysteretic input on the SCLK pin. 515



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VTNmin

VTPmax

TSCLKIH TSCLKIL

516 Figure 6 Received Clock Signal Constraints 517

Timings are referenced to VTPmax and VTNmin. 518

Table 8 Clock Input Timing Requirements 519


Min Max Min Max

TSCLKIH SCLK Input High Time 22 12 ns

TSCLKIL SCLK Input Low Time 22 12 ns

5.5 SPMI Data (SDATA) 520

The SPMI data signal is bi-directional. Data shall be written on the rising edge (transition from logical level 521 zero to logical level one) of the SCLK signal by both Master and Slave devices. Data shall be read on the 522 falling edge (transition from logical level one to logical level zero) of the SCLK signal. 523

5.5.1 Electrical Specifications for the SDATA Driver 524

The same signal integrity issues, maximum distance between any transmitter to any receiver device and 525 signal transition time factors, affect the SDATA line as well as the SCLK line as described in Section 5.4. 526 For this reason, the SDATA driver of a High Speed device shall have transition time control to meet 527 transition time specifications listed in Table 9. 528

The minimum slew time, TSDATAOTRmin, is specified for a single device driving the test load described in 529 Section 5.6. The slew time observed on the SDATA line may be smaller than TSDATAOTRmin when multiple 530 devices are simultaneously driving the bus, e.g. during Bus Request. 531

The output driver of a SDATA terminal shall drive the test loads specified in Section 5.6 with the dynamic 532 specifications shown in Figure 7 and Table 9. 533

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VTNmin

VTPmax

VOLmax

VOHmin

TSDATAOTR TSDATAOTR

SCLK

SDATA

TD TD

534 Figure 7 Bus Active Data Transmission Timing Specification 535

536

Table 9 SDATA Output Timing Characteristics 537


Min Max Min Max

TD Time for Data Output Valid from SCLK rising edge

0 20 0 11 ns

TSDATAOTR SDATA Output Transition (Rise/Fall) Time

2.1 8 2.1 5.3 ns

Timing is referenced to VTPmax, VOHmin and VOLmax. 538

SCLK

SDATA

Bus Park Cycle

VOLmax(VTNmin)

VOHmin (VTPmax)

VOLmax

VOHmin

TSDATAZ

TSDATAZ is measured from SCLK VOL level for the master device driving SCLK and SDATA lineTSDATAZ is measured from SCLK VTN level for a device receiving SCLK and driving SDATA line


Signal driven

539 Figure 8 Bus Park Cycle Timing 540



25

The Bus Park Cycle as shown in Figure 8 is a special bus condition that facilitates the change of SDATA 541 control for bus turnaround purposes. The SDATA line is driven to a logic level zero while SCLK is at a 542 logic level one. The SDATA line is released on the falling edge of SCLK. The Bus Park Cycle is also used 543 at the end of all Sequences with the exception of the Transfer Bus Ownership Sequence. 544

SCLK

SDATA

Bus Handover Cycle

VOLmax

VOHmin

VOLmax

VOHmin

TSDATAZ

TSDATAZ is measured from SCLK VOL level for the Master device driving SCLK and SDATA line


Signal driven

545 Figure 9 Bus Handover Timing 546

The Bus Handover as shown in Figure 9 is a special bus condition that facilitates the change of bus 547 ownership. The SDATA line is driven to a logic level zero while the SCLK is at a logic level one. The 548 SDATA and SCLK lines are released on the falling edge of SCLK. The Bus Handover cycle is used at the 549 end of the Transfer Bus Ownership Sequence. 550

Table 10 SDATA Release Timing Parameters 551


Min Max Min Max

TSDATAZ Data drive release time 18 10 ns

TSDATAZ timing is referenced to VOLmax and VTNmin in Figure 9 and Figure 8, respectively. 552

TSDATAZ data signal specification is measured from the falling edge of SCLK (either from VOLmax when the 553 device is driving SCLK and SDATA lines, or from VTNmin when the device is receiving SCLK and driving 554 the SDATA line). 555

5.5.2 Electrical Specifications for the SDATA Receiver 556

The SDATA receiver may use a glitch rejection filter on the SDATA input. The SDATA receiver shall be 557 capable of receiving slowly changing edges without glitching. A SPMI component shall implement 558 hysteretic input on the SDATA pin. Data receiver timing shall follow the timing of Table 11. 559



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VTNmin

VTPmax

VTNmin

VTPmax

TS

SCLK

SDATA

TH TS TH

560 Figure 10 Bus Active Data Receiver Timing Requirements 561

Table 11 Data Receiver Timing Requirements 562

Symbol Parameter Low Speed Device High Speed Device Units

Min Max Min Max

TS Data setup time 2 1 ns

TH Data hold time 5 5 ns

Timings are referenced to VTPmax and VTNmin and are measured at the input of the device. 563

5.6 Device Characterization 564

The device electrical characteristics for SCLK and SDATA lines listed in Section 5 shall be guaranteed 565 using the device characterization circuit shown in Figure 11. The characterization trace impedance in the 566 figure is only for characterization purpose, and does not reflect real trace impedance in an application that 567 may be different. 568

The slew times (TSCLKOTRmin and TSCLKOTRmax for the SCLK line, TSDATAOTRmin and TSDATAOTRmax for the 569 SDATA line), transient voltage, and transition time specifications of a device shall be characterized at both 570 the smallest and largest loads, represented by 15 pF and 50 pF, respectively, through a transmission line of 571 75 Ω impedance and 15 cm physical length. 572

Z = 75 Ω

Cload = 15 pF and 50 pF

Test point forcharacterization

Device Under Test(DUT)

SCLK or

SDATA15 cm

573 Figure 11 Device Characterization Circuit 574



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5.7 Electromagnetic Interference 575

Electromagnetic Interference (EMI) should be taken into account when designing or selecting I/O drivers 576 for SPMI implementation. The SPMI Specification does not define EMI requirements. The product 577 developer is responsible for managing EMI characteristics and susceptibility to EMI according to the needs 578 of the application. 579



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6 SPMI Constructs 580

The SPMI Specification constructs all Sequences on the interface using individual bits. Bits are organized 581 into Frames and Sequences. See Section 6.1 through Section 6.3 for information on Sequence elements and 582 Section 13 for descriptions of the various SPMI Sequences. 583

6.1 Bit Ordering 584

Bits shall be sent on the bus MSB first. In all figures, bits and Frames are shown such that both individual 585 bits and Frames are represented, in left-to-right, top-to-bottom reading order, as they would transfer across 586 the interface. 587

6.2 Sequences 588

Sequences shall be comprised of the following five events that occur in order: 589

• Bus Arbitration 590

• Transmission of the Sequence Start Condition (SSC) 591

• Transmission of Frames (Command Frame and possibly one or more Data Frames) 592

• Transmission of ACK/NACK for applicable Command Sequences 593

• Transmission of a Bus Park Cycle 594

The last four events, SSC, Frames, ACK/NACK and Bus Park Cycle, form the Command Sequence. 595

6.2.1 Bus Arbitration 596

Bus Arbitration is the process where the Bus shall be allocated to one Master or Request Capable Slave 597 among the devices that may simultaneously request to send a Command Sequence on the bus. See Section 598 8 for details on Bus Arbitration. 599

6.2.2 Sequence Start Condition 600

The Sequence Start Condition shall be a unique condition on the bus identified by a rising edge followed by 601 a falling edge on SDATA while SCLK remains at a logic low level. The SSC is used by a Slave or Master 602 to identify the start of a Command Sequence. 603

The Bus Owner Master shall generate the SSC by driving SDATA to logic level one for one SCLKint 604 period, then to logic level zero for one SCLKint period while holding SCLK at logic level zero as shown in 605 Figure 12. 606

If a Request Capable Slave device (see Section 8) wants to send the Command Sequence following the SSC 607 then the BOM shall send a Bus Park Cycle (see Section 6.2.6) on the last SCLKint period of the SSC. The 608 Bus Park Cycle releases the SDATA line so the Slave device can send the Command Sequence. If the 609 BOM is sending the Command Sequence there is no need for a Bus Park Cycle as the BOM drives the 610 SDATA line during the Command Frame. 611

A Command Frame shall start on the next SCLKint rising edge. 612

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SCLK

SDATA

Sequence Start Condition for Master Initiated Sequence

SCLKint

SPMI bus signal

Signal internal to Bus Owner Master

SDATA

Sequence Start Condition for Slave Initiated Sequence

Bus Park

613 Figure 12 Sequence Start Condition 614

6.2.3 Frames 615

There are three basic types of Frames: 616

• Command Frame, thirteen bits. See Section 6.2.3.1. 617

• Data or Address Frames, nine bits. See Section 6.2.3.2. 618

• No Response Frame, nine or thirteen bits. See Section 6.2.3.3. 619

All Frames consist of data, address or command bits and a parity bit. 620

6.2.3.1 Command Frame 621

A Command Frame shall consist of a 4-bit address field, an 8-bit command field, and a single parity bit. 622 The first two bits of the address field are always zero when sending a master address or MID field. The 623 Command Frame structure is shown in Figure 13. 624

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OR

SDATA C1 C0 P

Slave address Command payload bits Paritybit

C2C3C4C5C6C7SA3 SA2 SA1 SA0

C1 C0 P

Master address / MID Field

Command payload bits Paritybit

SDATA C2C3C4C5C6C70 0 MA1 MA0

SCLK

625 626

Figure 13 Command Frame 627

6.2.3.2 Data and Address Frames 628

A Data or Address Frame shall consist of eight data bits or eight address bits, respectively, and a single 629 parity bit. The Frame structure is shown in Figure 14. The Frame is called an Address Frame when the 630 payload bits carry address information and a Data Frame when the payload bits carry data. The type of data 631 being carried is defined by the position of the Frame within the Sequence. See Section 13 for more 632 information. 633

P

Data / address payload bits Paritybit

SCLK

SDATA D/A7 D/A6 D/A5 D/A4 D/A3 D/A2 D/A1 D/A0

634 Figure 14 Data Frame 635

6.2.3.3 No Response Frame 636

All bits, including the parity bit, of a No Response Frame shall be zero. This Frame may be generated by 637 driving SDATA to logic level zero or passively allowing the pull-down resistor to pull SDATA low for the 638 duration of the Frame. A No Response Frame may be nine bits long if it is a Data Frame or thirteen bits 639 long if it is a Command Frame. 640

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0

No Response payload bits (logic 0)

Paritybit

SCLK

SDATA 0 0 0 0 0 0 0 0

Signal driven by BOM

Signal not driven; pull-down only 641 Figure 15 No Response Data Frame 642

6.2.4 Parity Bit 643

A Frame shall end with a single parity bit. The parity bit shall be driven such that the total number of bits in 644 the Frame that are driven to logic level one, including the parity bit, is odd. For example, a Data Frame 645 with data 0x63 (0b01100011) has a ‘1’ parity bit and a Data Frame with data 0x4C (0b01001100) has a ‘0’ 646 parity bit. 647

6.2.5 ACK/NACK 648

ACK/NACK consists of two cycles that are used to confirm correct completion of a Write Command 649 Sequence and certain other Command Sequences. ACK/NACK shall be used on all Command Sequences, 650 except Read Command Sequences, the Authenticate Command Sequence and the Transfer Bus Ownership 651 Command Sequence. ACK/NACK is not used on Command Sequences where the correctness of the 652 Command Sequence can be confirmed based upon Data Frames received by the Device generating the 653 Command Sequence. ACK/NACK shall be generated as described in Section 13. 654

If a Command Sequence that includes ACK/NACK is performed, the Device generating the Command 655 Sequence shall generate a Bus Park Cycle to transfer control of the SDATA line to the accessed Devices. 656 The Bus Park Cycle permits SDATA turnaround in preparation of the ACK/NACK. 657

After the Bus Turnaround Cycle, the BOM shall provide one clock cycle on the SCLK line. A Device 658 controlling the SDATA line shall return the ACK/NACK value on SDATA. 659

If a Command Sequence that includes ACK/NACK is addressed to one Device using USID or MID, the 660 addressed Device shall respond with an ACK/NACK value of 0b1 if the Command Sequence was received 661 correctly, otherwise it shall respond with an ACK/NACK value of 0b0. 662

If a Command Sequence that includes ACK/NACK is addressed to a group of Devices using GSID, an 663 addressed Device shall keep its SDATA driver in high-Z state if the Command Sequence was received 664 correctly. Only if an error was detected shall a Device respond with ACK/NACK value of 0b1. This 665 procedure avoids race conditions between multiple receiving Devices on SDATA. 666

The Device generating the Command Sequence that includes ACK/NACK shall interpret the ACK/NACK 667 value based on whether it used USID/MID or GSID to send the Command Sequence. 668

After the ACK/NACK, a Device in control of SDATA shall perform a Bus Park Cycle as explained in 669 Section 6.2.6. An example of ACK/NACK using the Register Write Command Sequence is shown in 670 Figure 16. 671

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SA3 SA2 SA1 SA0 0 1 0 A4 A3 A2 A1 A0 P

D6 D5 D4 D2 D1 D0D7 D3 P 0P

SSC Register Write command frame

Data frame BUS PARK

SCLK

SDATA

SCLK

SDATA

ACK/NACK

BUS PARK

1

For reference only

Response by slave

Signal driven by BOM or Request Capable Slave (SCLK always driven by BOM only)Pull-down only.

672 673

Figure 16 Example ACK/NACK using Register Write Command Sequence 674

6.2.6 Bus Park Cycle 675

A Device with ownership of SDATA shall initiate a Bus Park Cycle on SDATA (see Figure 8) at the end of 676 a Sequence, or when the device transfers control of SDATA to another device. The purpose of the Bus Park 677 Cycle is to put the SPMI bus into a known state in preparation for an SDATA signal control change, the 678 start of Bus Arbitration, the start of a Command Sequence, or the start of the bus idle condition. 679

During the Bus Park Cycle, the device releasing SDATA shall drive the SDATA signal to a logic level zero 680 during the first half of the SCLK clock cycle. Thereafter, the device releasing SDATA shall put its SDATA 681 driver into the high impedance state. The BOM controlling the Sequence shall provide a normal SCLK 682 during the Bus Park Cycle except when the Bus Park Cycle occurs during the SSC (see Section 6.2.2). 683

6.3 Bus Idle Condition 684

The SPMI bus is in the “Idle” condition when both SCLK and SDATA signals are at logic level zero and 685 all devices connected to the bus other than the Bus Owner Master (BOM) have their bus driver outputs in a 686 high impedance state. The BOM shall be the only device on the bus that drives the SCLK line, maintaining 687 a strong (low-impedance) low level on that line. A pull-down resistor on SDATA maintains a weak (high 688 impedance) low level on that line. The bus is always in idle condition between the end of a Command 689 Sequence and the beginning of Bus Arbitration. See Figure 17 for an illustration of the bus idle condition. 690

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SCLK

Possible previous SCLK cycles: - Bus idle condition- Bus park cycle

Bus Idle condition Bus Idle condition or Arbitration start

SDATA

SDATA driver stays high-Z

During Bus Idle condition Bus Owner Master drives SCLK low.

Signal driven by device requesting arbitration


Signal not driven; pull-down only 691 Figure 17 Bus Idle Condition 692

6.4 Sequence Priority Classes 693

SPMI bus Sequences shall belong to one of two priority classes: Priority or Secondary Sequences. Priority 694 Sequences are Sequences that are considered by the transmitting device to be of highest urgency and 695 importance, and therefore must be sent as soon as possible. Priority Sequences are always transacted on the 696 bus before any secondary traffic, whether initiated by a Master or a Request Capable Slave. Secondary 697 Sequences are transacted on the bus whenever there is bandwidth left over from the priority Sequences. 698

See Section 8 for information about Bus Arbitration and how the SPMI bus is allocated to the different 699 Master devices and Request Capable Slave devices based on their Sequence classes. 700

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7 Device Enumeration 701

Devices on the SPMI bus are Master or Slave devices. To be able to address devices on the bus, SPMI uses 702 Master Identifier (MID) numbers and Slave Identifier (SID) numbers to identify specific devices or groups 703 of slave devices. 704

Each Master device on a SPMI bus shall have a unique identifier called the Master Identifier (MID). The 705 Master ID number shall be statically assigned by the system integrator. 706

Each Slave device on the bus shall have a unique identifier called the Unique Slave Identifier (USID). The 707 Unique Slave ID shall be statically assigned by the system integrator. 708

If there are less than sixteen Slave devices connected to the SPMI bus, the system integrator may assign 709 more than one Slave ID to a Slave device, provided that the device supports such an assignment. The 710 additional Slave Identifier numbers are called Group Slave IDs (GSID). 711

Unique Slave Identifier numbers and Group Slave Identifier numbers are collectively referred to as Slave 712 Identifiers (SID). 713

7.1 Master Identifier 714

A SPMI system may have up to four Master devices. Each Master in a system shall be assigned a unique 715 MID of 0b00, 0b01, 0b10 or 0b11. MIDs do not have to be sequential. For example, in a system with two 716 Master devices, one Master may have a MID of 0b00 and the second Master may have a MID of 0b10. 717

7.2 Unique Slave Identifier 718

A SPMI system may have up to sixteen Slave devices. Each Slave in a system shall be assigned a USID 719 between 0b0000 and 0b1111, inclusive. USIDs do not have to be sequential. For example, in a system with 720 four Slave devices, one Slave device may have a USID of 0b0000, the second Slave device may have a 721 USID of 0b1010, the third Slave may have a USID of 0b1110 and the fourth Slave may have a USID of 722 0b0011. 723

7.3 Group Slave Identifier 724

A Group Slave ID is a SID assigned to a Slave device in addition to the USID it already has. The GSID can 725 be the same for any number of Slave devices, and each Slave device may have multiple GSIDs. GSIDs do 726 not need to be sequential, and it is not mandatory for a Slave device to have a GSID. 727

The use of GSIDs limits the number of USIDs available to the system. For example, in a system that uses 728 two GSIDs, no more than fourteen Slaves devices can exist. 729

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8 Bus Arbitration 730

SPMI supports the existence of one to four Master devices and up to sixteen Slave devices on the bus at the 731 same time. The Master and Slave devices share the bus using a Bus Arbitration process to determine which 732 Master or Slave device has access to the bus at a given time. The ability to share the SPMI bus between 733 multiple Master and Slave devices allows sharing common peripheral resources as well as direct 734 Master-to-Master, Master-to-Slave, Slave-to-Slave or Slave-to-Master communications via the bus. 735

A Slave device that can arbitrate for SPMI bus access is called a Request Capable Slave. A Slave device 736 that does not arbitrate for bus access is called a Non-Request Capable Slave. 737

SPMI is an asynchronous bus and thus, when the bus is idle, multiple devices may request access to the bus 738 via Bus Arbitration. A specific Master, called the Bus Owner Master (BOM), monitors the Bus Arbitration 739 requests and subsequently facilitates the Bus Arbitration process to grant the bus to one requestor. 740

8.1 Bus Arbitration Levels 741

There are four different Bus Arbitration levels on the SPMI bus as shown in Table 12. 742

Table 12 Bus Arbitration Levels 743

Priority Bus Arbitration

Level

Description

highest 1 Slave arbitration using the Alert bit (A-bit) for priority Sequences from Request Capable Slave devices

2 Master Priority Arbitration for priority Sequences from Master devices

3 Slave arbitration using the Slave Request bit (SR-bit) for secondary Sequences from Request Capable Slave devices

lowest 4 Master Secondary Arbitration for secondary Sequences from Master devices

The different Bus Arbitration levels are exposed after arbitration request in the order indicated. The lower 744 levels of arbitration only occur when a high level arbitration mechanism has not previously allocated the 745 bus to a specific device. 746

The different Bus Arbitration levels allow the devices sharing the SPMI bus to transmit timing critical and 747 urgent Sequences with minimal latency while Sequences that can tolerate more latency are transmitted 748 when unused bus bandwidth is available. All priority Sequences from Request Capable Slave devices are 749 arbitrated at Bus Arbitration level 1. All priority Sequences from Master devices are arbitrated at Bus 750 Arbitration level 2. Secondary Sequences are arbitrated at Bus Arbitration level 3 and Bus Arbitration level 751 4. 752

Slave arbitration for both Slave Arbitration methods is based on the SID of the Slave devices on the SPMI 753 bus. See Section 8.4. 754

Master arbitration is based on Master Priority Levels that are dynamically rotated among Master devices to 755 provide equal access to the bus. See Section 8.5. 756

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8.2 Conditions 757

A Master shall operate according to the Master Arbitration process described in Section 8.5 even when all 758 other Master devices are disconnected from the SPMI bus. This requirement makes it possible for a 759 disconnected Master or a Request Capable Slave device to access the SPMI bus. 760

Note, each Master on a single SPMI bus instance may generate SCLK at a different frequency as long as 761 the frequency meets the requirements specified in Section 5.3. In addition, each Master may have a 762 different SCLKint frequency. 763

Request Capable Slave devices shall follow the Slave Arbitration process as described in Section 8.4. 764

In a system design with only one Master and no Request Capable Slave devices, Bus Arbitration is not 765 required. 766

Bus Arbitration shall be executed before every Command Sequence on the SPMI bus except in the case of 767 the sole Master just mentioned. 768

Before Bus Arbitration, the SPMI bus shall be in the Idle State, and the BOM shall be present on the bus. In 769 case a BOM is not present, Bus Initialization is needed. Refer to Section 9.3 for a description of SPMI Bus 770 Initialization. 771

8.3 Bus Arbitration Overview 772

Initial Conditions 773

The Bus Owner Master has completed the current Sequence transmitting the last bit of the final Frame. 774 Thereafter, the bus is considered Idle by all Master devices and Request Capable Slave devices on the bus. 775 SDATA is maintained at a logic level zero due to the pull-down resistors. SCLK is driven to a logic level 776 zero by the BOM. 777

Bus Ownership Request 778

During bus Idle, a Master (already active or waking-up) or Request Capable Slave may initiate a Bus 779 Request by asserting SDATA at a logic level one. A Master or Request Capable Slave shall not request the 780 bus within a time period TSDATAZ from the last falling edge of SCLK of the previous Sequence. Master 781 devices and Request Capable Slave devices may issue Bus Requests at the same time. The Bus Arbitration 782 process results in only one Master or Request Capable Slave device having bus ownership. 783

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SCLK

SDATA

TSDATAZ

BUS PARK

End of the previous sequence on the bus New arbitration request allowed

Signal driven by device requesting arbitrationSignal driven by BOM

Signal not driven; pull-down only 784 Figure 18 New Arbitration Delay 785

Bus Arbitration Steps 786

After the BOM has detected SDATA is logic level one, the BOM shall start the SCLK signal based on its 787 internal clock frequency within 64 µs of the Bus Arbitration Request. All other devices participating in the 788 Bus Arbitration process shall thereafter operate based on this clock signal. 789

A device disconnected from the SPMI bus shall ignore the Bus Arbitration and maintain its SDATA and 790 SCLK drivers in a high-Z state. 791

The Bus Arbitration process consists of the following steps: 792

Step 1: Responding to Arbitration Request 793

After SDATA has been asserted to logic level one, the BOM shall produce a SCLK pulse. On the falling 794 edge of the SCLK pulse, a device that is driving SDATA shall put its SDATA driver into a high-Z state. 795 The BOM shall produce a second SCLK pulse on the bus and execute a Bus Park Cycle on SDATA during 796 this SCLK cycle. 797

Step 2: Connecting Master 798

The BOM shall produce a third SCLK pulse. A Connecting Master shall drive SDATA to logic level one 799 during this SCLK pulse and shall put its SDATA driver into a high-Z state on the falling edge of SCLK. If 800 no Master devices are connecting to the SPMI bus, SDATA remains at logic level zero due to the internal 801 pull-down resistors of the devices connected to the bus. 802

If the BOM detects that SDATA is logic level one on the falling edge of SCLK, it shall execute the 803 Connect Sequence before proceeding with Bus Arbitration from Step 3. See Section 8.3.1 for a description 804 of the Connect Sequence. 805

Step 3: Slave Arbitration through Alert-bit 806

The BOM shall provide one SCLK pulse during which a Request Capable Slave shall drive SDATA to 807 logic level one if the device has a priority Sequence to send. If the BOM detects that SDATA is logic level 808 one on the falling edge of SCLK, it shall execute Slave Arbitration process as described in Section 8.4. If 809

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the BOM does not detect logic level one on SDATA on the falling edge of SCLK it shall execute the 810 Master Priority Arbitration process. 811

Step 4: Master Priority Arbitration 812

The BOM shall provide four SCLK pulses for Master Priority Arbitration. A Connected Master with a 813 Priority Sequence to send shall participate in the Master Priority Arbitration as explained in Section 8.5. 814

Step 5: Slave Arbitration using SR-bit 815

The BOM shall provide one SCLK pulse during which a Request Capable Slave device shall drive SDATA 816 to logic level one if it has a Sequence to send. If the BOM detects that SDATA is logic level one on the 817 falling edge of SCLK, it shall execute Slave Arbitration as described in Section 8.4. If the BOM does not 818 detect logic level one on SDATA on the falling edge of SCLK it shall execute the Master Secondary 819 Arbitration. 820

Step 6: Master Secondary Arbitration 821

The BOM shall provide four SCLK pulses for Master Secondary Arbitration. A Connected Master with any 822 Sequences to send shall participate in the Master Secondary Arbitration as described in Section 8.5. This 823 shall end arbitration. 824

If arbitration passes through Step 6 without any device winning the bus, the bus is Idle again. 825

If during Step 3 through Step 6 a device wins arbitration, the arbitration shall be stopped and a Sequence 826 shall be transmitted on the SPMI bus. 827

The flow diagram in Figure 19 illustrates the SPMI Bus Arbitration process. 828

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Bus Idle

C-bit = ’1'?Y

N

Arbitration RequestSDATA = ’1'

BOM provides SCLKRequestors release SDATA on

falling SCLK edge

BOM provides SCLKBOM executes Bus Park

Provide 3 SCLK pulsesSDATA= MID[1],MID[0], BP

A-bit = ’1'? Slave Arbitration

Master Priority Arbitration

Winning Master?

SR-bit = ’1'? Slave Arbitration

Master Secondary Arbitration

Winning Master?

Bus Idle

Y

N

Y

N

N

Y

Y

Hand over bus to new BOMTransmit SSC and sequence

Hand over bus to new BOMTransmit SSC and sequence

N

Transmit slavesequence

Transmit slavesequence

829 Figure 19 Bus Arbitration Flow Diagram 830



40

8.3.1 Connect Sequence 831

The Connect Sequence facilitates connecting new Master devices to the SPMI bus. Master connection is 832 explained in Section 9. 833

The Connect Sequence (C-Sequence) is used to provide the MID of the BOM to a Connecting Master so 834 that the Connecting Master can compute its Master Priority Level (MPL). The MPL is required to 835 participate in Bus Arbitration. A Connecting Master shall initiate the C-Sequence by asserting the C-bit to 836 logic level one during Bus Arbitration. After detecting the C-bit value as logic level one, the BOM shall 837 insert three SCLK cycles into the normal Bus Arbitration process and drive the SDATA line with the 838 following bit Sequence: MID[1], MID[0] and Bus Park Cycle (see Figure 20). After the C-Sequence, the 839 Bus Arbitration shall continue from the Alert bit (A-bit). 840

If the C-bit is logic level zero, the Bus Arbitration shall immediately continue from the A-bit on the next 841 SCLK cycle. 842

Figure 20 illustrates the Bus Arbitration with and without the Connect Sequence. 843

0

BUS IDLE

SDATA

SCLK 0

One (or more) masters or

slaves initiate arbitration

21

BUS PARK

BUS ARBITRATION WITH C-SEQUENCE

1

C MID[1] BP A

1/0 1/0 0


0 1

1

SSC

1/0 1/0 1/0

BUS PARK

MID[0]

0

BUS IDLE

SDATA

SCLK 0

One (or more) masters or

slaves initiate arbitration

21

BUS PARK

C A

0


0 1

1

SSC

1/0 1/0 1/0

Command FrameBUS PARK

BUS ARBITRATION WITHOUT C-SEQUENCE

Command Frame

Signal driven by device requesting or participating in bus arbitration


For reference only

Signal driven by the master winning the arbitration

Signal driven by Connecting Master

Signal not driven; pull-down only.

844 845

Figure 20 Bus Arbitration with and without C-Sequence 846

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8.4 Slave Arbitration 847

A Request Capable Slave shall implement the Slave Arbitration process. A Non-Request Capable Slave 848 device shall ignore the Slave Arbitration process and maintain its SDATA driver in a high-Z state 849 throughout the process. 850

A Request Capable Slave that does not have a Sequence to send, and therefore does not need to participate 851 in the arbitration, shall ignore the Slave Arbitration process and maintain its SDATA driver in a high-Z 852 state throughout the process. 853

A Request Capable Slave shall initiate the Slave Arbitration process by asserting the A-bit or the SR-bit to 854 logic level one during the Bus Arbitration process. The Slave Arbitration process shall be the same in both 855 cases. It is important for the Request Capable Slave to know whether it requests Slave Arbitration using the 856 A-bit or the SR-bit. 857

A Request Capable Slave shall use the A-bit to send a Sequence with Bus Arbitration level 1. A Request 858 Capable Slave shall use the SR-bit to send a Sequence with Bus Arbitration level 3. 859

A Master shall not set the A-bit nor the SR-bit. 860

Slave Arbitration is based on the fixed Slave Address of each Request Capable Slave device. The BOM 861 shall provide eight SCLK pulses during the Slave Arbitration process. 862

During the first SCLK pulse a Request Capable Slave device that requested Slave Arbitration shall drive 863 SDATA to logic level one if the Slave Address bit SA[3] is ‘1’. The Request Capable Slave device shall 864 put its SDATA driver to a high-Z state on the falling edge of SCLK. If SA[3] is ‘0’ the Slave device shall 865 maintain its SDATA driver in a high-Z state throughout the SCLK period. 866

A Request Capable Slave device participating in the arbitration shall read SDATA on the falling edge of 867 SCLK. If SDATA does not match the Slave Address bit SA[3] value for the Slave device then the Slave 868 device shall stop participating in the arbitration process and shall maintain its SDATA driver in a high-Z 869 state for the remainder of the Slave Arbitration process. 870

The BOM shall execute Bus Park Cycle during the second SCLK pulse. A Request Capable Slave shall 871 maintain its SDATA driver in a high-Z state during the Bus Park Cycle. 872

This Sequence is repeated for Slave Address bit SA[2] during the third and fourth SCLK periods. 873

This Sequence is repeated for Slave Address bit SA[1] during the fifth and sixth SCLK periods. 874

This Sequence is repeated for Slave Address bit SA[0] during the seventh and eighth SCLK periods. 875

Figure 21 shows the Slave Arbitration process using the A-bit Slave Arbitration request. 876

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0

BUS IDLE

SDATA

SCLK 0

One (or more) masters or slaves initiate arbitration

BUS PARK

Slave Arbitration

SA3 SA2 SA1 SA0

SSC

1/0 1/0 1/0

Command Frame

1/0 1/0 1/0 1/0

BUS PARK

BUS PARK

BUS PARK

BUS PARK

C

1

BPA



Signal driven by Request Capable Slave


877 Figure 21 Slave Arbitration using the A-bit 878

Figure 22 shows the Slave Arbitration process using the SR-bit Slave Arbitration request. 879

0

BUS IDLE

SDATA

SCLK 0


BUS PARK

BUS PARK

C

Master Priority Arbitration Slave Arbitration

SA31 SA22 SA13 SA0

SSC

1/0 1/0 1/0

Command FrameBUS PARK

BUS PARK

BUS PARK

SR

1 1/0 1/0 1/0 1/0

BUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

A 0



Signal driven by Request Capable Slave


880 Figure 22 Slave Arbitration using the SR-bit 881

A Request Capable Slave device that reads its own address during the Slave Arbitration process wins Slave 882 Arbitration and access to the SPMI bus. All other Request Capable Slave devices lose Slave Arbitration. 883

The BOM shall generate an SSC that completes within TBT (see Section A.2.3) after the end of the Slave 884 Arbitration process. After the SSC, the BOM shall put its SDATA driver in a high-Z state and shall 885 generate thirteen more SCLK pulses. During the thirteen SCLK pulses, the Request Capable Slave device 886 that won Slave Arbitration shall drive the Command Frame of its Sequence on the SPMI bus. The BOM 887 shall also provide any additional SCLK pulses required by the RCS device to complete its Sequence. At the 888 end of the Sequence the SPMI bus is Idle. 889

Unlike Master Arbitration (Section 8.5), Slave Arbitration does not result in a change to the Master Priority 890 Level. Therefore, after Slave Arbitration, and the subsequent Sequence, the BOM shall be the same as the 891 BOM before Slave Arbitration. 892

8.4.1 Slave Request Hold 893

Slave Request Hold is a mechanism that allows a Request Capable Slave device to access the bus despite 894 the fact that Slave Address 0b1111 always win Slave Arbitration if a Request Capable Slave with that 895 address participates in Slave arbitration. The Slave Arbitration process is not fair based on the Slave 896 Addresses alone. 897

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To guarantee other Request Capable Slave devices access to the SPMI bus a Request Capable Slave shall 898 obey the following rules: 899

• If a Request Capable Slave device requests and wins Slave Arbitration using the A-bit, it shall not 900 request Slave Arbitration again using the A-bit until it has observed at least one arbitration process 901 where the A-bit is logic level zero. While waiting for this condition to occur, the Request Capable 902 Slave device may request Slave Arbitration without the A-bit set to logic level one as many times 903 as necessary. 904

• If a Request Capable Slave requests and wins Slave Arbitration using the SR-bit, it shall not 905 request Slave Arbitration again using the SR-bit until it has observed at least one arbitration 906 process where the SR-bit is logic level zero. While waiting for this to occur, the Request Capable 907 Slave device may request Slave Arbitration without the SR-bit set to logic level one as many times 908 as necessary 909

Figure 23 illustrates the state machines that implement these rules. 910

A-bit State Machine SR-bit State Machine

No Message to Send(start state)

Request Slave Arbitration

No new message

Hold Slave Arbitration

New message to send using

A-bit

Lose Slave Arbitration

Win Slave Arbitration and send Sequence

A-bit = ’0' New message to

send

A-bit = ’0' No new

message to send

(Request) Arbitration, A-bit = ’1'

No Message to Send(start state)

Request Slave Arbitration

No new message

Hold Slave Arbitration

New message to send using

SR-bit

Lose Slave Arbitration

Win Slave Arbitration and send Sequence

SR-bit = ’0' New message to

send

SR-bit = ’0' No new

message to send

(Request) Arbitration, SR-bit = ’1'

911 Figure 23 Request Capable Slave Hold State Machines for A-bit and SR-bit Slave 912

Arbitration Requests 913

8.5 Master Arbitration 914

The Master Arbitration process enables up to four Master devices to share the bus. SPMI Master 915 Arbitration takes traffic class into account by allocating the bus for priority traffic before allocating the bus 916 for secondary traffic. The arbitration also takes into account the Master Priority Level for each traffic class. 917 The Master with the highest MPL requesting arbitration is granted the bus first. 918



44

Master Arbitration can occur twice during Bus Arbitration, first as Master Priority Arbitration if no Request 919 Capable Slave requested Slave Arbitration using the A-bit, and again as Master Secondary Arbitration after 920 the SR-bit if that was logic level ‘0’. These two Master Arbitration rounds arbitrate bus for priority traffic 921 and secondary traffic. 922

For the arbitration process, each active Master shall support the following features: 923

• Priority Sequence queue 924

• Secondary Sequence queue 925

• Master Priority Level (see Table 13) 926

Note that in the following sections, SCLKint signal refers to the internal clock signal of a Master. There is 927 no phase or frequency relationship required between the different SCLK frequencies in separate Master 928 devices. The SCLK bus line is driven by the Bus Owner Master SCLKint signal, thus the frequency of 929 SCLK bus line changes when the ownership of the bus is changed from one Master to another one. An 930 example Master Priority Arbitration Sequence is shown in Figure 24. 931

0

BUS IDLE

SDATA

SCLK0


1

SSC

1/0 1/0 1/0

FRAMEBUS PARK

C

BUS PARK

MPL0 MPL1 MPL2 MPL3

BUS PARK

BUS PARK

A





932 Figure 24 Master Priority Arbitration Example 933

Master arbitration shall be between one and four SCLK cycles long. Each Master is assigned an SCLK 934 cycle depending upon its Master Priority Level. The Master with MPL=0 shall assert a logic level one 935 during the rising edge of the first SCLK cycle if it is requesting to send a Sequence. A Master with MPL=1, 936 2, or 3 shall assert a logic level one during its respective SCLK cycle if a Master with a higher priority has 937 not already asserted a logic level one. A Master not requesting to send a Sequence should initiate a Bus 938 Park Cycle during its SCLK cycle. 939

During Master Priority Arbitration only Master devices with priority Sequences shall participate. If no 940 Master devices are granted the bus ownership during the Master Priority Arbitration the Bus Arbitration 941 continues with the SR-bit as explained in Section 8.3. 942

If SR-bit is logic level zero Master secondary arbitration shall be performed. Master secondary arbitration 943 is executed in the same way as the Master Priority Arbitration, with the exception that Master devices with 944 Sequences of any traffic class shall participate. 945

An example of Master secondary arbitration is shown in Figure 25. A Master with MPL=1 needs to send a 946 secondary Sequence. The Master with MPL=1 requests Bus Arbitration. The BOM responds by providing 947 Bus Arbitration clock. No other devices have any Sequences to send so the Bus Arbitration proceeds to 948 Master secondary arbitration (as explained in Section 8.3) where Bus Arbitration results in the bus being 949 granted to the Master. 950



45

0

BUS IDLE

SDATA

SCLK0


Master Priority Arbitration Master Secondary Arbitration

1

SSC

1/0 1/0 1/0

SEQUENCEBUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

C SRA MPL0 MPL1 MPL2 MPL3 MPL0 MPL1 MPL2 MPL3





951 Figure 25 Master Secondary Arbitration Example 952

During the SSC, each connected Master shall calculate its MPL for the next arbitration round, using the 953 round-robin arbitration algorithm, as described in Section 8.6. 954

The outcome of this protocol is that all Master priority Sequences are transacted on the bus before any 955 Master secondary Sequences are transacted. All Master devices take turns controlling the bus until all 956 Master devices run out of Master priority traffic. Thereafter, the same Sequence is repeated for Master 957 secondary traffic as long as there are Master Sequences remaining or until Master priority traffic is 958 generated again. 959

If no Master has any Sequences to transmit the bus goes idle with both SCLK and SDATA signals at logic 960 level zero; SDATA held at a logic level zero by the passive pull-down resistors and SCLK driven to a logic 961 level zero by the BOM. The bus is then Idle. 962

8.5.1 SCLK Handover 963

When a Master wins arbitration the SCLK line control shall be transferred from the present BOM to the 964 winning Master, which then becomes the new BOM. 965

The present BOM shall detect Master Arbitration end by sampling the SDATA on the falling edge of 966 SCLK. If SDATA is logic level one the present BOM shall release the SCLK line. 967

The new BOM shall wait for one of its SCLKint clock cycles before driving the SDATA line to logic level 968 zero and then sending the Sequence Start condition. SSC shall be completed within TBT of SDATA being 969 driven to logic level zero. At the start of the Sequence Start Condition the new BOM shall drive the SCLK 970 line to logic level zero. After the SSC the new BOM shall start the Command Frame immediately. See 971 Figure 26. 972

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SCLK

One SCLK_intwait period

SDATA

SCLK_int of new BOM

SSC

Arbitration Clock

Bus Park

<TBT

Signal driven by the original BOM

Signal driven by masters losing arbitration

Intermal signal in the new BOM

Signal driven by master winning the arbitration, the new BOM


973 974

Figure 26 SCLK Handover Sequence 975

The SSC allows all Master devices and Slaves connected, or connecting, to the bus to synchronize to the 976 bus activity. See Section 6.2.2 for information about the SSC. 977

8.6 Determining Master Priority Level for Master Arbitration 978

The MPL of a Master device changes after each Sequence that is sent on the bus using a Round-Robin 979 algorithm. The Round-Robin algorithm has several advantages: 980

• Provides access to the bus for all Master devices 981

• The worst-case latency for a Master requesting the bus is easily predicted: it is always proportional 982 to the number of Master devices connected on the bus minus one. 983

• Knowing the MID of the Bus Owner Master is sufficient for all Master devices, connected or 984 connecting ones, to set their MPL without ambiguity since MPL=3 for the Bus Owner Master. See 985 Section 9.2 for information about connecting to SPMI bus. 986

A Master shall calculate its new MPL according to the original MPL of the winning Master. For example, 987 if the winning Master originally had MPL=0, a Connected Master would add three (see Table 13) to its 988 current MPL (modulo 4) to determine its new MPL. Similarly, if the winning Master originally had a 989 MPL=1, 2, or 3, all connected Master devices would add 2, 1, or 0, respectively, to their current MPL 990 (modulo 4) to determine their new MPL. 991

Table 13 New Master Priority Level Calculation 992

Priority Winning Master Original MPL Master Priority Level Adder

highest 0 +3

1 +2

2 +1

lowest 3 +0

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Formula for calculating the new MPL is: 993

MPL(n+1) = (MPL(n) + MPLA) modulo 4 994

Where: MPL(n+1) = new Master Priority Level 995

MPL(n) = existing Master Priority Level 996

MPLA = Master Priority Level Adder from Table 13 997

A Connected Master device shall change its MPL only upon detection of the SSC. The Master Priority 998 Level shall not be changed as a result of Slave Arbitration. 999

Table 14 shows an example of the Round-Robin arbitration Sequence. In this example, it is not necessary 1000 that all Master devices are connected on the bus. 1001

Table 14 Round-Robin Arbitration Sequence 1002

Master ID MPL, Sequence n

New Bus Request for

Sequence n+1

MPL, Sequence n+1

New Bus Request for

Sequence n+2

MPL, Sequence n+2

0 MPL = 0 MPL = 2 MPL = 0

1 MPL = 1 Requester1 MPL = 3 Requester MPL = 1

2 MPL = 2 MPL = 0 MPL = 2

3 MPL = 3 Requester MPL = 1 Requester2 MPL = 3

1. Master ID1 wins arbitration 1003

2. Master ID3 wins arbitration 1004

8.7 Bus Arbitration Error Handling 1005

The SPMI protocol is designed to be robust against Electro-Magnetic Interference (EMI) that might induce 1006 noise spikes on the SCLK and/or SDATA lines. This section describes the behavior of SPMI Bus 1007 Arbitration when there is a noise spike on SDATA while the bus is in the Idle condition. Noise spikes are 1008 not expected on SCLK since the BOM drives a logic level zero on the SCLK during Idle. 1009

If a noise spike occurs on SDATA before arbitration starts, a false bus request is detected. In this case, 1010 there are no Master devices or Request Capable Slave devices requesting the bus, thus C-, A- and SR-bit 1011 shall be logic level zero as shall be all Master arbitration bits. The arbitration shall end with no device 1012 winning the arbitration and the bus shall be Idle. 1013

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0

BUS IDLE

SDATA

SCLK0

Master Priority Arbitration Master Secondary Arbitration

0 01 12 23 3

BUS PARK

C

NOISESPIKE

BUS IDLE

BUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

BUS PARK

A SR

Noise

Signal driven by other masters



1014 Figure 27 False Bus Request Detection 1015

If a noise spike occurs on SDATA during either the Master Priority or Secondary arbitration, it would 1016 appear that a Master is requesting the bus when in reality, it is not. In this situation, there would be no SSC. 1017 If the SSC is not detected on the bus for at least the Bus Timeout Period TBT (see Figure 28), the BOM shall 1018 retain ownership of the bus and Master Priority Levels shall remain the same. 1019

Noise Spike

0

BUS IDLE

SDATA

SCLK0


0 1 2

21

BUS PARK

C A

BUS PARK

TBT wait time for SSC

Arbitration Restarts

(or bus idle)

Bus Arbitration Request

BUS PARK

BUS PARK

Noise

Signal driven by BOMSignal driven by device requesting or participating in bus arbitrationSignal not driven; pull-down only.

1020 Figure 28 Noise During Priority Slots of the Bus Arbitration 1021

If a Master detects another Master has used the Master Priority Level that it was assigned, the Master shall 1022 disconnect from the bus and connect again. 1023

In case noise during arbitration causes accidental Slave Arbitration, the BOM shall assume there is a Slave 1024 that won the arbitration in any case. Since no slave requested arbitration, a No Response Frame will be seen 1025 on the Bus during the Command Frame. The BOM and any other connected device on the bus shall detect a 1026 corrupt Command Frame. As a result of this the BOM shall stop SCLK and the bus shall be idle. Figure 29 1027 shows an example of noise induced Slave Arbitration. 1028



49

0

BUS IDLE

SDATA

SCLK0


21

BUS PARK

Slave arbitration

SA3 SA2 SA1 SA0

SSCBUS PARK

BUS PARK

BUS PARK

BUS PARK

C BPA

Noise spike

SSC NO RESPONSE FRAME BUS IDLE

SDATA

SCLK


Initial arbitration request

Noise

For reference only


1029 Figure 29 False Slave Arbitration due to Noise 1030



50

9 Master Connection and Disconnection 1031

9.1 Definitions 1032

Connecting to the SPMI bus is the process where a Master device gains access to the Bus Arbitration 1033 process after the bus is initialized. 1034

If the bus is uninitialized then the process of accessing the bus is called Bus Initialization as explained in 1035 Section 9.3. 1036

Disconnecting from the SPMI bus is the process where a Master device ceases to participate in the Bus 1037 Arbitration process. After disconnecting from the bus, a Master device shall not send Sequences on the bus 1038 without first connecting to, or initializing, the bus. 1039

The SPMI bus is Initialized when there is at least one active Master (the Bus Owner Master). 1040

The SPMI bus is Uninitialized when there is no BOM on the bus. This state results when all Master 1041 devices, including the Bus Owner Master, disconnect from the bus or when the BOM disconnects from the 1042 bus without passing bus ownership to another Connected Master. 1043

INITIALIZED BUSBus Owner Master exists

UNINITIALIZED BUSNo Bus Owner Master

One or more masters connect to the SPMI

bus using the bus initialization procedure

Last connected master disconnects from the SPMI bus using the

Transfer Bus Owership command

Bus Owner Master disconnects using the Transfer Bus Ownership command, but

other masters are still connected

1044 Figure 30 SPMI Bus States 1045

9.2 Master Connecting on the Bus 1046

When connecting to the SPMI bus, a Master device attempts to acquire a MPL so it may participate in the 1047 Master Arbitration process. In order to get a MPL the Master device needs to know the MID of the BOM 1048 or, if the bus is uninitialized, become the BOM. 1049

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A Connecting Master can use any of three different procedures to connect to the SPMI bus. Since the 1050 Connecting Master does not know if the bus is initialized, i.e. if there is a BOM connected to the bus, it 1051 shall simultaneously monitor the interface for SCLK activity (procedure 2) and look for a SSC (procedure 1052 1) to determine the appropriate procedure to use to connect to the bus. The three procedures can be 1053 summarized as follows: 1054

1. If the Connecting Master detects a SSC it uses the procedure described in Section 9.2.1 to connect 1055 to the bus. This procedure is guaranteed to work even if the bus is busy. 1056

2. If the Connecting Master detects the Bus Idle state (both SCLK and SDATA are logic level zero), 1057 it uses the procedure described in Section 9.2.2 to connect to the bus. 1058

3. If the Connecting Master detects Bus Arbitration (SCLK is logic level zero and SDATA is logic 1059 level one), it uses the procedure described in Section 9.2.3 to connect to the bus. 1060

Together these procedures ensure that a Connecting Master is either notified of the MID of the BOM or the 1061 Connecting Master initializes the SPMI bus and becomes the BOM. Any number of Master devices may try 1062 to connect simultaneously or with arbitrary timing in relation to each other. 1063

9.2.1 Connecting by Detecting SSC 1064

Whenever the Connecting Master detects an SSC, it shall connect to the bus using the following procedure. 1065

Step 1: The Connecting Master shall decode the Frames following the SSC to determine the 1066 Command Sequence end. This is possible as Command Sequence length is determined by the 1067 Command Frame in the Command Sequence. 1068

Step 2: After the Command Sequence ends, the Connecting Master shall request Bus Arbitration 1069 unless another device has already done so. 1070

Step 3: Once the Bus Arbitration request is set (SDATA is logic level one), the Connecting Master 1071 shall wait for (MID+1)*TBT for the arbitration clock to start. 1072

Step 4-A: If the arbitration clock starts (SCLK signal starts) there is a BOM on the bus. The 1073 Connecting Master shall set the C-bit during Bus Arbitration, then monitor the MID of the BOM 1074 in the C-Sequence (see Section 8.3.1) and set its MPL based on Table 15. 1075

Step 4-B: If (MID+1)*TBT expires before SCLK starts the Connecting Master shall assume the 1076 role of BOM and shall start the arbitration clock immediately after (MID+1)*TBT has expired. 1077

Step 1 through Step 3 and Step 4-B result in Bus Initialization. Figure 31 shows a flow diagram of the 1078 procedure. Bus Initialization is further explained in Section 9.3. 1079



52

Master wants to connect to SPMI bus

Detect SSC?

Decode sequence until end of sequence is reached

N

Y

N

Y

SCLK activity?

(MID +1) * TBTexpired?

Assume BOM role. Start Arbitration clock immediately.

Arbitration clock just started, BOM exists, use C-sequence

to connect to busY

N

Drive SDATA to ’1'

Note: This procedure runs simultaneously with the Detecting Bus Idle procedure 1080 Figure 31 Detecting SSC to Connect to Bus Flow Diagram 1081

9.2.2 Connecting by Detecting Bus Idle 1082

If the Connecting Master has not yet detected SSC, it shall monitor the SPMI bus for the Bus Idle 1083 condition. The Connecting Master shall start an internal timer to wait for TBT to expire while SCLK and 1084 SDATA are both logic level zero. 1085

Whenever SCLK signal is detected to be logic level one the timer shall be reset to zero and started again. 1086

If SDATA is detected to be logic level one, the Connecting Master shall try to use the procedure explained 1087 in Section 9.2.3 instead. 1088



53

If the TBT timer expires and SDATA and SCLK are both logic level zero, the SPMI Bus is idle. Thereafter, 1089 the Connecting Master shall connect to the bus using the following procedure. Note that these steps are the 1090 same as Step 2 through Step 4 as explained in Section 9.2.1. 1091

Step 2: The Connecting Master shall request Bus Arbitration unless another device has already 1092 done so. 1093

Step 3: Once the Bus Arbitration request is set (SDATA is logic level one), the Connecting Master 1094 shall wait for (MID+1)*TBT for arbitration clock to start. 1095

Step 4-A: If arbitration clock starts (SCLK signal starts), there is a BOM on the bus, and the 1096 Connecting Master shall set the C-bit in the arbitration Sequence, then monitor the MID of the 1097 BOM in the C-Sequence (see Section 8.3.1) and set its MPL based on Table 15. 1098

Step 4-B: If (MID+1)*TBT expires before SCLK starts, the Connecting Master shall assume the 1099 role of BOM, and shall start arbitration clock itself immediately after (MID+1)*TBT has expired. 1100

Step 2, Step 3 and Step 4-B result in Bus Initialization. Figure 32 shows a flow diagram of the procedure. 1101 Bus Initialization is further explained in Section 9.3. 1102



54

N

N

N

Y

Reset TBT counter to zero

SCLK activity?

SDATA = ’1' ?

TBT expired?

Drive SDATA to ’1'

SCLK activity?


Assume BOM role. Start Arbitration clock immediately.

Arbitration clock just started, BOM exists, use C-sequence

to connect to busY

Y

N

N

Y A Continue with Detecting Bus Arbitration Procedure

Y


Note: This procedure runs simultaneously with the Detecting SSC procedure 1103 Figure 32 Detecting Bus Idle to Connect to Bus Flow Diagram 1104



55

9.2.3 Connecting by Detecting Bus Arbitration 1105

Whenever SDATA is detected to be logic level one and the Connecting Master itself has not yet requested 1106 Bus Arbitration, either a Request Capable Slave or another Master has requested Bus Arbitration and there 1107 might be multiple other Masters in the middle of the process of connecting to the SPMI bus. 1108

The Connecting Master shall use the following procedure. 1109

Step 1: The Connecting Master shall start a timer counting for 5*TBT. If SCLK signal arrives 1110 during this time, the Master shall exit this procedure and try to use processes described in Section 1111 9.2.1 and Section 9.2.2 instead. If SDATA signal goes to logic level zero during the 5*TBT period, 1112 there has been noise on the bus, and the Connecting Master shall use processes described in 1113 Section 9.2.1 and Section 9.2.2 instead. 1114

Step 2: If 5*TBT expires and SDATA is still logic level one, the Connecting Master shall 1115 immediately assert SCLK to logic level one and start counting for (MID +1)*TBT. The Connecting 1116 Master shall also drive SDATA to logic level one continuously. 1117

Step 3. The Connecting Master shall release SCLK within 64 µs of setting SCLK to logic level 1118 one and set its SCLK drive output to a high-Z state. 1119

Step 4-A: If while waiting for (MID+1)*TBT to expire the Connecting Master receives SCLK 1120 signal then a BOM exists on the bus and normal arbitration continues from the second SCLK 1121 pulse in arbitration Sequence. During Bus Arbitration the Connecting Master shall set C-bit to 1122 logic level one, observe the MID of the BOM during the next two SCLK cycles (see Section 1123 8.3.1), and set its MPL based on the BOM MID and Table 15. After that the Master is connected. 1124 The Connecting Master shall set SDATA driver output to a high-Z state after the C-bit. 1125

Step 4-B: If (MID+1)*TBT expires without SCLK arriving, the Connecting Master shall assume 1126 the BOM role. It will immediately drive SCLK signal to logic level zero for one internal SCLK 1127 period. Thereafter, it shall generate arbitration clock by driving the SCLK line. The Connecting 1128 Master shall keep SDATA at logic level one through the C-bit and then perform the C-Sequence 1129 as explained in Section 8.3.1. The Master is now connected and is the BOM. 1130

Table 15 Connecting Master Priority Level 1131

Present BOM MID Connecting Master

MID = 0 MID = 1 MID = 2 MID = 3

0 MPL = 0 MPL = 1 MPL = 2

1 MPL = 2 MPL = 0 MPL = 1

2 MPL = 1 MPL = 2 MPL = 0

3 MPL = 0 MPL = 1 MPL = 2

Step 1 through Step 3 and Step 4-B result in Bus Initialization. Figure 33 shows a flow diagram of the 1132 procedure. Bus Initialization is further explained in Section 9.3. 1133



56

N

Y

Y

N

Y


Reset 5*TBT counter

SCLK activity?

SDATA = ’1' ?

5* TBT expired?

Drive SCLK to ’1'and release within TBTSet SDATA to ’1' and

maintain until after C-bit.

SCLK activity?


Drive SCLK to ’0' for one SCLK period

Assume BOM role. Continue Arbitration clock from second

SCLK pulse immediately.

Second clock pulse of Arbitration clock just arrived,

BOM exists, use C-Sequence to connect to bus

Y

Y

N

N

N

A

1134 Figure 33 Detecting Bus Arbitration to Connect to Bus Flow Diagram 1135



57

9.3 Bus Initialization 1136

Bus initialization occurs automatically whenever there is no Bus Owner Master on the SPMI bus and a 1137 Master wakes up. The procedures explained in Section 9.2.1, Section 9.2.2 and Section 9.2.3 cause one of 1138 the waking Master devices to become the BOM. 1139

The wakeup procedure allows one, a few or all four Master devices to wake up at the same time, or in any 1140 order concurrently. To illustrate this Figure 34 shows Master wakeup and subsequent bus initialization for 1141 four Master devices concurrently when they are waking up simultaneously, and there is no activity on the 1142 SPMI bus. 1143

SCLK

Master ID = 3 4 * TBT

Master ID 3 can start arbitration clock.

MASTER ID 3

TBT

0SDATA

SCLK



MASTER ID 2

TBT

0SDATA

SCLK0



MASTER ID 1

TBT

0SDATA

0

BUS NOT INITIALIZED

SDATA

SCLK0

One (or more) masters initiate arbitration

Slave intiates arbitration

2

Master ID = 0 TBTMaster ID 0 can start

arbitration clock.

MASTER ID 0

TBT

1

Master wakes up internally and starts

bus monitoring period

0

0

For reference only

Signal driven by Master or Request Capable Slave (SCLK always driven by BOM only)


1144 1145

Figure 34 Bus Initialization 1146

Figure 35 shows bus initialization when a Request Capable Slave device is requesting Bus Arbitration 1147 before a BOM is on the SPMI bus. In this case, the waking Master shall detect that the SDATA line is logic 1148 level one, and shall proceed to connect to the bus using the process explained in Section 9.2.3. Figure 35 1149 shows the SCLK and SDATA activity for all Master devices initializing the bus at the same time to clarify 1150 the staggering mechanism that allows Master devices to independently wake up without disturbing each 1151 other. 1152

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1

BUS NOT INITIALIZED

SDATA

Master knows this is not a normal wakeup sequence or arbitration clock would have started. Master sets SCLK ’1' and releases it before 64 µs has expired.

Master sets SDATA ’1'

2

All waking masters start to measure time from rising edge

of SCLK

1

Master wakes up internally and starts bus monitoring period. Sees SDATA ’1'

2 * TBT

0

All masters have to release SCLK <64µS.

MASTER ID 3

TBT

Master ID 0 can start arbitration clock. 1st SCLK cycle is ’0'



Master ID 3 can start arbitration clock. 1st SCLKcycle is ’0'

3 * TBT 4 * TBT64 µs

Monitoring Period > 5 * TBT

0

0

SCLK 0

MASTER ID 2 SCLK

MASTER ID 1 SCLK

MASTER ID 0 SCLK

For reference only

Signal driven by master ID 3





1153 Figure 35 Bus Initialization with Pending Bus Arbitration Request by RCS 1154

9.4 Disconnecting from the Bus 1155

If a Master is not currently the Bus Owner Master, it may disconnect at any time it does not request the bus 1156 for sending a Sequence simply by ceasing to track the Master Arbitration Level and stopping any bus 1157 management related functions. A Master shall use the connecting procedure described in Section 9.2 if it 1158 wants to reconnect to the bus. 1159

A Master may disconnect at any time after completing a Sequence. A Master shall not disconnect after it 1160 has requested the bus by asserting SDATA to logic level one, nor in the middle of a Sequence. If the Bus 1161 Owner Master wants to disconnect from the bus it shall send the Transfer Bus Ownership Sequence to 1162 announce its intention to leave the bus and to request another connected Master, if any, take bus ownership. 1163 Refer to Section 13.2.6 for details on the Transfer Bus Ownership Sequence. In no active Master devices 1164 remain on the bus at the end of the Disconnect Sequence, the bus becomes uninitialized. 1165

9.4.1 Bus Monitoring by Disconnected Master 1166

When a Master disconnects from the SPMI bus it may still monitor bus activity. Such a Master is called 1167 inactive (see Section 11.1.3). A system with Request Capable Slave devices shall have at least one inactive 1168 Master that shall monitor the SDATA line such that it will wake up whenever a Request Capable Slave 1169 requests Bus Arbitration on an uninitialized bus. Else Slave Communication Request (see Section 10) will 1170 not function. 1171

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10 Slave Communication Request 1172

A Request Capable Slave has the capability to initiate and send Sequences to any other Master or Slave 1173 connected to the SPMI bus. 1174

There is no minimum set of commands defined that a Request Capable Slave shall support for a Sequence 1175 initiated by the Request Capable Slave. In this case all commands are optional. However, both the 1176 Non-Request Capable Slave and the Request Capable Slave shall support all mandatory commands when 1177 addressed by another Master or Request Capable Slave. For a complete overview of the mandatory and 1178 optional commands please refer to Figure 55. 1179

The Request Capable Slave devices can request communication on the bus by first requesting Bus 1180 Arbitration by setting SDATA to logic level one (see Section 8.4), and then by an alert request (using the 1181 A-bit) or a Slave request (using the SR-bit), as described in Section 10.1 and Section 10.2. 1182

The BOM is responsible for generating the SCLK during the complete Slave communication Sequence. 1183

The SDATA is handed over to the Slave that won arbitration after the BOM has generated the SSC. The 1184 SSC is described in more detail in Section 6.2.2. 1185

Arbitration for the Request Capable Slave devices is described in Section 8.4. 1186

10.1 Alert bit on an Initialized Bus 1187

The A-bit is used to initiate Slave Arbitration for high priority Slave-to-Slave or Slave-to-Master 1188 Sequences. 1189

When the Initialized bus is idle, one or more Request Capable Slave devices may request Bus Arbitration 1190 and subsequently set the A-bit to logic level one during the A-bit of the arbitration Sequence. 1191

The Slave Arbitration using the A-bit is shown in Figure 21. 1192

Figure 36 illustrates the flow diagram for Slave Arbitration using the A-bit. 1193

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60

Set SDATA ‘1’

Bus idle?>TBTus monitor period

SLAVE ALERTCOMMUNICATION

Release SDATA

SCLK=’1' ?

A-bit passed ?

Locate A-bit & set it ‘1’

Arbitrate for the bus

Arbitration won ?

Slave drives SDATA & sends sequence

Wait for SSC

SLAVE ALERTSERVED

Y

N

N

Y

N

Y

N

Y

1194 Figure 36 Flow Diagram for Slave Communication Request using the A-bit 1195

10.2 Slave Request Bit on an Initialized Bus 1196

The Slave Request bit (SR-bit) is used to request Slave Arbitration when a Request Capable Slave has a 1197 low priority Slave-to-Slave or Slave-to-Master Sequence to be sent. 1198



61

When the Initialized bus is idle, Request Capable Slave devices may request Bus Arbitration by setting 1199 SDATA to logic level one. Then one or more Slaves may initiate a Slave Arbitration by driving SDATA to 1200 logic level one during the SR-bit of the arbitration Sequence. 1201

The Slave Arbitration using the SR-bit is shown in Figure 22. 1202

Figure 37 illustrates the flow diagram for a Slave Arbitration using the SR-bit. 1203

Set SDATA ‘1’

Bus idle?>TBTus monitor period

SLAVE REQUESTCOMMUNICATION

Release SDATA

SCLK=’1' ?

SR-bit passed ?

Locate SR-bit & set it ‘1’

Arbitrate for the bus

Arbitration won ?

Slave drives SDATA & sends sequence

Wait for SSC

SLAVE REQUESTSERVED

Y

N

N

Y

N

Y

N

Y

1204 Figure 37 Flow Diagram for Slave Communication Request using the SR-bit 1205

10.3 Slave Communication Request on Uninitialized Bus 1206

When the bus is Uninitialized, Request Capable Slave devices can still request the bus for sending their 1207 commands by raising SDATA after detecting the bus is idle. The request shall remain active until one 1208 Master initializes the bus, after which the Request Capable Slave shall follow the protocol described in 1209 Section 10.1 and Section 10.2. 1210



62

11 SPMI Master Requirements 1211

11.1 Master Operating States 1212

Figure 38 shows the three operating states, BUS OWNER MASTER, CONNECTED, and 1213 DISCONNECTED, that describe the operation of a SPMI Master. 1214

CONNECTED- Has Master Priority Level

- Follows protocol

Master stops trackingMaster Priority Level

DISCONNECTED- Shall not participate in bus traffic

- May monitor bus activity

BUS OWNER MASTER- Has Master Priority Level 3

- Follows protocol

Master wins arbitrationor wins the Transfer Bus

Ownership sequence

Master disconnects usingthe Transfer Bus

Ownership command

Some other masterwins arbitration

Master connects to SPMI bususing the C-sequence or

bus initialization procedure

1215 Figure 38 SPMI Master Operating States 1216

11.1.1 Bus Owner Master 1217

The Bus Owner Master shall provide the arbitration clock for the arbitration Sequence. There shall be only 1218 one Bus Owner Master at any one time. The Bus Owner Master shall have MPL=3, i.e. the lowest priority. 1219

The Bus Owner Master shall also provide the SSC and SCLK signals for any Sequence transmitted by a 1220 Request Capable Slave. 1221



63

If a Bus Owner Master wishes to disconnect from the SPMI Bus, it shall request arbitration, and after 1222 winning Master arbitration, it shall issue the Transfer Bus Ownership Sequence. After issuing this 1223 Sequence, the Bus Owner Master shall disconnect from the bus. If the BOM loses Master arbitration before 1224 it is able to send the TBO Sequence, it shall no longer be the BOM, and can disconnect simply by ceasing 1225 to follow Bus Arbitration and Master Priority Level as explained in Section 11.1.2. 1226

During the TBO Sequence, the Connected Master with the next lowest MPL after the BOM shall become 1227 the new Bus Owner Master and set its MPL to 3. All other connected Master devices shall recalculate their 1228 MPLs. If the disconnecting Bus Owner Master is the last Connected Master on the bus, the bus state is 1229 referred to as Bus Uninitialized. See Section 9.1 for further details. 1230

11.1.2 Connected Master 1231

A Master is connected to the SPMI bus if it has a MPL and it monitors the Master Arbitration Sequence. If 1232 a Connected Master stops following the Bus Arbitration Sequence for any reason, that Master shall be 1233 deemed to have disconnected from the Bus. A Disconnected Master shall use the Connect Sequence to 1234 reconnect to the bus if the bus is Initialized (see Section 8.3.1) or the Bus Initialization Sequence (see 1235 Section 9.3) if the bus is Uninitialized. 1236

11.1.3 Disconnected Master 1237

A Master is disconnected from the bus if it does not maintain a MPL and does not respond to bus events. A 1238 Disconnected Master shall connect to the bus as described in Section 9.2. A Disconnected Master that 1239 monitors the bus activity is called an Inactive Master. The bus monitoring capability of an Inactive Master 1240 is out of scope for this document. 1241

11.2 Optional Command Support 1242

A Master shall decode all Command Frames defined in Section 13, including Command Frames defined as 1243 optional, to determine the end of a Sequence, even if the Master does not use the optional Command 1244 Frames. 1245

11.3 Master External Control Signals 1246

A Master may implement the same, or similar, control inputs and outputs as those provided for a Slave. See 1247 Section 12.2. 1248

A Master may also have control inputs that correspond to Slave control outputs. For example, a Master may 1249 have a PWROK input corresponding to the Slave PWROK output for the purpose of generating a 1250 power-on-reset. 1251

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12 SPMI Slave Requirements 1252

There are two types of Slaves, Request Capable Slave devices and Non-Request Capable Slave devices. 1253 Request Capable Slave devices can initiate a request for communication on the bus, either by an alert 1254 request (using the A-bit) or a Slave request communication (using the SR-bit). During communication by a 1255 Request Capable Slave, the BOM supplies the clock on the bus. In order to distinguish an initialized bus 1256 from an un-initialized bus, a Request Capable Slave shall have an internal time base so it can determine if 1257 the bus is idle. 1258

12.1 Register Map 1259

The SPMI Slave register slave is a single memory map of up to 65536 8-bit registers. Different commands 1260 may access different portions of the memory map as shown in the following list: 1261

• Register 0 Write command only accesses the register at address 0 1262

• Register Read/Write commands may access registers from address 0 to 31 1263

• Extended Register Read/Write commands may access registers from address 0 to 255 1264

• Extended Register Read/Write Long commands may access registers from address 0 to 65535. 1265

Note 1266 Bus traffic may be reduced by using the appropriate Read/Write command. 1267

12.2 Slave External Control Signals 1268

A Slave may have three distinct I/O signals, to control or indicate the Slave state, that are independent of 1269 the SPMI bus. Other signals unrelated to the SPMI Specification may be present on the Slave. 1270

• Inputs ENABLE and RESETN 1271

• Output PWROK. 1272

12.2.1 RESETN 1273

RESETN is an asynchronous, active-low input signal. Pulling RESETN low shall cause the PMIC to go to 1274 the STARTUP state. Voltage regulation is lost once RESETN is asserted. RESETN is optional. 1275

12.2.2 ENABLE 1276

ENABLE is an asynchronous, active-high input signal. The PMIC shall start its power-up Sequence once 1277 the ENABLE signal goes high while in the STARTUP state. If the ENABLE signal goes low in any state 1278 the device shall go to the STARTUP state. ENABLE is optional. 1279

12.2.3 PWROK 1280

PWROK in an asynchronous, active-high output signal. When PWROK is high, the SPMI controlled 1281 regulators on the PMIC have valid output voltages. PWROK can be used to generate reset signals, etc. for 1282 the SoC. 1283

12.2.4 Exceptional Control Inputs 1284

A PMIC can use information about its operating conditions and environment to adjust its operating state 1285 within those states. These inputs are defined by the manufacturer of the PMIC and should be constrained to 1286

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sensing environmental and operational parameters required to determine the operating conditions of the 1287 device. For example a device may sense input and output voltages, currents, temperature, pressure, ambient 1288 lighting, radiation and so on. 1289

12.2.5 Other Control Inputs and Outputs 1290

If a Slave is part of a larger IC with external control inputs, these external control inputs can be used to 1291 manipulate the RESETN and ENABLE input signals, which are internal to the larger PMIC. If RESETN 1292 and ENABLE operation is different than that specified in Section 12.2.1 and Section 12.2.2 then they shall 1293 be named differently to avoid confusion. The same principle applies to the PWROK output signal. 1294

Figure 39 shows two example implementations. The first implementation is a stand-alone SPMI Slave with 1295 external control inputs and outputs. The second implementation is an integrated SPMI Slave with controls 1296 internal to the host device. 1297

HOST DEVICE

SPMI SLAVEDEVICE

PWROK

ENABLE

RESETN

SDATA

SCLK

STAND-ALONE SPMI SLAVE

SPMI SLAVEDEVICE

PWROK

ENABLE

RESETN

SDATA

SCLK

INTEGRATED SPMI SLAVE 1298 Figure 39 Alternate External Control Signal Configurations 1299

12.2.6 Multiple Logical Slaves on a Single Physical Device 1300

A single physical device may have more than one logical Slave device. In this case the logical Slaves can 1301 share the external control inputs (or corresponding host device internal signals). SPMI protocol commands 1302 operate on individual logical Slaves. A logical Slave’s operation may be Sequenced or coupled to another 1303 Slave’s operation. 1304

12.3 Slave Operating States 1305

SPMI Slaves shall have the four operating states, ACTIVE, SLEEP, SHUTDOWN and STARTUP, as 1306 shown in Figure 40. Separate SHUTDOWN and STARTUP states are provided to allow an independent 1307 SPMI command initiated shutdown process without the requirement to simultaneously configure the 1308 external control signals to prevent an immediate re-boot from the STARTUP state. The external control 1309 signals (see Section 12.2) have priority over the SPMI commands. 1310



66

SHUTDOWN STARTUP

ACTIVE(User Defined)

SLEEP(User Defined)

WAKEUP-command

ENABLE = 0

ENABLE = 1

SHUTDOWN-command

ENABLE = 0

ENABLE = 0

SHUTDOWN-command

Reset (by command or ResetN signal) from any

state

SLEEP-command1311 1312

Figure 40 SPMI Slave State Diagram 1313

12.3.1 STARTUP 1314

The STARTUP state is the default state after a reset. The STARTUP state is entered from any other state if 1315 the ENABLE signal is asserted to logic level zero. All regulators shall be off in this state and the PWROK 1316 output shall be logic level zero. The power-up (or power-down) Sequence of the regulators is device 1317 specific. The Sequences in which voltage regulators activate, and the time required to activate them, 1318 depend on the needs of the target application and SoC. When the ENABLE signal is asserted high, a Slave 1319 device shall transition into the ACTIVE state. 1320

12.3.2 ACTIVE 1321

The ACTIVE state is the normal operating state of a Slave after the power-on Sequence. The state of any 1322 regulator or sub-module on the Slave is either user-defined or specified by the device manufacturer. In the 1323 ACTIVE state, a SPMI Master may control any of the voltages on the PMIC by programming the 1324 corresponding SPMI control registers. Changing the state of a voltage regulator does not necessarily cause 1325 a transition away from the ACTIVE state. 1326

12.3.3 SLEEP 1327

The SLEEP state is another user-defined state and is similar to the ACTIVE state in that the state of any 1328 regulator or sub-module on the Slave is either user-defined or specified by the device manufacturer. The 1329 SLEEP state is meant to allow for a lower power state that may be entered automatically under hardware 1330 control. 1331

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In the SLEEP state the SPMI Master may control any of the voltages on the PMIC by programming the 1332 corresponding SPMI control registers if the internal register clock is available within the Slave. Changing 1333 the state of a voltage regulator does not necessarily cause a transition away from the SLEEP state. 1334

12.3.4 SHUTDOWN 1335

In the SHUTDOWN state, a Slave shall turn off all regulators, thus causing all output voltages to go to 1336 zero. Exit from the SHUTDOWN state is achieved with a RESETN command, external signal or by setting 1337 the external ENABLE to a logic level zero and then back to a logic level one. 1338

12.3.5 Exceptional State Transitions 1339

This document does not specify the external or environmental conditions required for PMIC operation, only 1340 the normal operation that occurs while external and environmental factors are within operating limits. The 1341 PMIC can have operating limit monitoring, and the limit monitoring can affect PMIC state transitions, 1342 triggering state transitions like going to the SHUTDOWN state. New, top-level states may not be added 1343 into the Slave state behavior although sub-states may be added under the top level states. Examples of 1344 exceptional state transitions are PMIC shutdown triggered by excessive die temperature or exceeding the 1345 output current of a regulator. 1346

12.4 Optional Command Support 1347

A Request Capable Slave shall decode all Command Frames defined in Section 13 to determine the end of 1348 a Sequence, even if the Slave does not use the Command Frames. 1349

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13 Command Sequences 1350

The Command Sequences of the SPMI protocol only apply to an initialized SPMI bus. Each Sequence 1351 accomplishes one complete transaction over the interface. Command Sequences shall be sent only by a 1352 Master device or a Request Capable Slave device. A Non-Request Capable Slave device shall not send 1353 Command Sequences. 1354

A SPMI Master device shall support all Command Sequences. A Request Capable Slave device may 1355 support any, all or none of the Command Sequences. A Non-Request Capable Slave device acting as a 1356 receiver may support any, all or none of the Command Sequences. 1357

13.1 Command Sequence Summary 1358

This section describes all Command Sequences defined in the SPMI protocol. 1359

See Section 6 for more information about Sequences and other SPMI constructs. The coding of the 1360 Command Frame is shown in Table 16. 1361

Table 16 Summary of SPMI Commands 1362

Command Frame Payload Description

0x00 to 0x0F Extended Register Write

0x10 Reset

0x11 Sleep

0x12 Shutdown

0x13 Wakeup

0x14 Authenticate

0x15 Master Read

0x16 Master Write

0x17 to 0x19 Reserved

0x1A Transfer Bus Ownership

0x1B Device Descriptor Block Master Read

0x1C Device Descriptor Block Slave Read

0x1D to 0x1F Reserved

0x20 to 0x2F Extended Register Read

0x30 to 0x37 Extended Register Write Long

0x38 to 0x3F Extended Register Read Long

0x40 to 0x5F Register Write

0x60 to 0x7F Register Read

0x80 to 0xFF Register 0 Write

13.2 Command Sequence Descriptions 1363

Each Command Sequence is described in detail in the following sections. 1364



69

13.2.1 Extended Register Write Command Sequence 1365

The Extended Register Write allows write access to the extended register space on a Slave device. One to 1366 sixteen bytes of data shall be written in a single Command Sequence. The extended register address shall 1367 be supplied in a separate Data Frame in the Command Sequence. 1368

Figure 41 shows the Extended Register Write Command Sequence. The Command Sequence starts with the 1369 SSC followed by the Extended Register Write Command Frame, an Address Frame and one or more Data 1370 Frames with the data to be written. Note that the Data Frames immediately follow the Command Frame in a 1371 continuous Sequence. ACK/NACK follows the Data Frame. The Command Sequence ends with a Bus Park 1372 Cycle. 1373

The four LSBs of the Extended Register Write Command Frame, BC[3:0] in Figure 41, indicate the 1374 number of bytes to be written in the Command Sequence. BC3 is the byte count MSB. 0b0000 indicates 1375 one byte shall be written and 0b1111 indicates sixteen bytes shall be written. 1376

The register address in the Command Sequence contains the address of the first extended register to be 1377 written. If more than one byte is written in a single Command Sequence then the Slave’s local extended 1378 register address shall be automatically incremented by one for each byte written up to address 0xFF, 1379 starting from the address indicated in the Address Frame. If the extended register address reaches 0xFF 1380 before the last Data Frame in the Sequence then the content of the register at address 0xFF is overwritten 1381 with the overflow data. 1382



70

SA3 SA2 SA1 SA0 0 0 0 BC2 BC1 BC0 P

P A7 A6 A5 A4 A3 A2 A1 A0 P

D7 D6 D5 D4 D3 D2 D1 D0 P

0 BC3

P

P D7 D6 D5 D4 D3 D2 D1 D0 P

... INTERMEDIATE DATA FRAMES ...

Extended Register Write command frame

Register address (data frame) for first register

First data frame

Last data frame

SSC

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA 0

Buspark

ACK/NACK

Bus Park

1

Signal driven by BOM or Request Capable Slave (SCLK always driven by BOM only)

For reference only


Response by slave

1383 Figure 41 Extended Register Write Command Sequence 1384

13.2.2 Extended Register Read Command Sequence 1385

The Extended Register Read Command Sequence allows read access to the extended register space on a 1386 Slave device. One to sixteen bytes of data shall be read in a single Command Sequence. The extended 1387 register address shall be supplied in a separate Data Frame in the Command Sequence. 1388

Figure 42 shows the Extended Register Read Command Sequence. The Command Sequence starts with the 1389 SSC followed by the Extended Register Read Command Frame, an Address Frame and one or more Data 1390 Frames with the data read from the Slave. A Bus Park Cycle occurs between the Address Frame and the 1391 Data Frames. The Command Sequence ends with a Bus Park Cycle. 1392

The four LSBs of the Extended Register Write Command Frame, BC[3:0] in Figure 42, indicate the 1393 number of bytes to be read in the Command Sequence. BC3 is the byte count MSB. 0b0000 indicates one 1394 byte shall be read and 0b1111 indicates sixteen bytes shall be read. 1395

The register address in the Command Sequence contains the address of the first extended register to be 1396 read. If more than one byte is read in a single Command Sequence then the Slave’s local extended register 1397



71

address shall be automatically incremented by one for each byte read up to address 0xFF, starting from the 1398 address indicated in the Address Frame. If the extended register address reaches 0xFF before the last Data 1399 Frame in the Command Sequence then the content of the register at address 0xFF is read multiple times. An 1400 Extended Register Read command by the Master to an unsupported Slave extended register address results 1401 in a No Response Frame from the Slave. If the address that results from auto-incrementing the Slave’s local 1402 extended register address is for an unsupported register then the Slave sends a No Response Frame to the 1403 Master in place of the Data Frame. The Command Sequence continues from the next extended register 1404 address. 1405

SA3 SA2 SA1 SA0 0 0 1 0 BC3 BC2 BC1 BC0 P

P A7 A6 A5 A4 A3 A2 A1 A0 P

D6 D5 D4 D3 D2 D1 D0 PD7

P D7 D6 D5 D4 D3 D2 D1 D0 P 0


Last data frame (from slave) Bus park

First data frame (from slave)

Extended Register Read command frame

Register address (data frame) for first register Buspark

SSC

0

0

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA


For reference only

Signal driven by slave


1406 1407

Figure 42 Extended Register Read Command Sequence 1408



72

13.2.3 Reset, Sleep, Shutdown, Wakeup Command Sequences 1409

The Reset, Sleep, Shutdown, and Wakeup Command Sequences are similar in format and thus are 1410 described together in this section. Each Command Sequence starts with the SSC. The SSC is followed by a 1411 Command Frame and the Sequence ends with a Bus Park Cycle. The Command Frame is unique for each 1412 command. Figure 43 shows the Command Sequences for these commands and the values for each 1413 Command Frame. 1414

13.2.3.1 Reset 1415

Writing the Reset command initializes the Slave and forces all registers to their reset values. The Slave 1416 shall enter the STARTUP state after receiving a Reset command, and acknowledging it with ACK/NACK. 1417 See Section 12.3.1. 1418

13.2.3.2 Sleep 1419

The Sleep command causes the Slave to enter the user defined SLEEP state after acknowledging it with 1420 ACK/NACK. See Section 12.3.3. 1421

13.2.3.3 Shutdown 1422

The Shutdown command causes the Slave to enter the SHUTDOWN state after using ACK/NACK to 1423 acknowledge the command. See Section 12.3.4. The Slave enters the SHUTDOWN state after a Shutdown 1424 command is received while in either the ACTIVE or SLEEP states. In the STARTUP state, the Shutdown 1425 command is ignored because the reset and enable signals take priority. See Section 12.3. 1426

13.2.3.4 Wakeup 1427

The Wakeup command causes the Slave to move from the SLEEP state to the ACTIVE state. The Slave 1428 acknowledges receiving the Wakeup command using ACK/NACK. See Section 12.3.2 and Section 12.3.3. 1429

SA3 SA2 SA1 SA0 0 C1 C0 P

Slave address Command payload bits Parity

SCLK

SDATA

Command Bits C1 C00 00 11 01 1

RESETSLEEP

SHUTDOWNWAKEUP

0 0 1 0 0

SSC

Command frame

0

Buspark

ACK/NACK

Bus Park

1

Signal driven by BOM or Request Capable Slave (SCLK always driven by BOM only)Signal not driven; pull-down only.

Response by slave

1430 1431

Figure 43 Reset, Sleep, Shutdown and Wakeup Command Sequences 1432

13.2.4 Authentication Command Sequence 1433

The Authenticate command starts a 9-Frame Command Sequence consisting of a Command Frame, four 1434 Challenge Frames and four Response Frames, to interrogate a Slave device for identification. Challenge 1435 and Response Frames are Data Frames. Challenge and response data patterns are manufacturer defined, and 1436



73

may be encrypted. This Command Sequence is intended to support intellectual property management and 1437 device identification. A Slave that does not support the Authentication Command Sequence shall respond 1438 with No Response Frames (see Section 6.2.3.3). Authentication Command Sequence shall not use 1439 ACK/NACK as the Response Frames fulfill this function. 1440

The Authentication Command Sequence starts with the SSC and the Authenticate Command Frame 1441 followed by alternating Challenge and Response Frames. Challenge Frames shall be transmitted using the 1442 Data Frame format. A Slave shall transmit Response Frames using the Data Frame format. Challenge 1443 Frames from the Master are interleaved with Response Frames from the Slave as shown in Figure 44. 1444

SA3 SA2 SA1 SA0 0 0 0 1 0 1 0 0 P

P D7 D6 D5 D4 D3 D2 D1 D0 P

0

D7 D6 D5 D4 D3 D2 D1 D0 P

D7 D6 D5 D4 D3 D2 D1 D0 P D7 D6 D5 D4 D3 D2 D1 D0 P



Challenge frame 1

SSC Authentication command frame

Response frame 1

Challenge frame 2 Response frame 2

Challenge frame 3 Response frame 3

Challenge frame 4 Response frame 4 Bus park

0

Bus Park

0

Bus Park

0

Bus Park

0

Bus Park

0

Bus Park

0

Bus Park

0

Bus Park

0

0

0

SDATA

SCLK

For reference only

Response by slave


1445 1446

Figure 44 Authenticate Command Sequence 1447

13.2.5 Master Write Command Sequence 1448

The Master Write Command Sequence enables a Master or Request Capable Slave in a multi-Master 1449 system to write a register of another Master on the bus. The Command Sequence consists of three Frames: 1450 a Master write Command Frame, a Data Frame with register address and a Data Frame with write data. The 1451



74

Command Sequence also includes the SSC, ACK/NACK and a Bus Park Cycle as shown in Figure 45. A 1452 Slave shall ignore this command. 1453

0 0

MASTER ID#

0 0 0 1

Master Write commandSSC

0 1

Parity

A7 A6 A5 A4 A3 A2 A1 A0 P

Data frame with register address

D7 D6 D5 D4 D3 D2 D1 D0 P

Data frame with write data

1 0 1/0

1/0

P

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

1/0 1/0

0

Buspark

ACK/NACK

Bus Park

1

For reference only


Response by slave

1454 1455

Figure 45 Master Write Command Sequence 1456

13.2.6 Master Read Command Sequence 1457

The Master Read Command Sequence enables a Master or Request Capable Slave to access the register 1458 space of another Master on the bus. The Command Sequence consists of three Frames: a Master read 1459 Command Frame, a Data Frame with a register address and a Data Frame from the other Master with the 1460 contents of the register. The Command Sequence also includes the SSC and Bus Park Cycles as shown in 1461 Figure 46. A Slave shall ignore this command. 1462



75

0 0

MASTER ID#

0 0 0 1

Master Read commandSSC

0 1 0 1 P

Parity

A7 A6 A5 A4 A3 A2 A1 A0 P

Data frame with register address Buspark

D7 D6 D5 D4 D3 D2 D1 D0 P 0

Data frame with register contents Bus park

P 0

0

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA 1/0 1/0


Response by other master

For reference only1463

1464

Figure 46 Master Read Command Sequence 1465

13.2.7 Transfer Bus Ownership Command Sequence 1466

The Transfer Bus Ownership (TBO) Command Sequence enables the transfer of bus ownership to another 1467 connected Master in the event that the BOM wants to disconnect from the bus. This Command Sequence is 1468 required for the Bus Owner Master to disconnect from the bus. 1469

The Transfer Bus Ownership Command Sequence starts with an SSC followed by the TBO Command 1470 Frame and a Data Frame containing responses, if any, from other Master devices on the bus, and ends with 1471 a Bus Handover cycle as shown in Figure 47. When the BOM sends this command, and disconnects from 1472 the bus, it shall use the bus connecting procedure (see Section 9) prior to sending a new Command 1473 Sequence on the bus. 1474

In response to the Transfer Bus Ownership Command Sequence, if a Master is connected, it shall raise 1475 SDATA during the correct SCLK cycle according to its MPL, and subsequently sends its MID on the 1476 following two SCLK cycles followed by zeros to complete the eight data slots, a parity bit, and a Bus Park 1477 Cycle. The first Master that drives SDATA to logic level one shall become the new Bus Owner Master, and 1478 sets its MPL to 3 (lowest priority). Masters that have not become the BOM shall not drive SDATA to logic 1479 level one during its SCLK cycle. Other Master MPLs are defined using the Round-Robin arbitration 1480



76

algorithm. If there are no other Connected Masters on the bus, the Data Frame shall be a No Response 1481 Frame after which the BOM shall disconnect from the bus. 1482

0 0 1 1 0 P

0 1 MID1 MID0 0

Master with PL = 2 responds to TBO command Bus Handover

Transfer Bus Ownership commandSSC

SCLK

SDATA

SCLK

SDATA

0 1 0

Bus park

0000

Case if master with PL=2 is active

0 1 MID1 MID0 0

Master with PL = 1 responds to TBO command

SDATA 0Case if master with PL=2 is not active, but master with PL = 1 is active

0 1 MID1 MID0 0

Master with PL = 0 responds to TBO command

SDATA 0Case if masters with PL=2 and PL = 1 are not active, but master with PL = 0 is active

0

0

No master responds, bus becomes not initialized

SDATACase if no other masters are active

P

P

P

Bus Handover

Bus Handover



Response by other masters

For reference only 1483

Figure 47 Transfer Bus Ownership Command Sequence 1484

13.2.8 Device Descriptor Block Slave Read Command Sequence 1485

The Device Descriptor Block Slave Read Command Sequence starts with an SSC followed by the Device 1486 Descriptor Block Slave Read Command Frame. The response from the Slave is ten bytes long. The bit 1487 order of the Device Descriptor Block is MSB to LSB as shown in Figure 48. MIPI Alliance Specification 1488 for Device Descriptor Block (DDB) [MIPI01] defines the contents of the Device Descriptor Block. 1489



77

SA1 SA0 0 0 1 1 1 P

D7 D6 D5 D4 D3 D2 D1 D0 P

D6 D5 D4 D3 D2 D1 D0 PD7

P D7 D6 D5 D4 D3 D2 D1 D0 P 0


Device Descriptor Block data frame (least significant byte) from slave Bus

park

Device Descriptor Block data frame from slave

Device Descriptor Block data frame (most significant byte) from slave

SSC

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

P

0 0 0

Bus park

Device Descriptor Block Slave Read command

SA3 SA2


Response by slave


Figure 48 Device Descriptor Block Slave Read Command Sequence 1491

13.2.9 Device Descriptor Block Master Read Command Sequence 1492

The Device Descriptor Block Master Read Command Sequence starts with an SSC followed by the Device 1493 Descriptor Block Master Read Command Frame. The response from the Master is ten bytes long. The bit 1494 order of the Device Descriptor Block is MSB to LSB as shown in Figure 49. MIPI Alliance Specification 1495 for Device Descriptor Block (DDB) [MIPI01] defines the contents of the Device Descriptor Block. 1496



78

MA1 MA0 0 0 1 1 0 P

D7 D6 D5 D4 D3 D2 D1 D0 P

D6 D5 D4 D3 D2 D1 D0 PD7

P D7 D6 D5 D4 D3 D2 D1 D0 P 0


Device Descriptor Block data frame (least significant byte) from master

Bus park

Device Descriptor Block data frame from master

Device Descriptor Block Master Read command

Device Descriptor Block data frame (most significant byte) from master

SSC

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

P

0 1 1

Bus park


Response by master


Figure 49 Device Descriptor Block Master Read Command Sequence 1498

13.2.10 Extended Register Write Long Command Sequence 1499

The Extended Register Write Long Command Sequence allows write access to the extended register space 1500 on a Slave device using a 16-bit address. One to eight bytes of data may be written in a single Command 1501 Sequence. The extended register address is supplied in two Address Frames within the Command 1502 Sequence. ACK/NACK shall be used to verify the completion of the entire Extended Register Write Long 1503 Command Sequence. 1504



79

Figure 50 shows the Extended Register Write Long Command Sequence. The Extended Register Write 1505 Long Command Sequence starts with an SSC followed by the Extended Register Write Long Command 1506 Frame, two Address Frames and one or more Data Frames with the data to be written followed by 1507 ACK/NACK. The Command Sequence ends with a Bus Park Cycle. 1508

The three LSBs of the Extended Register Write Command Frame, BC[2:0] in Figure 50, indicate the 1509 number of bytes to be written in the Command Sequence. BC2 is the byte count MSB. 0b000 indicates one 1510 byte shall be written and 0b111 indicates eight bytes shall be written. 1511

The register address in the Command Sequence contains the address of the first extended register to be 1512 written. If more than one byte is written in a single Sequence then the Slave’s local extended register 1513 address shall be automatically incremented by one for each byte written up to address 0xFFFF, starting 1514 from the address indicated in the Address Frame. If the extended register address reaches 0xFFFF before 1515 the last Data Frame in the Command Sequence then the content of the register at address 0xFFFF is 1516 overwritten with the overflow data. 1517



80

SA3 SA2 SA1 SA0 0 0 1 1 0 BC2 BC1 BC0 P

P A7 A6 A5 A4 A3 A2 A1 A0 P

D6 D5 D4 D3 D2 D1 D0 PD7

P D7 D6 D5 D4 D3 D2 D1 D0 P


Last data frame (from master)

First data frame (from master)

Extended Register Write Long command frame

Register address lower byte (data frame)

SSC

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

P A15 A14 A13 A12 A11 A10 A9 A8 P

Register address upper byte (data frame)

SCLK

SDATA

P

0

Buspark

ACK/NACK

Bus Park

1


For reference only

Response by slave

1518 Figure 50 Extended Register Write Long Command Sequence 1519

13.2.11 Extended Register Read Long Command Sequence 1520

The Extended Register Read Long Command Sequence allows read access to the extended register space 1521 on a Slave device using a 16-bit address. One to eight bytes of data may be read in a single Command 1522



81

Sequence. The extended register address shall be supplied in two Address Frames within the Command 1523 Sequence. 1524

Figure 51 shows the Extended Register Read Long Command Sequence. The Command Sequence starts 1525 with the SSC followed by the Extended Register Read Long Command Frame, two Address Frames and 1526 one or more Data Frames with the data read from the Slave. A Bus Park Cycle occurs between the Address 1527 Frame and the Data Frames. The Command Sequence ends with a Bus Park Cycle. 1528

The three LSBs of the Extended Register Read Long Command Frame, BC[2:0] in Figure 51, indicate the 1529 number of bytes to be read in the Sequence. BC2 is the byte count MSB. 0b000 indicates one byte shall be 1530 read and 0b111 indicates eight bytes shall be read. 1531

The register address in the Command Sequence contains the address of the first extended register to be 1532 read. If more than one byte is read in a single Command Sequence then the Slave’s local extended register 1533 address shall be automatically incremented by one for each byte read up to address 0xFFFF, starting from 1534 the address indicated in the Address Frame. If the extended register address reaches 0xFFFF before the last 1535 Data Frame in the Command Sequence then the content of the register at address 0xFFFF is read multiple 1536 times. An Extended Register Read command by the Master to an unsupported Slave extended register 1537 address results in a No Response Frame from the Slave. If the address that results from auto-incrementing 1538 the Slave’s local extended register address is for an unsupported register then the Slave sends a No 1539 Response Frame to the Master in place of the Data Frame. The Command Sequence continues from the 1540 next extended register address. 1541



82

SA3 SA2 SA1 SA0 0 0 1 1 1 BC2 BC1 BC0 P

P A7 A6 A5 A4 A3 A2 A1 A0 P

D6 D5 D4 D3 D2 D1 D0 PD7

P D7 D6 D5 D4 D3 D2 D1 D0 P 0


Last data frame (from slave) Bus park

First data frame (from slave)

Extended Register Read Long command frame

Register address lower byte (data frame) Buspark

SSC

0

0

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

SCLK

SDATA

P A15 A14 A13 A12 A11 A10 A9 A8 P

Register address upper byte (data frame)

SCLK

SDATA




Figure 51 Extended Register Read Long Command Sequence 1543



83

13.2.12 Register Write Command Sequence 1544

Figure 52 shows the Register Write Command Sequence. The Command Sequence starts with an SSC, 1545 followed by the write Command Frame containing the Slave address and the target register address and a 1546 Data Frame containing the data to be written followed by ACK/NACK. The Command Sequence ends with 1547 a Bus Park Cycle. 1548

SA3 SA2 SA1 SA0 0 1 0 A4 A3 A2 A1 A0 P

D6 D5 D4 D2 D1 D0D7 D3 PP

SSC Register Write command frame

Data frame

SCLK

SDATA

SCLK

SDATA 0

Buspark

ACK/NACK

Bus Park

1


For reference only

Response by slave

1549 1550

Figure 52 Register Write Command Sequence 1551

13.2.13 Register Read Command Sequence 1552

Figure 53 shows the Register Read Command Sequence. The Sequence starts with an SSC, followed by the 1553 read Command Frame, a one-clock cycle Bus Park Cycle and a Data Frame sent by the Slave device. The 1554 Command Sequence ends with another Bus Park Cycle. 1555



84

SA3 SA2 SA1 SA0 0 1 1 A4 A3 A2 A1 A0 P

P D7 D6 D5 D4 D3 D2 D1 D0 P 0

Register Read command frame

Data frame Bus park

Bus park

SSC

0

SCLK

SDATA

SCLK

SDATA



For reference only1556

1557

Figure 53 Register Read Command Sequence 1558

13.2.14 Register 0 Write Command Sequence 1559

Figure 54 shows the Register 0 Write Command Sequence. The Command Sequence starts with an SSC, 1560 followed by the Register 0 write Command Frame containing the Slave address, a logic one, and a 7-bit 1561 word to be written to Register 0. The Slave verifies receiving the correct data with ACK/NACK. The 1562 Command Sequence ends with a Bus Park Cycle. 1563

This Command Sequence is used to support advanced power management functions that require repetitive 1564 Command Sequences to a fixed Slave register with minimal bandwidth consumption. 1565

SA3 SA2 SA1 SA0 1 D6 D5 D4 D3 D2 D1 D0 P

Slave address DATA Parity

SCLK

SDATA 0

Buspark

ACK/NACK

Bus Park

1



Response by slave 1566 Figure 54 Register 0 Write Command Sequence 1567

13.3 Error Handling 1568

The SPMI protocol provides two means of error detection, parity check on each Frame and a check for 1569 invalid fields such as commands and addresses. The response of a device receiving either of these types of 1570



85

error depends on whether the device is a Master or a Slave, and the Frame in which the error occurs. The 1571 following sections describe the error condition and the response of each device type to the error. 1572

13.3.1 Parity Error in the Command Frame 1573

If a Master receives a Sequence with an incorrect parity value in the Command Frame, it shall ignore the 1574 Command Sequence, disconnect from the bus and try to reconnect to the bus. 1575

If a Slave receives a Command Sequence with an incorrect parity value in the Command Frame, it shall 1576 ignore the Command Sequence and reset its command decode logic on the next SSC. 1577

There is no means to detect multiple bit errors that alias onto known commands with the correct parity, 1578 except that the number of SCLK cycles might not match with the expected length. In this situation, a 1579 Master shall consider itself disconnected from the bus and shall connect to the bus to send a Sequence as 1580 defined in Section 9.2. If a Slave receives a different number of SCLK cycles than it expects for a given 1581 Command Frame, it shall reset its command decode logic on the next SSC. 1582

If a Parity Error occurs in the Command Frame sent by an RCS Device, the BOM shall stop the SCLK for 1583 > TBT. The RCS Device shall detect that the SCLK has stopped for TBT, shall reset itself and place its 1584 SDATA line in a High-Z state. 1585

13.3.2 Unsupported Commands 1586

If a Master receives a Command Sequence with an unsupported Command Frame, it shall ignore the 1587 command, disconnect from the bus and try to reconnect to the bus. 1588

If a Slave receives a Command Sequence with an unsupported Command Frame, it shall ignore the 1589 Command Sequence and reset its command decode logic on the next SSC. 1590

13.3.3 Parity Error in the Address Frame 1591

If a Master receives a Command Sequence with an incorrect parity value in an Address Frame, it shall 1592 ignore the Command Sequence. Since the length of the Command Sequence is known, the Master shall 1593 wait until the Command Sequence completes the requisite number of SCLK cycles before initiating a new 1594 arbitration request. The Master is not required to disconnect from the bus. If the Address Frame parity error 1595 occurs in a Write Command Sequence, the Master shall inform the writing Device of the error using 1596 ACK/NACK. 1597

If a Slave receives a Command Sequence with an incorrect parity value in the Address Frame, it shall 1598 ignore the Command Sequence. If the Address Frame parity error occurs in a Write Command Sequence, 1599 the Slave shall inform the writing Device of the error using ACK/NACK. 1600

13.3.4 Parity Error in the Data Frame 1601

If a Master receives a Command Sequence with an incorrect parity value in a Data Frame, it shall ignore 1602 the Command Sequence and use ACK/NACK to inform the writing Device of the error. Since the length of 1603 the Command Sequence is known, the Master shall wait until the Command Sequence completes the 1604 requisite number of SCLK cycles before initiating a new arbitration request. The Master is not required to 1605 disconnect from the bus. 1606

If a Slave receives a Command Sequence with an incorrect parity value in a Data Frame, the Slave shall 1607 ignore all Data Frames after encountering the first Parity Error. The Slave may ignore the entire Command 1608 Sequence if a single Data Frame contains a Parity Error. 1609



86

Address incrementing shall not be affected due to a Data Frame Parity Error for multi-byte write Command 1610 Sequences. 1611

13.3.5 Unsupported Address 1612

If a Master or Slave receives a read command with an unsupported address, the device shall send No 1613 Response Frames instead of Data Frames. 1614

If a Master or Slave receives a write command with an unsupported address, the device shall ignore the 1615 data in the unsupported addresses and inform the writing Device of the error using ACK/NACK. 1616



87

Annex A SPMI Reference (informative) 1617

A.1 DC Operating Conditions 1618

Table 17 SPMI DC Electrical Specifications 1619

Description Symbol Min Typ Max Unit

Number of Masters Nmaster 1 4

Number of Slaves Nslaves 0 16

Characterized Capacitive Bus Loading CLOAD 15 50 pF

Slave SDATA Pull Down Resistance RDS 0.5 2.0 MΩ

Slave SCLK Pull Down Resistance RCS 0.5 2.0 MΩ

Total System SDATA Pull Down Resistance RDT 0.125 2.0 MΩ

Total System SCLK Pull Down Resistance RCT 0.125 2.0 MΩ

Output Low Voltage VOL 0 0.2*VDD V

Output High Voltage VOH 0.8*VDD VDD V

Positive Going Threshold Voltage VTP 0.4*VDD 0.7*VDD V

Negative Going Threshold Voltage VTN 0.3*VDD 0.6*VDD V

Hysteresis Voltage (VTP - VTN) VH 0.1*VDD 0.4*VDD V

SPMI Supply Voltage 1.8 V signaling 1.2 V signaling

VDD 1.65 1.1

1.95 1.3

V V

A.2 AC Operating Conditions 1620

A.2.1 High Speed (HS) Device Class 1621

Table 18 SPMI HS Device AC Specifications 1622


SCLK Frequency (typical) FSCLK 0.032000 26 MHz

SCLK Period (1/FSCLK) TSCLK 38 32000 ns

SCLK Output High Time TSCLKOH 12 ns

SCLK Output Low Time TSCLKOL 12 ns

SCLK Output Transition Time (Rise / Fall) TSCLKOTR 2.1 5.3 ns

SDATA Output Transition Time (Rise / Fall) TSDATAOTR 2.1 5.3 ns

SDATA Output Valid Time TD 0 11 ns

SDATA Setup Time TS 1 ns

SDATA Hold Time TH 5 ns

SDATA Drive Release Time TSDATAZ 10 ns

Timing characterized as explained in Section 5.6. 1623



88

A.2.2 Low Speed (LS) Device Class 1624

Table 19 SPMI LS Device AC Specifications 1625


SCLK Frequency FSCLK 0. 032000 15 MHz

SCLK Period (1/FSCLK) TSCLK 66.67 31250 ns

SCLK Output High Time TSCLKOH 22 ns

SCLK Output Low Time TSCLKOL 22 ns

SCLK Output Transition Time (Rise / Fall) TSCLKOTR 2.1 8 ns

SDATA Output Transition Time (Rise / Fall) TSDATAOTR 2.1 8 ns

SDATA Output Valid Time TD 0 20 ns

SDATA Setup Time TS 2 ns

SDATA Hold Time TH 5 ns

SDATA Drive Release Time TSDATAZ 18 ns

Timing characterized as explained in Section 5.6. 1626

A.2.3 Other Signaling Electrical Specifications 1627

Table 20 defines SPMI Bus Timeout specification. 1628

Table 20 SPMI Bus Timeout Specification 1629


Bus Timeout Period TBT 96 μs



89

A.3 Command Sequence Reference (informative) 1630

M RCS NRCS Hex Description00 0 0 0 0

Y O O -0F 1 1 1 1

Y O O 10 Reset 0 0 0 1 0 0 0 0 P BP A/N BPY O O 11 Sleep 0 0 0 1 0 0 0 1 P BP A/N BPY O O 12 Shutdown 0 0 0 1 0 0 1 0 P BP A/N BPY O O 13 Wakeup 0 0 0 1 0 0 1 1 P BP A/N BPY O O 14 Authenticate 0 0 0 1 0 1 0 0 P P BP P BP BPY O N 15 Master Read 0 0 0 0 0 1 0 1 0 1 P P BP P BPY O N 16 Master Write 0 0 0 0 0 1 0 1 1 0 P P P BP A/N BP

17 (Reserved) 0 0 0 1 0 1 1 1 P18 (Reserved) 0 0 0 1 1 0 0 0 P19 (Reserved) 0 0 0 1 1 0 0 1 P

Y N N 1A Transfer Bus Ownership 0 0 0 0 0 0 0 1 1 0 1 0 P BP MP2 A* B* C* D* BP BP BP P BP

Y O N 1BDevice Descriptor Block

Master Read 0 0 0 0 0 1 1 0 1 1 P BP P P BP

Y O O 1CDevice Descriptor Block

Slave Read 0 0 0 1 1 1 0 0 P BP P P BP

1D (Reserved) 0 0 0 1 1 1 0 1 P1E (Reserved) 0 0 0 1 1 1 1 0 P1F (Reserved) 0 0 0 1 1 1 1 1 P20 0 0 0 0

Y O O -2F 1 1 1 130 0 0 0

Y O O -37 1 1 138 0 0 0

Y O O -3F 1 1 140 0 0 0 0 0

Y O O -5F 1 1 1 1 160 0 0 0 0 0

Y O O -7F 1 1 1 1 180 0 0 0 0 0 0 0

Y O O -FF 1 1 1 1 1 1 1

Address[7:0]Extended Register Write BC[3:0] BP

Command Frame

0

1 11 P

Information

P0

P

P

P

P

P

1 0 P Data[7:0]

0

Data[6:0]

BC[2:0]

BC[2:0]

0

Address[4:0]

Address[4:0]

00 1 1

Register 0 Write

SA[3:0]

SA[3:0]

SA[3:0]

SA[3:0]

SA[3:0]

SA[3:0]

MA[1:0]MA[1:0]

SA[3:0]

Register Write

Register Read

0Extended Register Read

Extended Register Write Long

SA[3:0]Extended Register Read

Long 0

0

1

A/N

0

0 0 0

10 P Address[7:0]BC[3:0]

1 BP Data[7:0]

Up to 16 Bytes of Data with Parity

BP

P

Address[7:0]

Address[7:0]

Address[15:8]

Address[15:8]

BP

P

1 BP

P

P

P

BP0 1

P Up to 16 Bytes of Data with Parity

Up to 8 Bytes of Data with Parity BPBP

Up to 8 Bytes of Data with Parity

Response Data 1 [7:0] Challenge/Response 2,3,&4

BP

BP

SA[3:0]

Undefined

Undefined

8 Bytes of Data + Parity

Undefined

Address[7:0] Data[7:0]Data[7:0]

SA[3:0]

Mandatory Commands

UndefinedUndefinedUndefined

Challenge Data 1 [7:0]Address[7:0]

SA[3:0]

SA[3:0]

MA[1:0]

SA[3:0]

Data 0 [7:0]

Data 9 [7:0] 8 Bytes of Data + Parity Data 1 [7:0]

Data 9 [7:0]

BP

A/N BP

Data Frame

A/N BP

A/N BP

SSC

1631 Figure 55 Command Sequence Formats 1632

Legend: BC = Byte Count BP = Bus Park Cycle M = Master A/N = ACK/NACK

MA = Master Address MPx = Master with Priority x N = Not supported

NRCS = Non-Request Capable Slave O = Optional P = Parity

RCS = Request Capable Slave SA = Slave Address Y = Mandatory

1633


Participants The following list includes those persons who participated in the Working Group that developed this Specification and who consented to appear on this list.

Atukula, Radha Krishna – Research in Motion

Limited Johnson, Robert C – IEEE-ISTO (staff)

Chun, Christopher – Qualcomm Incorporated Le Meur, Alice – Texas Instruments Incorporated

Hambro, Glen – IEEE-ISTO (staff) Pennanen, Juha – Texas Instruments Incorporated

note to implementersread.pudn.com/.../doc/comm/2918547/mipi_spmi_spec.pdf · an updated frequently...

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