new xtca developments at slac

26-Sep-11 1

New xTCA Developments at SLAC

CERN xTCA for Physics Interest Group Sept 26, 2011

Ray LarsenSLAC National Accelerator Laboratory

New xTCA Developments at SLAC - R. Larsen

26-Sep-11 2

Topics

• Standards developments• Applications Demonstration Program• Future Plans


26-Sep-11 3

Standards

• Hardware, Software working groups meet weekly/ needed

• 2 new HW standards approved– ATCA

• PICMG3.8 Standard IO interface to Rear Transition Module (RTM), IPMI extension & power connector

– MTCA• MTCA.4 Crate, 2-wide AMC & RTM, IO interface,

IPMI extension and power pins designated


26-Sep-11 4

Standard Extensions for Physics


26-Sep-11 5

Standards Details– ATCA PICMG3.8

• 120 5GHz BW IO channels on 3- 4x10 ZD connectors• New connector (Positronix) for IPM, power• Mechanical, E-keying functions• Implemented on SLAC MPP Processor (M. Huffer)

– MTCA.4• Extends double-wide shelf (crate) to include RTM• 60 Ch IO, IPMI on 2- 3x10 ZD connectors• Extended backplane timing, trigger, interlocks layer• Compatible with all existing 1-wide AMC products• Implemented by Schroff, ELMA, PT, others in dev’mt


26-Sep-11 66New xTCA Developments at SLAC - R. Larsen

PICMG3.8 RTM Interface StandardRear View

120 - IO Channels (3x40)IPMI, Power Connector (blue)2 Mechanical Keys Courtesy M. Huffer, SLAC

26-Sep-11 7

MTCA.4 AMC-RTM-Shelf Concept


text

FAN TRAY-HOTSWAP

FRONT END MODULE

ADVANCED MEZZANINE CARD (AMC)

INPUT/OUTPUT SIGNAL CONDITIONING

REAR TRANSITION MODULE (RTM)

I/O

I/O

BP CONN

BACKPLANE

AIR IN

AIR OUT

FAN TRAY-HOT SWAP

USE

R D

EFIN

ED I/

O C

ON

NEC

TOR

S


MTCA.4 12-AMC Backplane

Intlk, Vector Sums

Parallel Triggers


MTCA.4 Backplane Timing Distribution

Backplane

Enc.ClockTrigger

MCH

Enc.ClockTrigger

Cross-

Point-Switc

h

Interlock Interlock

AMCADC

AMCADC

AMCTiming

Central Timing

2 radial clocks per AMC,low jitter

8 bussed lines,M-LVDS for

Clocks, triggers, interlocks

Courtesy K. Rehlich, DESY


µRTM Extended IPMI Circuit

26-Sep-11 11Emerging New Electronics Standards - R. Larsen

MTCA.4 Prototype Shelves & Modules

26-Sep-11 12

MTCA.4 - 12 Slot Shelf Dual Star


12 Payload AMC-RTMs Dual Star Redundant Front View

Back-Plane

Dual PU slot

Dual MCH Slot

26-Sep-11 13

MTCA.4 - 6-Slot Shelf Non-Redundant


6 Slot Development Shelf1-Star Non- Redundant

Front View

6-Slot Rear View

Courtesy Schroff, Struck

26-Sep-11 14

SLAC Applications Demonstrations

1. LLRF for Main Linac S-Band 50MW station

2. Klystron interlocks for 10MW L-Band station

3. Beam Position Monitors for LCLSII Injector


26-Sep-11 15

1. S-Band LLRF

• Demonstrate intra-pulse feedback to achieve ~30fs phase control– Lower noise RF front end chassis– New solid state sub-booster– Feedback loop implemented in MTCA.4 using

Struck 10 Ch ADC 2 Ch DAC developed w/DESY– New LCLSI waveguide water-stabilized rack– Test on Standby triggering, switch to Accelerate

• Tests on accelerator to complete Oct 2011


26-Sep-11 16

LLRF MTCA & RF Chassis Testing


26-Sep-11 17

Rear View


26-Sep-11 18

RTM Inputs


Note – Preliminary RTM shownFinal RTMwith full IPMI complete, In test.

26-Sep-11 19

RF Chassis – Reference, LO, Sources, Downmixers


Note – Next stageplan is to test L-Band down-mixers, other RF modules inMTCA card format

26-Sep-11 20

AMC - 10/2Ch ADC/DAC 16bit 125 MSPS

Emerging New Electronics Standards - R. Larsen

Photo courtesy M. Kirsch,(Struck )

Initial Applications: LLRF DESY XFELLLRF SLAC Upgrade Proto

26-Sep-11 21

RTM 10 Ch ADC-DAC, IPMI Interface


Rear Panel

• Mini-Coax IF Signals In

• RF Ref In• Trigger in• Dual I&Q

DAC Out• IPMI

Extension to RF Chassis

Courtesy A. Young, SLAC

26-Sep-11 22

2. MTCA Klystron Interlocks S&L Band

• FPGA based interlocks in MTCA.4– S-Band interlocks currently in separate FPGA

non-modular chassis– L-Band interlocks currently FPGA based in VME– MTCA solution will serve both in future– SLAC designed RTM mates to new TEWS

Spartan 6 FPGA module (just received in US)– RTM testing starting– 1 board pair serves 8 Ch-60MSps, 16 Ch-2KSps– 2 board pairs serve 1 S- or L-band station


26-Sep-11 23

RTM FPGA Interlocks


Rear Panel

• Inputs- 8-60 MSps Ch- 16-2 KSps Ch- 12 bits Diff +/- 1V- Diode protection All channels• Outputs- Interlock Sums• RF Interlocks for L-Band 1 msec, S-band 1.5 µsec

Courtesy D.G. Brown, SLAC

26-Sep-11 24

AMC TAMC651 FPGA w/RTM


Courtesy TEWS

Note – Completion date for ESB installation Dec. 2011.

26-Sep-11 25

3. BPMs for LCSLII Injector

• Goal: Demonstration of 8 BPMs in 12-slot– RTM has 4 Ch analog plus calibration w/ strip-

line coupling between 120 Hz pulses– AMCs will be 4 Ch 125 or 250 MSps (125

available now; 250 may be developed by commercial supplier(s)

– 250 MSps needed if multibunch (2 bunches 8 nsec apart)

– Requirements being finalized (16 bit ADCs)– Preliminary RTM layout indicates feasible


26-Sep-11 26

BPM System Block Diagram


AFE

AFE

AFE

AFE

AFE

AFE

AFE

MCH

CPU

EVR

ADC

ADC

ADC

ADC

ADC

ADC

- Front -

12-slot MicroTCA crateInjector BPM Crate 1; 8 BPMs

- Back -

1 ADC per BPM

1 AFE per BPM

Signal cables to tunnel4 per BPM

Timing data

EPICSChannel Access Network

ADC

ADC

EVR

AFE

TrigFanout

TrigFanout

Calibrator trigger1 per BPM

ADC trigger1 per BPM

EVR provides clock to ADCs along the backplane

Courtesy S. Hoobler et al, private communication

26-Sep-11 27

Conclusions 1

• Standards for hardware have passed 2 major milestones– Committees will disband when SOWs complete– Software committee continues developing

guidelines for architecture and protocols– Member labs remain involved in PICMG through

Coordinating Committee for oversight, servicing tweaks

– Start new initiatives, SOWs, form committees as needed


26-Sep-11 28

Conclusions 2• SLAC new initiatives open future opportunities

– Main Linac RF upgrades for LCLSII, I.– BPM upgrades for LCLSII Injector, Main Linac– Interlock systems wholly contained in MTCA.4

combined RF-Controls package– Long range: Complete replacement CAMAC

controls in 2-mile accelerator, $20M program• Timeline:

– RF and interlock demos complete in Q1-2 FY12– BPM AIP completes Q2 FY13


new xtca developments at slac

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