new sis developments at uva - science website€¦ · 08-24-2016 alma workshop uva-uvml charles l....

08-24-2016 ALMA Workshop UVA-UVML

Charles L. Brown Department of Electrical & Computer Engineering

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Outline

!  Background: UVML, facilities, partnership !  SIS Materials/Technology !  UVA SIS Material & Fabrication Improvements

New SIS Developments at UVA



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Background: Arthur Lichtenberger

Education:

B.A. (Physics) Amherst College, 1980. Thesis: Superfluid Transitions in Thin Helium Films Ph.D. (Electrical Engineering) University of Virginia, 1987 Dissertation: SIS Nb Trilayer and NbCN Edge Junctions for Mixer Applications. Dissertation Advisor: Dr. Robert J Mattauch / Dr. Marc Feldman



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Background: Lichtenberger

Experience

Research Full Professor, 2008 – present Director, University of Virginia Microfabrication Laboratory 2003 – present Research Associate Professor, 1993 – 2008 Research Assistant Professor, 1987 – 1993 Technician Department of UMass Radio Astronomy, 1980-1981 To date, been PI or Co-PI on over 25 million dollars of funding and author on over 150 papers



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Long history of mm/submm collaboration between UVA and NRAO



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NRAO 200-300 GHz SIS mixer (UVA chips) & preamplifier ‘rockets’- each

an individual receiver with hemispherical top lens ��

�� Kitt Peak Telescope

Superconducting detectors



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Semiconductor Device Laboratory (SDL) Bob Mattauch, Director (60s)

Applied ElectroPhysics Laboratory (AEpL) Tom Crowe, Director (‘89) University of Virginia Microelectronics Laboratory (UVLM)

Arthur Lichtenberger (‘03)

- UVML currently has 20 associated faculty

!  ~10,000 ft2 …. 4,000 ft2 of class 10k cleanroom

!  Fully equipped for research on materials and devices

!  1 facility manager, 3 facility technicians

!  3 faculty mm-submm (Bobby Weikle, Scott Barker & myself)

!  UVML research ranges from superconducting materials & devices through electro-optical devices to microfluidics to spintronics, to interfaces/transport … etc

UVML - Background



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~ $3M UVML Equipment Dedicated to Superconducting Work

!  Four 3” magnetron gun (Nb, NbTi, Al, Au) up-sputter trilayer deposition tool with oxygen and nitridation load locks. Self designed/built

!  Four 3” magnetron gun (Nb, Ti, Cr, Au) confocal up-sputter deposition tool, iongun on fifth port, with loadlock. Self designed/built

!  Si monoxide thermal evaporator with off-axis deposition and four sample holders with rotation, iongun cleaning

!  AJA magnetron sputtering tool, confocal up-sputter with 5-gun room temperature stage chamber and 5-gun 900C heated stage chamber. Sputter etching configured electrodes, loadlock with ICP and sputter etching configuration.

!  Single 8” magnetron/diode sputtering tool (Nb and SiO2 targets) with sputter etching and rotation. Self designed/built



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UVA-CDL: Partnership of R & D

•  Joint SIS mixer research planning and realization of mixers, devices

•  Shared collaborations with NA research groups, such as AZ-ARO, UMass, ASU

•  From long standing collaboration: design rules “synch” with material/fabrication outcome

•  NRAO collaboration is particularly facilitated by physical proximity of UVA and CDL

Background



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• Trilayer Definition- clean, debris free

• Junction Insulation (wiring layer should not short to base electrode)

• as f ↑ Required junction size ↓

• as f ↑ Linewidths ↓

• as f ↑ Jc↑(and hence barrier thickness↓) requiring new high Jc barrier material

• as f ↑ chip and waveguide sizes ↓ and assembly more difficult

• as f ↑ SIS is frequency gap limited, so new larger gap materials are required

SIS Materials/Technology

Our mixers are based on SIS junctions (e.g. Nb/Al-oxide/NbMaterials & Fabrication Realities



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Very Low Leakage Currents Possible

UVA Nb/Al-Aloxide/Nb junction tested at 2K. World record low leakage current.



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With SIS technology, in collaboration with NRAO, HIA, AZ and IRAM, UVA has demonstrated Band3, Band6,

Band7 and Band8 SIS mixers that have met ALMA specifications



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Following are examples of recent UVA SIS material & fabrication improvements



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à sub micron junctions for higher bands

• as f ↑ Required junction size ↓



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Junction Pentalevel

Process

Thin hard top mask, thicker organic layer: high-res, multi resist stack for liftoff



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Junction process with size good

control to ~ 0.6um diameter



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Nb/Al-AlN/Nb/Au/nfr/poly/SiO2/Cr/imaging-resist

0.35 um

Junction Size



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The junction SiOx film/process is an extremely critical aspect. Below, UVA SiOx evaporation (left) versus SiO2 sputtering (right)



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à AlN Tunnel Barriers

as f ↑ Jc↑ (and hence barrier thickness ↓ )

…. Al-Aloxide barriers fail

requiring new high Jc barrier material for many applications

or Al-Aloxide not optimal for mixer design



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AlN Tunnel Barriers

Al-AlN Alternative Barrier Material

–  Enables higher Jc mixer designs –  Is grown from plasma nitridation of Al overlayer (not thermal growth) e.g., JPL: rf parallel plate grown



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•  Parallel plate method can introduce damage to barrier, thickness control •  AlN Plasma Nitridation by ICP - First Investigated by UVA

• Lower kinetic energy possible compared to parallel plate, ion gun •  Ion energy independent of ICP current density



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UVA Trilayer (tri-3) System ($200K in upgrades for AlN and NbTiN)



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Taken before modifications

- Decreasing oxidation with decreasing water partial pressure - At ~3x10-9 Torr, no oxidation observed with tool on our time scales

Tri3 Modifications



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•  What is the ICP reactive species/chemistry role on junction quality & growth rate

•  Relative Dissociation = N/N2 ratio of atomic/molecular signals

•  Also developed ellipsometer method to in situ monitor AlN growth –  RnA prediction within factor of ~1.5

Optical Spectrometry AlN growth Study



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•  Ocean Optics USB4000 in situ Spectrometer •  Collimating lens collects light emitted by ICP plasma

Optical Spectrometry



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Applying the algorithm to various condition gives good qualitative results




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AlN thickness at 30 s growth time for various RD. Growth rates are proportional to the density of the atomic N species.

Raw spectra (and repeated). N2 background counts ~ overlap. The density of the observed atomic N species is therefore proportional to RD for at least these four cases.




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Rsg/Rn of SIS junctions made across varying ICP conditions plotted against the relative dissociation of the ICP.

Normalized spectrum from the four ICP conditions used.




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•  Higher RD → higher growth rates

•  Higher RD → higher quality AlN films –  Increased Rsg/Rn by more than a factor of 2 –  Extrapolation for highest RD: Rsg/Rn ~30 (though very fast growth) –  Currently, higher Rsg/Rn values are traded off for RnA target values

" Atomic N plays a critical role in the formation of high quality AlN tunnel barriers.




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Typical I-V characteristics for RD = 0.08 vs RD = 0.20




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This is one of the current “fruits” from the ICP, trilayer system, optical spectroscopy, and junction SiO2 research and development.

385-500 GHz Prototype Mixer: (not RF tested yet)



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à UVA’s SOI architecture

as f ↑ chip and waveguide sizes ↓ … realization and

assembly of quartz chips becomes increasingly difficult

" quartz architecture problematic, especially for ALMA with many receivers, often with multi chips per receiver



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385-500 GHz mixer – UVA SOI Architecture

Realized the first ever AlN based mixers (ALMA Band 8 Freq 385-500 GHz) … on 3 um thin-Si substrates with Au beamleads



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SOI Improvements Our SOI uses a thermal SiO2 surface layer

! Requires backside SiO2 compensation layer ! Do not know the stress of the thermal SiO2! Compensate with sputtered SiO2

! Performed full backside stress compensation with four different �� thickness of sputtered SiO2 stress compensation. Evaluate



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SOI: UVA Ultra Thin Si with Beam Leads

No post processing, labor intensive, lapping and dicing required by the user…

Directional coupler & hybrid chips



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à Nb/Al-AlN/NbTiN

as f ↑ … new larger gap materials are required (SIS is

frequency gap limited depending on superconductors used)

NbTiN counter electrode with larger energy gap… or even all NbTiN SIS junctions



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Nb/Al-AlN/NbTiN (B8-B10) SIS Material Systems



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AlN barrier and NbTiN top electrode. Used Cl RIE for trilayer, Pentalevel junction processing, smallest junction is 0.24um2, good yield (~80%).



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à NbTiN/AlN/NbTiN

as f ↑ … new larger gap materials are required

NbTiN counter electrode with larger energy gap… or even all NbTiN SIS junctions (B10)

Al overlayer not compatible with NbTiN base electrode

direct deposit AlN barrier



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Reactive Bias Target Ion Beam Deposition (RBTIBD)

RBTIBD is a hybrid between ion beam and conventional magnetron sputter deposition that combines the best of each technique.

Use of RBTIBD with the direct sputtering of AlN tunnel barrier (NbTiN/AlN/NbTiN) in a radical departure from the standard Al overlayer approach.



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NbTiN deposited on Si/SiO2 in Tri-3 Smoothest film Roughness (RMS): 0.9 nm

NbTiN deposited on Si/SiO2 in LANS Smoothest film Roughness RMS): 0.4 nm

Different roughness & surface morphology of NbTiN films deposited in Tri-3 and RBTIBD



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•  Can be scribed into 4 sub-samples

•  Can isolate effects of

single process •  Also includes: –  Capacitors –  Tc elements

Prototyping Process Test Mask



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SiO2 insulation study: 93% yield (Pentalevel resist)



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Screening mixer chips for dc I-V curves and normal resistance is very time consuming- particularly for a

project like ALMA and an array receiver

Rapid SIS chip screening



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Current SIS device evaluation is realized by time consuming hand mounting of a few individual device chips onto a carrier chip for dip testing in a liquid helium dewar.

IV of thin-Si band-8 mixer tested by silver paint mounting and dip testing

Painfully Time

Consuming



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UVA Cryogenic Probe Station

• Investigate and optimize the thermal design, connections and heat management of our existing Lake Shore cryogenic probe station,

• Currently working with Lakeshore to realize improvements




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UVSCG’s Cryogenic Probe Station DC probing of individual (previously verified) SIS chips •  Superconducting properties (e.g. Nb gap) depend on temperature (90% at 5.5K) •  Platter temperature measured, reaches 4.2K •  SIS I-V curve at platter temperature of 4.2K gives actual I-V of ~ 7.5-8K •  Clearly the SIS chip temperature is significantly higher than the platter temperature



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UVA’s Cryogenic Probe Station –  UVA has recent success with designing on wafer probes

Low loss on-wafer measurements from 140GHz to 1.1 THz (room temp) –  Opens future work to redesign and realize improved DC cryogenic wafer

probes (in house)

Simulated thermal gradient map of DMPI's compact WR-5.1 cryogenic probe and waveguide. [1] Such a design and simulation can be adapted to DC.

Also possible to design probe cards in conjunction with NRAO mixer mask designs to facilitate probing.

[1] “Cryogenic temperature, 2-port, on-wafer characterization at WR-5.1 frequencies” publication IMS 2016

In collaboration with Lakeshore WR10 & WR5 cryo probes



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•  Nb/Al-AlN/Nb (B6, B7) AlN barrier •  Nb/Al-AlN/NbTiN (B8-B10) higher energy gap NbTiN & AlN barrier •  NbTiN/barrier/NbTiN (B10) benefit from higher energy gap all NbTiN

− Work with ALMA partners to develop designs − Adjust/adapt technology and fabrication methods − Fabricate prototype mixer wafers for RF evaluation

UVA is excellently positioned to collaborate with ALMA receiver groups for the next generation of ALMA SIS mixers

SIS Material Systems

SOI Architecture •  More accurate definition of chip size and registration to metallization •  No time intensive lapping-thinning/dicing required •  Close to drop in chip placement in waveguide block

•  Normal metal tuning elements (Band10) •  Rapid, whole wafer, dc cryogenic probing/screening of mixer chips •  Miscellaneous circuits (superconducting RF & IF Hybrids & LO Couplers

Miscellaneous

new sis developments at uva - science website€¦ · 08-24-2016 alma workshop uva-uvml charles l....

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