neural-network based analog-circuit fault diagnosis using wavelet transform as preprocessor

6
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000 151 REFERENCES [1] E. Hunt, Artificial Intelligence. New York: Academic, 1975. [2] P. Winston, Artificial Intelligence. Reading, MA: Addison-Wesley, 1977. [3] B. G. Batchelor, Pattern Recognition. New York: Plenum, 1978. [4] R. Gnanadesikan, Methods for Statistical Data Analysis of Multivariate Observations. New York: Wiley, 1977. [5] T. M. Cover and P. E. Hart, “Nearest neighbor pattern classification,” IEEE Trans. Inform. Theory, vol. IT-13, pp. 21–27, Jan 1967. [6] R. O. Duda and P. E. Hart, Pattern Classification and Scene Anal- ysis. New York: Wiley, 1973. [7] J. C. Bezdek, Pattern Recognition with Fuzzy Objective Function Algo- rithms. New York: Plenum, 1981. [8] J. M. Keller, M. R. Gray, and J. A. Givens Jr., “A fuzzy -nearest neighbor algorithm,” IEEE Trans. Syst., Man, Cybern., vol. SMC-15, pp. 580–585, July/Aug. 1985. [9] E. Seevinck, R. F. Wassenaar, and H. C. K. Wong, “A wide-band tech- nique for vector summation and rms-dc conversion,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 311–318, June 1984. [10] O. Landolt, E. Vittoz, and P. Heim, “CMOS selfbiased Euclidean dis- tance computing circuit with high dynamic range,” Electron. Lett., vol. 28, no. 4, pp. 352–354, Feb. 1992. [11] S. I. Liu and C. C. Chang, “A CMOS square-law vector summation cir- cuit,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 520–524, July 1996. [12] C. Y. Huang and B. D. Liu, “Current-mode multiple input maximum circuit for fuzzy logic controller,” Electron. Lett., vol. 30, no. 23, pp. 1924–1925, Nov. 1994. [13] C. Y. Huang, C. Y. Chen, and B. D. Liu, “Current-mode linguistic hedge circuit for adaptive fuzzy logic controllers,” Electron. Lett., vol. 31, no. 17, pp. 1517–1518, Aug. 1995. [14] C. Y. Chen, C. Y. Huang, and B. D. Liu, “Current-mode fuzzy linguistic hedge circuit—Contrast intensification,” in Proc. 1996 IEEE Int. Symp. Circuits and Systems, Atlanta, GA, May 1996, pp. 511–514. [15] C. Y. Chen, C. Y. Huang, B. D. Liu, and T. J. Su, “A current-mode fuzzy linguistic hedge circuit—More or less,” in Proc. 5th IEEE Int. Conf. Fuzzy Systems, New Orleans, LA, Sept. 1996, pp. 1080–1085. [16] C. Y. Chen, C. Y. Huang, J. Y. Tsao, and B. D. Liu, “A current-mode circuit for Euclidean distance calculation,” in Proc. 1997 Int. Symp. VLSI Technology, Syst.ems, and Applications, Taipei, Taiwan, June 1997, pp. 83–86. [17] C. Y. Chen, C. Y. Huang, and B. D. Liu, “Current-mode defuzzifier cir- cuit to realize the centroid strategy,” Proc. Inst. Elect. Eng.—Circuits Devices and Systems, vol. 144, no. 5, pp. 265–271, Oct. 1997. [18] C. Y. Huang, C. Y. Chen, and B. D. Liu, “Current-mode fuzzy linguistic hedge circuits,” Analog Integr. Circuits Signal Processing, vol. 19, no. 3, pp. 255–278, June 1999. [19] K. Bult and H. Wallinga, “A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 357–364, June 1987. [20] E. Seevinck and R. J. Wiegerink, “Generalized translinear circuit prin- ciple,” IEEE J. Solid-State Circuits, vol. SSC-26, pp. 1098–1102, Aug. 1991. [21] R. J. Wiegerink, Analysis and Synthesis of MOS Translinear Cir- cuits. Boston, MA: Kluwer, 1993. [22] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits. New York: McGraw-Hill, 1988, pp. 58–63. Neural-Network Based Analog-Circuit Fault Diagnosis Using Wavelet Transform as Preprocessor Mehran Aminian and Farzan Aminian Abstract—We have developed an analog-circuit fault diagnostic system based on backpropagation neural networks using wavelet decomposition, principal component analysis, and data normalization as preprocessors. The proposed system has the capability to detect and identify faulty com- ponents in an analog electronic circuit by analyzing its impulse response. Using wavelet decomposition to preprocess the impulse response drastically reduces the number of inputs to the neural network, simplifying its archi- tecture and minimizing its training and processing time. The second pre- processing by principal component analysis can further reduce the dimen- sionality of the input space and/or select input features that minimize diag- nostic errors. Input normalization removes large dynamic variances over one or more dimensions in input space, which tend to obscure the relevant data fed to the neural network. A comparison of our work with [1], which also employs backpropagation neural networks, reveals that our system re- quires a much smaller network and performs significantly better in fault diagnosis of analog circuits due to our proposed preprocessing techniques. Index Terms—Analog circuits, electronic circuits, fault diagnosis, neural networks, wavelet transform. I. INTRODUCTION Fault diagnosis in digital electronic circuits has been successfully de- veloped to the point of automation. However, the process of developing test strategies for analog circuits still relies heavily on the engineer’s experience and intuition. This requires the engineer to have some de- tailed knowledge of the circuit’s operational characteristics and expe- rience in developing test strategies. As a result, analog fault detection and identification is still an iterative and time-consuming process. The current state in electronic circuit manufacturing has introduced analog and analog/digital hybrid circuits, where the total circuit under test is large. As a result, there is an urgent need to find a systematic approach to automate the fault diagnostic process in these circuits where intu- ition and experience may no longer be sufficient [2], [3]. The engineering community began to look into analog test problems in the mid 1970’s, since analog systems were among the most unreli- able and least testable systems. As a result, many works appeared in the literature and analog fault diagnosis became an active area of re- search. During the past few years, there has been significant research on analog fault diagnosis at the system, board, and chip level [1], [3]–[5]. A survey of the research conducted in this area clearly indicates that analog fault diagnosis is complicated due to the poor fault models, com- ponent tolerances, and nonlinearity issues. These difficulties make the application of neural networks to these problems very appealing. In this approach, all the faults are modeled by a unique set of features (signatures) that the network learns during the training phase. These features, together with the associated fault classes, are presented to the network as input–output pairs. The network is then allowed to adjust its weight and bias parameters to learn the desired input–output rela- tionship. Next, the network is presented with a set of features as input during the testing phase and determines the fault class. This is called generalization, where the network predicts the fault class based on the knowledge acquired during the training phase. Fault diagnosis based on Manuscript received December 1998; revised September 1999. This paper was recommended by Associate Editor P. Thiran. M. Aminian is with St. Mary’s University, San Antonio, TX 78228 USA. F. Aminian is with Trinity University, San Antonio, TX 78212 USA. Publisher Item Identifier S 1057-7130(00)01464-6. 1057-7130/00$10.00 © 2000 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000 151

REFERENCES

[1] E. Hunt,Artificial Intelligence. New York: Academic, 1975.[2] P. Winston,Artificial Intelligence. Reading, MA: Addison-Wesley,

1977.[3] B. G. Batchelor,Pattern Recognition. New York: Plenum, 1978.[4] R. Gnanadesikan,Methods for Statistical Data Analysis of Multivariate

Observations. New York: Wiley, 1977.[5] T. M. Cover and P. E. Hart, “Nearest neighbor pattern classification,”

IEEE Trans. Inform. Theory, vol. IT-13, pp. 21–27, Jan 1967.[6] R. O. Duda and P. E. Hart,Pattern Classification and Scene Anal-

ysis. New York: Wiley, 1973.[7] J. C. Bezdek,Pattern Recognition with Fuzzy Objective Function Algo-

rithms. New York: Plenum, 1981.[8] J. M. Keller, M. R. Gray, and J. A. Givens Jr., “A fuzzy -nearest

neighbor algorithm,”IEEE Trans. Syst., Man, Cybern., vol. SMC-15,pp. 580–585, July/Aug. 1985.

[9] E. Seevinck, R. F. Wassenaar, and H. C. K. Wong, “A wide-band tech-nique for vector summation and rms-dc conversion,”IEEE J. Solid-StateCircuits, vol. SC-19, pp. 311–318, June 1984.

[10] O. Landolt, E. Vittoz, and P. Heim, “CMOS selfbiased Euclidean dis-tance computing circuit with high dynamic range,”Electron. Lett., vol.28, no. 4, pp. 352–354, Feb. 1992.

[11] S. I. Liu and C. C. Chang, “A CMOS square-law vector summation cir-cuit,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 520–524, July 1996.

[12] C. Y. Huang and B. D. Liu, “Current-mode multiple input maximumcircuit for fuzzy logic controller,”Electron. Lett., vol. 30, no. 23, pp.1924–1925, Nov. 1994.

[13] C. Y. Huang, C. Y. Chen, and B. D. Liu, “Current-mode linguistic hedgecircuit for adaptive fuzzy logic controllers,”Electron. Lett., vol. 31, no.17, pp. 1517–1518, Aug. 1995.

[14] C. Y. Chen, C. Y. Huang, and B. D. Liu, “Current-mode fuzzy linguistichedge circuit—Contrast intensification,” inProc. 1996 IEEE Int. Symp.Circuits and Systems, Atlanta, GA, May 1996, pp. 511–514.

[15] C. Y. Chen, C. Y. Huang, B. D. Liu, and T. J. Su, “A current-mode fuzzylinguistic hedge circuit—More or less,” inProc. 5th IEEE Int. Conf.Fuzzy Systems, New Orleans, LA, Sept. 1996, pp. 1080–1085.

[16] C. Y. Chen, C. Y. Huang, J. Y. Tsao, and B. D. Liu, “A current-modecircuit for Euclidean distance calculation,” inProc. 1997 Int. Symp. VLSITechnology, Syst.ems, and Applications, Taipei, Taiwan, June 1997, pp.83–86.

[17] C. Y. Chen, C. Y. Huang, and B. D. Liu, “Current-mode defuzzifier cir-cuit to realize the centroid strategy,”Proc. Inst. Elect. Eng.—CircuitsDevices and Systems, vol. 144, no. 5, pp. 265–271, Oct. 1997.

[18] C. Y. Huang, C. Y. Chen, and B. D. Liu, “Current-mode fuzzy linguistichedge circuits,”Analog Integr. Circuits Signal Processing, vol. 19, no.3, pp. 255–278, June 1999.

[19] K. Bult and H. Wallinga, “A class of analog CMOS circuits based onthe square-law characteristic of an MOS transistor in saturation,”IEEEJ. Solid-State Circuits, vol. SC-22, pp. 357–364, June 1987.

[20] E. Seevinck and R. J. Wiegerink, “Generalized translinear circuit prin-ciple,” IEEE J. Solid-State Circuits, vol. SSC-26, pp. 1098–1102, Aug.1991.

[21] R. J. Wiegerink,Analysis and Synthesis of MOS Translinear Cir-cuits. Boston, MA: Kluwer, 1993.

[22] S. Franco,Design with Operational Amplifiers and Analog IntegratedCircuits. New York: McGraw-Hill, 1988, pp. 58–63.

Neural-Network Based Analog-Circuit Fault DiagnosisUsing Wavelet Transform as Preprocessor

Mehran Aminian and Farzan Aminian

Abstract—We have developed an analog-circuit fault diagnostic systembased on backpropagation neural networks using wavelet decomposition,principal component analysis, and data normalization as preprocessors.The proposed system has the capability to detect and identify faulty com-ponents in an analog electronic circuit by analyzing its impulse response.Using wavelet decomposition to preprocess the impulse response drasticallyreduces the number of inputs to the neural network, simplifying its archi-tecture and minimizing its training and processing time. The second pre-processing by principal component analysis can further reduce the dimen-sionality of the input space and/or select input features that minimize diag-nostic errors. Input normalization removes large dynamic variances overone or more dimensions in input space, which tend to obscure the relevantdata fed to the neural network. A comparison of our work with [1], whichalso employs backpropagation neural networks, reveals that our system re-quires a much smaller network and performs significantly better in faultdiagnosis of analog circuits due to our proposed preprocessing techniques.

Index Terms—Analog circuits, electronic circuits, fault diagnosis, neuralnetworks, wavelet transform.

I. INTRODUCTION

Fault diagnosis in digital electronic circuits has been successfully de-veloped to the point of automation. However, the process of developingtest strategies for analog circuits still relies heavily on the engineer’sexperience and intuition. This requires the engineer to have some de-tailed knowledge of the circuit’s operational characteristics and expe-rience in developing test strategies. As a result, analog fault detectionand identification is still an iterative and time-consuming process. Thecurrent state in electronic circuit manufacturing has introduced analogand analog/digital hybrid circuits, where the total circuit under test islarge. As a result, there is an urgent need to find a systematic approachto automate the fault diagnostic process in these circuits where intu-ition and experience may no longer be sufficient [2], [3].

The engineering community began to look into analog test problemsin the mid 1970’s, since analog systems were among the most unreli-able and least testable systems. As a result, many works appeared inthe literature and analog fault diagnosis became an active area of re-search. During the past few years, there has been significant research onanalog fault diagnosis at the system, board, and chip level [1], [3]–[5].A survey of the research conducted in this area clearly indicates thatanalog fault diagnosis is complicated due to the poor fault models, com-ponent tolerances, and nonlinearity issues. These difficulties make theapplication of neural networks to these problems very appealing. Inthis approach, all the faults are modeled by a unique set of features(signatures) that the network learns during the training phase. Thesefeatures, together with the associated fault classes, are presented to thenetwork as input–output pairs. The network is then allowed to adjustits weight and bias parameters to learn the desired input–output rela-tionship. Next, the network is presented with a set of features as inputduring the testing phase and determines the fault class. This is calledgeneralization, where the network predicts the fault class based on theknowledge acquired during the training phase. Fault diagnosis based on

Manuscript received December 1998; revised September 1999. This paperwas recommended by Associate Editor P. Thiran.

M. Aminian is with St. Mary’s University, San Antonio, TX 78228 USA.F. Aminian is with Trinity University, San Antonio, TX 78212 USA.Publisher Item Identifier S 1057-7130(00)01464-6.

1057-7130/00$10.00 © 2000 IEEE

152 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000

neural networks bypasses the difficulties associated with analog faultdiagnosis described earlier, since no physical models of the faults ortolerance problems are required. Instead, the faulty circuit is simulatedor built and the appropriate features associated with the fault under con-sideration are extracted from the circuit’s output(s).

There are three recent works that discuss applications of neural net-works to analog fault diagnosis [1], [2], [6]. Among these, [2] is avery introductory work that mainly discusses the potential of neuralnetworks in analog system test development. Reference [1] appliesneural networks to fault diagnosis of linear circuits without any prepro-cessing of the circuit’s impulse response. This can lead to large neuralnetwork architectures even for relatively small circuits. For a largercircuit, the authors attempt two ambiguity groups to keep the clas-sification problem and neural network size manageable. In this case,each ambiguity group is assumed to be the collection of seven to eightfaulty components. Even though faults can be indistinguishable if theycreate similar outputs, it is possible to further break down the ambi-guity groups in this reference through appropriate preprocessing of thecircuit’s output(s) as shown later. The work in [6] also does not involvepreprocessing to reduce the number of input features to a manageablesize. Feature selection is performed in frequency domain and involvesa significant number of features, even for a small circuit. Moreover, theselection process in the authors’ approach requires significant experi-ence and intuition about circuit’s operational characteristics.

Neural-network based fault diagnosis is applicable to analog circuitsas long as the faults under consideration result in classes which can beseparated from each other and the no-fault class by means of appro-priate features. Within the context of this work, appropriate featuresrefer to the impulse response of the electronic circuit preprocessed bywavelet decomposition, principal component analysis (PCA), and nor-malization. We will show later that through these preprocessing steps,we can significantly reduce the number of inputs and select appro-priate features such that the neural network architecture required forfault diagnosis has a minimal size. In this work, we will concentrateon faults resulting from components having values out of the range al-lowed by component tolerances so that we can compare our results with[1]. However, our proposed system is capable of identifying any faultin any analog circuit which can be represented by a unique signature.Comparison of our work with [1] in a later section clearly indicatesthe importance of preprocessing the output of an analog circuit in: 1)significantly reducing the size and, therefore, the training time of theneural network and 2) improving the performance of the neural net-work in fault diagnosis.

The material in this brief is arranged in the following order. In Sec-tions II and III, we briefly review our proposed preprocessing tech-niques for analog-circuit fault diagnosis and cover the sample circuitsand faults considered in this work. Section IV discusses the selection ofwavelet coefficients as features to train and test the neural network, andSection V covers the results. We will present our conclusion in SectionVI.

II. PROCESSING OFNEURAL NETWORK INPUTS

A. Wavelet Transform as a Preprocessor

Discrete (dyatic) wavelet analysis refers to the decompositionof a signal into the so-called approximations and details. This isaccomplished using shifted and scaled versions of the so-calledoriginal (mother) wavelet as

a;b (x) =1pa

x� b

a: (1)

Fig. 1. Hierarchial decomposition of a signal into approximations and details.Note that each approximation or detail component is further decomposed into itsown approximation and detail levels. Here, only two levels of decompositionsare shown. Also shown is the downsampling effect in wavelet analysis.

In this equation,a andb define the degree of scaling and shifting ofthe mother wavelet (x) ; respectively. The coefficients of expansionC(a; b) for a particular signal can be expressed as

C (a; b) = h a;b (x)

I(x)i = 1pa

I(x) x� b

adx: (2)

These coefficients give a measure of how closely correlated the mod-ified mother wavelet [in (1)] is with the input signal. In (2),I(x) rep-resents the signal and the integration is performed over all possiblex

values. Wavelet analysis in its discrete (dyatic) form assumesa = 2j

andb = k2j = ka; where(j; k) 2 Z2: Approximations and detailsmentioned earlier correspond to high-scale (low-frequency) and low-scale (high-frequency) components of a signal, respectively. Therefore,wavelet decomposition can be considered a process that generates afamily of hierarchically organized low- and high-frequency compo-nents of a signal. At each level, sayj; one can construct the approx-imationAj and detailDj of the original signal. The block diagram ofthis decomposition is shown in Fig. 1. One can, therefore, consider ap-proximation and detail as low- and high-pass filter operations on theoriginal signal, respectively.

In applying wavelet analysis to sampled signals, one needs to per-form the downsampling operation after each level of decomposition topreserve the number of data points in the original signal. This simplymeans to include every other data point in the signal components (ap-proximation and detail). Consequently, the number of data points inthe components at levelj approximation or detail will be reduced by afactor of two compared to the corresponding number of data points atlevel (j � 1): This can be effectively used to extract optimal featuresfor neural network training as explained later. The process of down-sampling is also shown in Fig. 1.

Several families of wavelets are proven to be useful in signal andimage processing. These families include Haar, Daubechies, Biorthog-onal, Coiflets, Symlets, Morlet, Mexican Hat, Meyer, etc. Each of thesewavelets have properties that make them suitable for certain applica-tions [7]. For example, the wavelet Biorthogonal 3.7, which belongsto Biorthogonal family of wavelets, is popular in image processing,and the Mexican Hat wavelet has been applied to rotation-invariantpattern recognition [8]. The proper choice of the mother wavelet forpreprocessing the analog circuit’s output(s) is crucial for optimal de-sign of the fault diagnostic system. In this work, we have used the firstmember of Daubechies family of wavelets, also known as Haar, shownin Fig. 2 for the circuits under test. This choice was made after sev-eral wavelet functions were examined as possible candidates for themother wavelet. After analyzing the wavelet coefficients generated bythese wavelet functions, it was determined that Haar gave the most dis-tinct features (wavelet coefficients) across fault classes, thus providing

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000 153

Fig. 2. The mother wavelet used in our study. This is the first member of theDaubechies family of wavelets, also known as Haar.

optimal features for neural network training. This issue is discussedfurther in Section IV.

As mentioned before, the main advantage of using wavelet transformis to reduce the number of inputs to the neural network. This is accom-plished by the downsampling operation performed in wavelet analysis,which causes the number of wavelet coefficients to be reduced by afactor of two at each level of approximation or detail. Since this de-composition is hierarchically organized, we can search for an appro-priate collection of these coefficients that remain distinct across faultclasses. The selected coefficients are further preprocessed by PCA andnormalization to prepare the inputs to the neural network. The coeffi-cient selection process will be discussed later in Section IV.

B. PCA and Data Normalization

Principal component analysis is a preprocessing technique which cansignificantly reduce the complexity of the neural networks employedin fault classification problems. PCA achieves this goal by further re-ducing the dimensionality of the input space after wavelet analysiswhile preserving as much of the relevant information as possible forfault classification. In cases where input space is not high-dimensional,PCA can still be a very useful preprocessing technique for selecting op-timal features that minimize classification errors. In summary, the aimof PCA is to map vectorsx in ad-dimensional input space(x1; � � � ; xd)onto vectorsz in anM -dimensional space(z1; � � � ; zM) in such a waythat loss of essential information and data variation needed for classifi-cation is minimized while keepingM < d: To apply PCA to a typicalinput space vectorx; we first writex as a linear combination of a setof d orthonormal vectorsui in the form

x =

d

i=1

ziui (3)

wherezi = uT

i x: Next, we retain only a subsetM < d of the basisvectorsui and their associatedzi values to form

x0 =

M

i=1

ziui +

d

i=M+1

biui (4)

wherex0 is the approximation tox: In (4), the remaining coefficientszi for i � M + 1 are replaced by constantsbi: Minimizing

EM = 1

2

N

n=1

kxn � xnk2 (5)

which is the sum of the squares of the errors over the whole data set(n = 1; N); gives the vectorz with componentszi(i = 1;M); whichapproximatex in theM -dimensional input space. In practice,M isdetermined by principal component analysis such that a pre-specifiedpercentage of the total variation in the data set is preserved.

The third preprocessing stage is data normalization which followsPCA for the purpose of enhancing the features in a data set. Data nor-malization is a linear scaling of the input features to avoid large dy-namic ranges in one or more dimensions. There are many applications

Fig. 3. A 25-kHz Sallen-Key bandpass filter used in our study.

in which two or more input features may differ by several orders ofmagnitude. These large variations in feature sizes can dominate moreimportant but smaller trends in the data and should be removed throughnormalization. Our studies have shown that normalizing feature vec-tors selected by PCA to have zero mean and unit standard deviationcan make the neural network training phase much more efficient.

The neural network selected for this study is a multilayer feedfor-ward neural network trained by backpropagation [9]. Our work showsthat through preprocessing of the output signals from an analog circuit,we can select an optimal number of features (inputs) for the neuralnetwork. This consequently minimizes the size of the neural network,reducing its training time and improving its performance. The waveletcoefficients not selected as features to train the neural network are dis-carded since they are irrelevant to distinguishing among fault classes.

III. SAMPLE CIRCUITS AND FAULTS

The two circuits studied in our work are the same as those in [1] andare shown in Figs. 3 and 5. The first circuit is the Sallen-Key band-pass filter [10]. The nominal values for the components which resultin a center frequency of 25 kHz are shown in the figure. The resistorsand capacitors are assumed to have tolerances of 5% and 10%, respec-tively1. The primary motivation for selecting this filter and its associ-ated faults described later in this section is to compare our results withthose in [1]. The same circuit and faults are considered in this referencewith the impulse response sampled and fed directly to a neural networkwithout any preprocessing. Comparison of the two case studies provesthe importance of preprocessing in neural network based diagnosticsystems which leads to neural networks having simpler architecturesand improved performance.

The impulse response of the circuit in Fig. 3, withR3; C2; R2; andC1 varying within their tolerances, belong to the no-fault class (NF)and are fed to the preprocessors for feature selection. When any of thefour components is higher or lower than its nominal value by 50% withthe other three components varying within their tolerances, we obtainfaulty impulse responses. These faulty impulse responses are similarlyfed to the preprocessors for feature selection and form the fault classesR3 *; R3 +; C2 *; C2 +; R2 *; R2 +; C1 *; andC1 +;where* and+ stand for high and low, respectively. For instance,R3 * fault classcorresponds toR3 = 3k; withC2; R2; andC1 allowed to vary withintheir tolerances. This procedure allows us to generate training and testpatterns at the output of the preprocessors for training and testing theneural network. The impulse response of the filter can be very wellapproximated by the output generated from a narrow pulse whose widthT is much smaller than the inverse of the filter’s bandwidth. For all ourSPICE simulations, we have taken the filter input to be a single pulseof height 5 V and duration of 10µs. Our simulation results indicate

1The robustness of the neural network based fault diagnostic system to thetolerance of nonfaulty components is automatically verified during a successfultraining phase. This phase requires the neural network to place output voltagescorresponding to the given tolerance ranges in the same fault class and achievea prespecified error goal.

154 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000

Fig. 4. Linear plot (value versus index) of the first element of levels 1–5 approximation coefficients for the circuit shown in Fig. 3. Fault classes ineach plot arein the order 1 1 2 2 2 2 3 and 3 and are separated from each other by vertical lines. Within a fault class,50 typical values are shown.

that the output generated by such a pulse is very adequate to classifyall faults considered here.

The second circuit studied in our work and [1] is more complicatedand is shown in Fig. 5. This is a two-stage four-op-amp biquad low-passfilter [10]. The work in [1] uses two ambiguity groups of seven andeight faulty components. The first group containsC1 *; C3 *; C4 *;R16 *; R19 *; R21 +; andR22 *; and the second group consistsof C2 *; R17 +; R3 *; R4 +; R6 *; R7 +; R8 *; andR9 *.The faulty component values used in our work and [1] are shown inTable I where* and+ imply significantly higher and lower than nom-inal values. These two ambiguity groups are defined in [1] based onthe degree of similarity between circuit outputs belonging to differentfault classes. The measure used in this reference to obtain the degreeof similarity is theK1 criterion defined by

K1 =Rxy

Rxx +Ryy �Rxy

(6)

where

Rxx =1

T

T

0

x(t)x(t) dt (7)

and

Rxy =1

T

T

0

x(t)y(t) dt: (8)

In this equation,x(t) andy(t) are the signals whose correlation isunder investigation andT is the period. If this measure indicates highcorrelation between outputs, the associated faults are placed in the sameambiguity group. Through our proposed preprocessing techniques, weshow that it is possible to select an optimal number of features thatleads to successful classification of individual faults presented in TableI except for one ambiguity group containingR6 *; R7 +; andR9 * :

The reason these faults belong to the same ambiguity group is becausethey produce very similar outputs, as discussed in Section V.

IV. WAVELET COEFFICIENT(FEATURE) SELECTION

As indicated before, we have used Haar wavelet function in this worksince it gives the most distinct features across fault classes. This be-comes clear during the training phase, when the network must meeta reasonable error goal to warrant good generalization. Among manywavelets we examined, only Haar function achieved our prespecifiedmean-square error goal of 0.01. The wavelet properties that can pro-vide insight into the appropriateness of this function are support andregularity. Support is a measure of the duration of a wavelet in timedomain and regularity is related to its ability to correlate to smoothfunctions [11]. Since Haar function has a compact support and a regu-larity of zero because of its discontinuous nature, it is very well suitedto extract features from signals characterized by short durations andswift variations. When an input pulse is applied to our circuits, it is thelocalized behavior of the output signal at its onset that carries the dis-tinct features required to classify faults. This localized behavior of theoutput signal at its rupture characterized by short duration then makesHaar wavelet appropriate for this application.2 The general guidelinesfor selecting wavelet coefficients as features to train the neural networkare as follows:

1) Depending on the nature of the signal, one needs to go up tosufficiently high levels of approximation and detail to expose thelow- and high-frequency features of the signal, respectively. Onecan then use principal component analysis to further reduce the

2To demonstrate the significance of the localized behavior of the outputs inthis application, we have examined these signals, which typically last 1 ms. Ex-tracting features from the first 0.2 ms of the output signals is sufficient to trainthe neural network and achieve a mean square error goal of 0.01. Training theneural network on features extracted from the last 0.8 ms of the output signalsleads to a mean square error which is several order of magnitudes higher. Thisproves that the onset of the output signal has the necessary information to dis-tinguish among fault classes which is best analyzed by the Haar function.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000 155

Fig. 5. The two-stage four-op-amp biquad low-pass filter used in our study. All resistors are in ohms.

number of features and/or enhance their distinctiveness acrossfault classes.

2) The approximation and detail coefficients reflect the low- andhigh-frequency contents of a signal, respectively. The low-fre-quency contents usually give a signal its basic structure, whilethe high-frequency contents provide its details. As a result, themain features of a signal are usually captured in the approxima-tion coefficients.

Using these guidelines, we have selected the first coefficient of approx-imation levels 1–5, associated with the impulse response of the filters asour features. Training the neural network on these features meets ourprespecified error goal of 0.01, implying that they are distinct acrossfault classes. It is possible to demonstrate graphically the role thesefeatures play in distinguishing among fault classes. Consider the NFand eight faulty classes associated with the sample circuit in Fig. 3.For each of the nine classes, 50 impulse responses are generated byvarying components within their tolerances as described in Section III.The selected approximation coefficients associated with these impulseresponses are shown in Fig. 4. In this figure, each plot corresponds toa single coefficient with thex-axis ranging from 1 to 450 to cover nineintervals of size 50, separated by vertical lines, corresponding to eachclass. Fault classes in each plot are presented in the orderC1 *; C1 +;C2 *; C2 +; NF; R2 *; R2 +; R3 *; andR3 + : We can examineFig. 4 to determine how fault classes are distinguished by features. Forinstance, feature 1 can separateNF; R3 *; andR3 +; or NF andR2 * can be distinguished by features 2 or 3. The effectiveness ofthese five features to classify the faults associated with the sample cir-cuits will be discussed in the next section. It is important to note thatfeature selection is a critical and intricate task in analog fault diagnosisor any other neural network based system. However, this task needs tobe carried out only once in a given application.

V. RESULTS

In this section, we compare the size and performance of our neuralnetworks with [1] to show the significance of the proposed prepro-cessing techniques. To perform a diagnosis of the faults described inSection III for the Sallen-Key bandpass filter, the work presented in [1]requires a three-layer backpropagation neural network. This network

has 49 inputs, 10 first-layer, and 10 second-layer neurons, resulting ina total adjustable parameters of about 700. During the training phase,an error function of these parameters must be minimized to obtain theoptimal weight and bias values. Their trained network was able to prop-erly classify 95% of the test patterns. Our backpropagation neural net-work has two layers with 5 inputs, 7 neurons in layer 1, and 1 neuronin the output layer. The total number of adjustable parameters in ournetwork is about 45, with the reduction in the number of weights andbiases directly translating to shorter training time and better perfor-mance. Our trained network is capable of 100% correct classificationof our test data.

The real advantage of preprocessing becomes evident when appliedto the more complex low-pass filter shown in Fig. 4. As mentioned be-fore, the work in [1] assigns all faults to one of two ambiguity groups.The size of the neural network is not specified in their work and theyachieve a 100% correct classification of the test data as belonging toone of the two ambiguity groups. We have successfully classified all thefaults in Table I except three,(R6 *; R7 +; R9 *);which are placed inone ambiguity group. The backpropagation neural network trained forthis problem has 5 inputs, 20 neurons in hidden layer 1, and 1 neuronin the output layer. This neural network correctly classifies 99.3% ofthe test data. Due to the effective preprocessing of the low-pass filter’soutput, the neural network architecture used for this complicated cir-cuit is very simple, implying fast and efficient training and superiorperformance.3 As mentioned before, the reason forR6 *; R7 +; andR9 * belonging to the same ambiguity group is that they create verysimilar outputs. This is evident from an analysis of the low-pass filter,which gives

dvo1

dt=

R7

R6R9C2

v1: (9)

For these three fault classes, the expression (9) remains relatively un-changed for the faulty component values shown in Table I. As a result,

3It is important to note that the work in [1] is a black-box approach to fault di-agnosis and does not analyze the circuit characteristics, except for some simplesignal similarity metric. This is intended to move the test/diagnosis objectiveclose to the goal of a built-in self-test module. However, in light of the advan-tages of the proposed preprocessing techniques, it is beneficial to add a prepro-cessing unit to this module.

156 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 2, FEBRUARY 2000

TABLE IFAULT CLASSES USED FOR THE TWO-STAGE

FOUR-OP-AMP BIQUAD CIRCUIT. THE NOMINAL AND FAULTY

VALUES ARE ALSO SPECIFIED

these three faults must be placed in the same ambiguity group if the cir-cuit output is the only measure to determine fault classes. Training theneural network on more than one node voltage or using testability anal-ysis as a preprocessor [12] can further resolve the ambiguity groups.For instance, if the training data for the lowpass filter includes featuresassociated with thev2 node voltage, our neural network can classifyR9 * fault correctly and the ambiguity group reduces toR6 * andR7 + : Our results clearly indicate that through appropriate prepro-cessing of an analog circuit output, one can train a neural network tocorrectly diagnose all faults unless the circuit’s outputs are similar forsome fault classes.

VI. CONCLUSION

We have applied backpropagation neural networks with wavelet de-composition, PCA, and data normalization as preprocessors to fault di-agnosis of analog circuits. Our study indicates that the proposed pre-processing techniques have a significant impact on analog fault diag-nosis due to the selection of an optimal number of relevant features.This leads to neural network architectures with minimal size that canbe trained efficiently and carry out fault diagnosis with a high degreeof accuracy. For complex analog circuits, our approach leads to neuralnetworks that can identify individual faulty components unless thesefaults give similar circuit outputs. In such a case, the neural network canidentify the ambiguity group containing the fault classes with similaroutputs. Further resolution of ambiguity groups is possible by additionof features from more node voltages to train the neural network. Sinceour analog fault-diagnostic system is based on neural networks, its per-formance depends on how well the selected features can distinguishamong fault classes. As a result, choosing proper wavelet function andwavelet coefficients is critical to the system performance. Since onecan not make these choices with absolute certaintya priori, any ad-ditional analysis to ensure the distinctiveness of the selected featuresacross fault classes is beneficial [13]. The test that will eventually deter-mine the appropriateness of the selected wavelet function and featuresis the training phase which must meet a reasonable error goal leadingto a satisfactory performance of the neural network.

REFERENCES

[1] R. Spina and S. Upadhyaya, “Linear circuit fault diagnosis using neuro-morphic analyzers,”IEEE Trans. Circuits Syst. II, vol. 44, pp. 188–196,1997.

[2] H. Spence, “Automatic analog fault simulation,” inProc. AU-TOTESTCON’96 Conf., pp. 17–22.

[3] R.-W. Liu, Testing and Diagnosis of Analog Circuits and Sys-tems. New York: Van Nostrand, 1991.

[4] Selected Papers on Analog Fault Diagnosis. New York: IEEE Press,1987.

[5] J. W. Bandler and A. Salama, “Fault diagnosis of analog circuits,” inProc. IEEE, 1985, pp. 1279–1325.

[6] M. Catelani and M. Gori, “On the application of neural networks tofault diagnosis of electronic analog circuits,”Measurement, vol. 17, pp.73–80, 1996.

[7] G. Strang and T. Nguyen,Wavelet and Filter Banks. Cambridge, MA:Wellesley-Cambridge Press, 1996.

[8] H. W. Lee, Wavelet Gri-Minace Filter for Rotation-Invariant PatternRecognition. Philadelphia, PA: SPIE, 1994, vol. 2762, pp. 343–352.

[9] M. H. Hassoun, Fundamentals of Artificial NeuralNetworks. Cambridge, MA: MIT Press, 1995.

[10] M. V. Valkenburg,Analog Filter Design. New York: Oxford Univ.Press, 1982.

[11] B. B. Hubbard,The World According to Wavelets. Boston, MA: Peters,1996.

[12] G. J. Hamink, B. W. Meijer, and H. G. Kerkhoff, “Testability analysisof analog systems,”IEEE Trans. Computer-Aided Design, vol. 9, pp.573–583, June 1990.

[13] C. M. Bishop,Neural Networks for Pattern Recognition. New York:Oxford Univ. Press, 1995.

Cascaded Parallel Oversampling Sigma–Delta Modulators

Xuesheng Wang, Wei Qin, and Xieting Ling

Abstract—Based on the well-known time-interleaved modulator (TIM), anew cascade-parallel architecture of oversampling sigma–delta analog-to-digital converters is proposed. While retaining the speed advantage of TIM,the new architecture gives a general method to effectively suppress the in-fluence of circuit nonidealities, especially coefficient mismatches, on theconverter’s resolution. Such influence is a serious problem in the practicalrealization of TIM. Simulation results of examples of both TIM and the newarchitecture are given for comparison. In addition to its improved perfor-mance, the new architecture turns out to be quite simple. Therefore it canbe a practical approach to extend the use of sigma–delta analog-to-digitalconversion to high-speed applications.

Index Terms—Cascade, converters, parallel, TIM.

I. INTRODUCTION

Because of their outstanding linearity, oversampling converters havebecome a popular technique for data conversion [2]. However, due tothe nature of oversampling, these converters are much slower than theirNyquist-rate counterparts. Hence, the applications of sigma–delta mod-ulators are usually restricted to low-speed high-linearity applicationssuch as digital audio. Emerging needs have forced designers to seekhighly linear converters with broader input bandwidths.

Manuscript received January 1999; revised October 1999. This paper wasrecommended by Associate Editor H. Tanimoto.

The authors are with the Department of Electrical Engineering, Fudan Uni-versity, Shanghai, China.

Publisher Item Identifier S 1057-7130(00)01463-4.

1057–7130/00$10.00 © 2000 IEEE