Combinational Circuits Design Topics Analysis Procedure Design Procedure Common Building Blocks Hardware Design Languages

Combinational Logic Design

Read MK 87-124, 141-161, 201-229

3.2 - Jon Turner - 04/19/23

4 Bit ALU Design Elements

Negate4 Bit Adder

Quad 4:1 Multiplexor

4 Bit Adder

Negate

4 Bit Adder

Negate

if S=0 then D=BAif S=1 then D=ABif S=2 then

D=A+Bif S=3 then D=A

S

B

AD

3.3 - Jon Turner - 04/19/23

Combinational Circuits

In combinational circuits, there is no way for a signal to flow from a gate output to one of its inputs.»so, outputs depend only on current input values (not past)

Combinational CircuitA

B

Non-combinational CircuitA

B

»non-combinational circuits use feedback to implement storage Combinational circuits are essential building blocks. Each output of a combinational circuit is a function of

the input values.»each output can be specified by a truth table or Boolean exp.»analysis: circuit specification»synthesis: specification circuit

3.4 - Jon Turner - 04/19/23

Hierarchical Design Complex systems are designed by assembling simpler

parts in a systematic and (usually) hierarchical way.»complex function at top of hierarchy, simple gates at bottom»design process can be top-down or bottom-up

Key concept is composition of simpler circuit blocks to produce more complex blocks.

odd(X0,…,X8)=odd(odd(X0,X1,X2), odd(X3,X4,X5),odd(X6,X7,X8))

Z0=odd(X0,…,X8)

9 inputodd

function

X0X1X2X3X4X5X6X7X8

Z0

top level spec 3 inputodd

X0X1X2

Z0

3 inputodd

X0X1X2

Z0

3 inputodd

X0X1X2

Z0 3 inputodd

X0X1X2

Z0

odd(X0,X1,X2) =odd(X0,odd(X1,X2))

odd(X0,X1)= nand(nand(X0,nand(X0,X1)), nand(X1,nand(X0,X1)))

3.5 - Jon Turner - 04/19/23

Design Concepts Hierarchical design is essential for managing

complexity & allows us to understand larger circuits. Design re-use is a key tool for reducing design effort.

»apply common building blocks (functional blocks) to construct larger systems

» large designs may contain many instances of a given block»generic design elements implement common functions but

may differ based on parameter values– e.g. an odd function block, with number of inputs as a parameter

Top-down design, goes from high level specification to simpler components using iterative refinement.

In bottom-up design, we identify & construct common elements that can be re-used multiple times.

3.6 - Jon Turner - 04/19/23

Analyzing Combinational Circuits

Purpose of analysis is to determine what a circuit does. Procedure

1. verify that circuit is combinational2. label all inputs, outputs and internal nets3. write logic equations for internal nets in terms of inputs4. write logic equations for outputs in terms of inputs and simplify

T1=B C T2=AB

T3=A+T1=A+B C

T4=T2D=AB D

F1=T3+T4

=A+B C+B D +BD

F2=T2+D=AB+D

ABC

D

F1

F2

T1 T2

T3

T4

3.7 - Jon Turner - 04/19/23

Derivation of Truth Tables Can derive truth tables directly from circuit. Procedure

1. For n input circuit, truth table has 2n rows, one for each binary number from 0 to 2n1.

2. Label internal nets and place columns in truth table for internal nets and outputs.

3. Fill in columns for internal netsand outputs.

ABC

D

F1

F2

T1 T2

T3

T4

F2

0101111101010101

ABCD

0000000100100011010001010110011110001001101010111100110111101111

T1

0011000000110000

T2

0000111100000000

T3

0011000011111111

T4

0101101001010101

F1

0111101011111111

3.8 - Jon Turner - 04/19/23

Designing Combinational Circuits

Procedure1. Determine number of inputs and outputs and assign

a symbol to each.2. Derive truth table for each output.3. Obtain Boolean expressions for each output.4. Create an appropriate logic diagram.5. Verify correctness by analysis and/or simulation.»Example: design circuit with 3 inputs, 1 output; the

output should be 1 when the binary value of the inputs is <3.XYZ000001010011100101110111

F11100000

1X

0 01

00 01

0 1

YZ

00 0

111 10

F =X Y +X Z

X

Z

YF

3.9 - Jon Turner - 04/19/23

BCD to Excess 3 Code Converter

Excess-3 code for a decimal digit is the binary value for the decimal number plus 3.

ABCD0000000100100011010001010110011110001001

WXYZ0011010001010110011110001001101010111100

input output

0AB

0 10

00 01

00

01

CD

01 1

011 10

x1 1

x11

10xx x

x

W=A+BC +BD

0AB

1 01

00 01

00

01

CD

10 0

111 10

x0 1

x11

10xx x

x

X=B C +B D +BC D

1AB

1 00

00 01

00

01

CD

11 0

011 10

x1 0

x11

10xx x

x

Y=CD +C D

X

Z

Y

W A

B

D

C

3.10 - Jon Turner - 04/19/23

Decoders A binary-to-unary decoder converts a binary input

value with n bits to one of 2n possible output values.3

8 D

eco

der

A0

A1

A2

D0

D1

D2

D3

D4

D5

D6

D7

000001010011100101110111

D7..D0

0000000100000010000001000000100000010000001000000100000010000000

A2A1A0 D0

D1

D2

D3

D4

D5

D6

D7

A0A1A2

2

4D

eco

der

A0

A1

E

D4

D5

D6

D7

A0A1A2

2

4D

eco

der

A0

A1

E

D0

D1

D2

D3

AlternativeImplementation

3.11 - Jon Turner - 04/19/23

Decoder Schematic & Simulation

3.12 - Jon Turner - 04/19/23

Encoders A unary-to-binary encoder converts one of 2n

input values to an encoded binary value.

00011011

A1A0

0001001001001000

D3D2D1D0

A1=D2+D3

A0=D1+D3

A priority encoder converts the first of 2n input values that are 1 to the corresponding encoded binary value.

xx0001011101111

A1A0V00000001001x01xx1xxx

D3D2D1D0 A1=D3+D2

A0=D 3+D2D1

V= D3+D2+D1+D0 -- valid output

3.13 - Jon Turner - 04/19/23

Multiplexers A multiplexer (a.k.a. data

selector) has n control inputs, 2n data inputs & a single data output»control input value

connects one data input to output

»circuit similar to decoder»optional enable input allows

construction of larger muxes –implement with AND at output

»alternative implementation uses transmission gates

D0

D1

D2

D3

D4

D5

D6

D7

S0S1S2

Y

3.14 - Jon Turner - 04/19/23

Demultiplexers A demultiplexer has n control

inputs, 2n data outputs & a single data input»control input value connects

data input to one of the outputs

D0

D1

D2

D3

D4

D5

D6

D7

S0S1S2

X

S1S0S1S0

D0D1D2D3

D0D1D2D3

Mux & demux can be used to transmit several low speed signals on a single wire.

3.15 - Jon Turner - 04/19/23

Choosing the Best Circuit Often there are many alternative circuits we can use.

» trade-off between circuit cost and performance The complexity of a circuit is the number of

elementary components needed to implement it.»often, we count simple gates (or “gate equivalents”)»example

– 8 bit decoder on page 3.10 requires 19 simple gates– an n bit decoder using the same design requires n(log2n 1) + log2n

simple gates The worst-case delay of a circuit is the maximum

time required for an input signal change to affect an output.»estimate by looking for longest input-to-output path (most

simple gates) and counting one “unit” per gate in path»can estimate more precisely if gate delays are given

3.16 - Jon Turner - 04/19/23

Increment Circuit and Half Adders An increment circuit with n

inputs and n+1 outputs computes binary value that is one larger than its input.

incr

em

en

tA0

A1

A2

A3

S0

S1

S2

S3

S4

1

S4

A0

A1

A2

A3

S0

S1

S2

S3

It can be implemented using n linked half-adder circuits.» to obtain a selectable incrementer replace

the constant 1 input with a control input» time for increment grows

with number of bits

Ai Si

Cout

Cin

3.17 - Jon Turner - 04/19/23

Addition Circuit and Full Adders

Addition circuit with 2n inputs & n+1 outputs computes the binary sum of two input values.

A0

B0

A1

B1

A2

B2

A3

B3

add

S0

S1

S2

S3

S4

It can be implemented using n linked full-adder circuits.

FAAB

S=ABCi

n

Cin

Cout=AB+BC +ACin

FAA2

B2S2

FAA3

B3S3

FAA0

B0S0

FAA1

B1S1

S4

0

A full-adder can be built from 2 half-adders.

AB

Cin Cout

S

This addition circuit is called a ripple carry adder» takes time proportional to n to add two n bit numbers

3.18 - Jon Turner - 04/19/23

Timing Simulation (post place & route)

Simulation of Adder CircuitFunctional Simulation (no gate delays)

3.19 - Jon Turner - 04/19/23

Binary Multiplication Binary multiplication is done

much like decimal multiplication.

1101 multiplicand1010 multiplier0000

11010000

1101

partial products

10000010product Requires 1 bit multipliers

(AND gates) and addition circuits.

Can speedup by rearranging so additions occur in parallel. P7P6P5P4P3P2P1P0

AdderAddend Augend

SumC

AdderAddend Augend

SumC

AdderAddend Augend

SumC

Y1

X0X1X2X3. . .

Y2

X0X1X2X3. . .

Y3

X0X1X2X3. . .

Y0X0X1X2X3. . .

3.20 - Jon Turner - 04/19/23

Incrementer with Carry Look-ahead

Can speed up incrementer using carry lookahead.

Compute carry out of each position directly from inputs.» redundant AND operations, but faster

Speed comparison» assumptions: 2 input gate has 1 ns delay,

3 or 4 input gate has 2 ns delay, 5 to 8 input gate has 3 ns delay, . . .

» 64 bit ripple carry incrementer needs 64 ns in worst-case

» 64 bit carry-lookahead incrementer needs 7 ns in worst-case

So, what’s the catch?» carry lookahead uses 2000 “simple gate

equivalents”» inputs must drive many gates

inc

S4

X0

X1

X2

X3

S0

S1

S2

S3

3.21 - Jon Turner - 04/19/23

More Scalable Carry LookaheadEN=c0 c1= ENx0x0

c2= ENx0x1x1

x0x1ENx0x1

ENx0x1x2

x2

c3= ENx0x1x2

x1x2

x6

c7= ENx0x1x2x3x4x5x6

x3x4x5x6x5x6

x5

c6= ENx0x1x2x3x4x5

x2x3x4x5x4x5

x0x1x2x3

c4= ENx0x1x2x3x3

x2x3

x4

c5= ENx0x1x2x3x4

x1x2x3x4x3x4

x7

c8= EN x0x1x2x3

x4x5x6x7

x4x5x6x7x6x7

64 bit version has 7 ns delay, about 380 gates for carry, fanout=6.

3.22 - Jon Turner - 04/19/23

Carry Lookahead Adder Ripple carry adder is too slow for fast addition of large

values (typical computer uses 32 or 64 bit arithmetic). To get a faster circuit, replace long carry chain with a

“shorter” circuit. First separate carry logic in FA.

XY

Cin Cout

S

generate

partialfull adder

Let Gi be generate signal for bit i, Pi be propagate signal and Ci be carry into bit i.C2=G1+C1P1=G1+G0P1+C0P0P1

andC3=G2+C2P2

=G2+(G1+G0P1+C0P0P1)P2

=G2+G1P2+G0P1P2+C0P0P1P2

and so forth.

propagate

»So high order carries can be generated with low delay, at the cost of more gates.

3.23 - Jon Turner - 04/19/23

C3

C4

C2

C1

C0

Simulation of Carry Lookahead Adder

Functional Simulation (0 gate delays)

Unit Delay Simulation (1 ns delay per gate)

3.24 - Jon Turner - 04/19/23

More Scalable Lookahead Adder

A more scalable lookahead adder can be obtained by writing the logic equations differently.

Let G(i,j) be true if a carry is generated from within the bits ij+1 up to i: G(i,j)=Gi + Gi1Pi + + Gij+1Pij+2Pi

Let P(i,j)=PiPij+1. Now, we can also write,

G(i,1)=Gi P(i,1)=Pi

G(i,2)=G(i,1)+G(i1,1)P(i,1) P(i,2)=P(i,1)P(i1,1)G(i,4)=G(i,2)+G(i2,2)P(i,2) P(i,4)=P(i,2)P(i2,2)G(i,8)=G(i,4)+G(i4,4)P(i,4) P(i,8)=P(i,4)P(i4,4)

These equations lead directly to the design on the following page.

3.25 - Jon Turner - 04/19/23

Lookahead Adder Schematic

About 3n+3nlog2n gates.

G(i,j)

G(i-j,j)

P(i-j,j)

P(i,j)

G(i,2j)

P(i,2j)

Up to 2+2log2n gate delays.

Partial full adder

3.26 - Jon Turner - 04/19/23

Linear Circuit Pattern Ripple-carry increment and addition circuits are

examples of a common linear circuit pattern.»copies of a common “block” with one or more signals

between adjacent blocks

. . .

Other circuits with similar pattern.» 2s-complementer, maximum, comparison, count-

ones, . . . Propagation delay for such circuits typically grows

in proportion to number of blocks. Look-ahead versions can have propagation delays

that grow with logarithm of number of blocks.

3.27 - Jon Turner - 04/19/23

Modular and Signed Arithmetic

If overflows are discarded, binary adders actually implement modulo arithmetic in which values wrap around circularly.» to add A+B, start at position for A

and then count clockwise B positions»standard addition algorithm does

exactly this.

0011+0110 =1001

1111+0011=0010

00

00

0001

1100

0010

0011

1011

0100

1010

0101

1101

0110

0111

1111

10

00

1110

1001

0 12

345

14

109 7

6

15

131211

8

1111+0011=0010

00

00

0001

1100

0010

0011

1011

0100

1010

0101

1101

0110

0111

1111

10

00

1110

1001

0 12

345

-2

-6-7 7

6

-1

-3-4-5

-8

Associating certain bit patterns with negative values yields signed arithmetic.

Negate a given value by flipping all bits and adding 1.

3.28 - Jon Turner - 04/19/23

2’s Complement and Subtraction

In 2’s complement arithmetic with n bits:» the first bit represents the sign (0 for positive, 1 for negative)» for positive numbers, the remaining n1 bits give the

magnitude in standard binary notation» to convert a positive number to corresponding negative

number, flip all bits and add 1 (00111100+1=1101)» to convert a negative number to corresponding positive

number, flip all bits and add 1 (11010010+1=0011) To subtract, take complement and add.

»410710 = 01000111 = 0100+(0111) = 0100+1001 = 1101 = 310

2’s complement is most popular method for representing negative numbers.» requires no special subtraction circuit, just addition and

complement

3.29 - Jon Turner - 04/19/23

Adder-Subtracter When sub=0, result is

A+B. When sub=1

»bit flipper complements all bits of B

»adder sums and adds 1AB = A + (B)

= A + (not(B) + 1)

= A + not(B) + 1

Takes just slightly more time than “plain” adder.

A0A1A2A3

sub

Adder

R0R1R2R3

B0B1B2B3

bitflippe

r

CinCout

3.30 - Jon Turner - 04/19/23

Alternative Negative Number Formats

In 1’s complement arithmetic, negate a valueby flipping bits (do not also add 1).»gives two different representations for zero»when adding two values, if carry out of most

significant digit, increment to obtain final sum»comparable to 2’s complement but not quite as simple

00

00

0001

1100

0010

0011

10110100

1010

0101

1101

0110

0111

111110

00

1110

1001

0 12

345

-1

-5-6 7

6

-0

-2-3-4

-7

00

00

0001

1100

0010

0011

10110100

1010

0101

1101

0110

0111

111110

00

1110

1001

0 12

345

-6

-2-1 7

6

-7

-5-4-3

-0

In sign-magnitude arithmetic, left-most bit is sign and remaining bits give magnitude.»most obvious representation for people»does not allow negative numbers to be

directly added»requires separate subtraction hardware

3.31 - Jon Turner - 04/19/23

Computer-Aided Design CAD tools are essential to the design of complex

parts. Logic design

»schematic capture - interactive creation of logic diagrams»hardware description languages - textual representation of

circuit function Design verification

» logic simulation to check circuit behavior experimentally» formal verification tools - automated correctness proofs and

assertion checking» timing analysis and simulation

Implementation» logic synthesis - convert high level spec. to low level gates»circuit layout - placement of components, routing of wires»details - clock distribution, power, pads, testing

3.32 - Jon Turner - 04/19/23

Hardware Description Languages

Read Sections 1,2 of VHDL Tutorial

HDLs allow designers to work at a higher level of abstraction than logic gates.

As with programming languages, HDL descriptions are compiled into a lower level representation.» low level form can be simulated for logical correctness»and, can be converted to a circuit specification using a

library of primitive components and timing/area constraints But don’t confuse hardware design with software.

»HDL descriptions must reduce to physical hardware that can be fit in the physical space available and meets timing specs.

»hardware designs are inherently parallel with many things going on at once

»on the other hand, software can be used to implement much more complex functions than hardware alone.

3.33 - Jon Turner - 04/19/23

VHDL Specification of Half Adder

Signal assignments occur

simultaneously. xor, and are built-in

operators

Port declaration defines inputs and outputs.

STD_LOGIC type used for signals.

library provides commonly used

types and functions

May have different implementations

for a given module.

CAD software simulates

circuit operation.

3.34 - Jon Turner - 04/19/23

VHDL Specification of Full Adder

Compact port

declarations

Complex logic

expressions.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fullAdd is

Port (a, b, Ci : in std_logic;S, Co : out std_logic; );

end fullAdd;architecture a1 of fullAdd isbegin

S <= a xor b xor Ci;Co <= (a and b) or (a and Ci) or (b and Ci);

end a1

3.35 - Jon Turner - 04/19/23

What Does VHDL Spec Mean? VHDL specifies a circuit, not sequential execution. So,

architecture arch of fulladd is begins <= (a xor b) xor Ci;

Co <= (a and b) or (a and Ci) or (b and Ci);end arch;

means

a b Ci

Co

s

So, what does this mean?architecture foo of bar is begin

a <= ‘1’; b <= a; a <= ‘0’; end bar;

3.36 - Jon Turner - 04/19/23

Signal Assignments for Vectors Example:

entity foo is port(a: in std_logic; b: in std_logic_vector(2 downto 0); c: out std_logic_vector(3 downto 0));

end foo;architecture bar of foo is begin

c <= a & (b(0) and a) & b(2 downto 1);end bar;

defines circuit

ab(2)

b(1)

b(0)

c(3)

c(2)c(1)c(0)

3.37 - Jon Turner - 04/19/23

Conditional Signal Assignment Example:

c <= "0010" when a /= b else"1101" when a = '1' else"0100";

means

ab

"0010"

c

4/

"1101"4/

"0100"4/

4/

general formx <=v1 when f1(a1,b1,...) else

v2 when f2(a2,b2,...) else

v3 when f3(a3,b3,...) else

... else vN

x <= (f1(a1,b1,...) and v1) or

(not f1(a1,b1,...) and

f2(a2,b2,...) and v2) or

(not f1(a1,b1,...) and

not f2(a2,b2,...) and

f3(a3,b3,...) and v3) or

...

3.38 - Jon Turner - 04/19/23

Selected Signal Assignment Example:

with x selectc <= "0010" when "00" ,

"1101" when "01" | "10" ,“1100" when others;

means

x

"0010"

c4/

"1101"

"1100"

0123

Resulting circuit is more compact and faster than circuit produced by conditional assignment.

3.39 - Jon Turner - 04/19/23

Important Characteristics of VHDL VHDL developed for circuit modelling & simulation.

» allows specification of hardware behavior independent of implementation

» synthesis tools developed later» not all VHDL specifications can be synthesized

Signals correspond to wires in circuit.» language also supports variables - useful in behavioral models,

testbenches» best to avoid variables in synthesizable models – (except loop variables)

Signal assignments define logic circuits.» signals on left side of assignment change as signals on right side

change (exceptions to be discussed later)» not like sequential program execution

Strong typing in VHDL.» signal types in expressions must match exactly

– no automatic type conversions» bit and integer are only built-in types» extensive support for user-defined types, such as std_logic» std_logic defines 9 values, including 0, 1 and undefined

3.40 - Jon Turner - 04/19/23

Processes and if-then-else Example:

entity foo is port(a, b: in std_logic;

c, d: out std_logic_vector(3 downto 0));end foo;architecture foo of bar is begin

process (a, b) beginif a /= b then

c <= "0010"; d <= "1100";elsif a = '1' then

c <= "1101"; d <= a & b & "01";else

c <= "0100"; d <= "10" & b & a;end if;

end process;end foo;

sensitivity list must include all

“input” signals to process

note that c,d defined under all possible input conditions -

REQUIRED

process block enables use of complex statement types

3.41 - Jon Turner - 04/19/23

Avoiding Unintended Storage If value of a signal is not specified for some condition,

it means that signal is unchanged. Example

process(a,b) begin if a = '1' then

x <= '0';elsif b = '1' then

x <= '1'; end if; -- x retains value when a=b=0

end process;

Storage elements are required to implement circuit with the specified behavior.– if one accidentally omits a condition for a signal, unintended

storage elements are synthesized. Easy way to avoid unintended storage is to start

process with assignment of default values to all signals assigned a value inside the process.

3.42 - Jon Turner - 04/19/23

Default Values Example:

entity foo is port(a, b: in std_logic;

c, d: out std_logic_vector(3 downto 0));end foo;architecture foo of bar is begin

process (a, b) beginc <= "0100"; d <= "10" & b & a;if a /= b then

c <= "0010"; d <= "1100";elsif a = '1' then

c <= "1101"; d <= a & b & "01";end if;

end process;end foo;

initial assignments define “default”

values for c and d

What values are assigned to c, d if we rearrange soif-then-else comes first?

3.43 - Jon Turner - 04/19/23

For-loopsentity adder8 is Port ( Cin : in std_logic; A, B : in std_logic_vector(7 downto 0); S : out std_logic_vector(7 downto 0); Cout : out std_logic);end adder8;architecture arch1 of adder8 issignal C: std_logic_vector(8 downto 0);begin

process(A,B,C,Cin) beginC(0) <= Cin; Cout <= C(8);for i in 0 to 7 loop

S(i) <= A(i) xor B(i) xor C(i);C(i+1) <= (A(i) and B(i)) or (A(i) and C(i))

or (B(i) and C(i));end loop;

end process;end arch1; Note separate carry signal for

each stage – cannot re-assign values to one signal as in sequential programs.

For-loop defines multiple identical (or similar) sub-circuits.

Loop does not imply sequential ordering of signal assignments.

3.44 - Jon Turner - 04/19/23

Case Statement Case statement provides convenient way to express

alternatives that depend only on value of a single signalarchitecture a1 of foo isbeginprocess(c,d,e) begin

b <= '1'; -- provide default value for bcase e is

when "00" => a <= c; b <= d;when "01" => a <= d; b <= c;when "10" => a <= c xor d;when others => a <= '0';

end case;end process;

end a1; Creates more efficient circuits than equivalent if-then-else.

others alternative is required even when all

“logical alternatives” are specified

3.45 - Jon Turner - 04/19/23

VHDL Spec. for Simple Arithmetic Unit

v bit signalsarithmetic error

c=0 means x=a, c=1 means x=b,c=2 means x= a, c=3 means x=b,c=4 means x=a+b (unsigned),c=5 means x=a+b (signed),c=6 means x=ab,c=7 means x=ba

entity alu is Port ( a, b : in std_logic_vector(3 downto 0); c : in std_logic_vector(2 downto 0); x : out std_logic_vector(3 downto 0); v : out std_logic);end alu;architecture a1 of alu issignal result: std_logic_vector(4 downto 0);signal ax, bx: std_logic_vector(4 downto 0);begin

ax <= '0' & a; bx <= '0' & b;result <=

ax when c = "000" elsebx when c = "001" else(not ax)+1 when c = "010" else(not bx)+1 when c = "011" elseax+bx when c = "100" elseax+bx when c = "101" elseax-bx when c = "110" elsebx-ax;

x <= result(3 downto 0);v <= '1‘ when (c = "010" and a = "1000")

or (c = "011" and b = "1000")or (c = "100" and result(4) = '1')or (c = "101" and a(3) =b(3) and a(3) /= result(3))or (c = "110" and a(3)/=b(3) and a(3) /= result(3))or (c = "111" and a(3)/=b(3) and b(3) /= result(3))else '0';

end a1;

3.46 - Jon Turner - 04/19/23

VHDL Spec. for Simple Arithmetic Unit

v bit signalsarithmetic error

c=0 means x=a, c=1 means x=b,c=2 means x= a, c=3 means x=b,c=4 means x=a+b (unsigned),c=5 means x=a+b (signed),c=6 means x=ab,c=7 means x=ba

entity alu is Port ( a, b : in std_logic_vector(wSiz-1 downto 0); c : in std_logic_vector(ctlSiz-1 downto 0); x : out std_logic_vector(wSiz-1 downto 0); v : out std_logic);end alu;architecture a1 of alu issignal result: std_logic_vector(wSiz downto 0);signal ax, bx: std_logic_vector(wSiz downto 0);begin

ax <= '0' & a; bx <= '0' & b;with c select

result <= ax when "000" ,bx when "001" ,(not ax)+1 when "010" ,(not bx)+1 when "011" ,ax+bx when "100" ,ax+bx when "101" ,ax-bx when "110" ,bx-ax when others;

x <= result(wSiz-1 downto 0);v <= '1‘ when (c = "010" and a = "1000")

or (c = "011" and b = "1000")or (c = "100" and result(wSiz) = '1')or (c = "101" and a(wSiz-1) =b(wSiz-1) and a(wSiz-1) /= result(wSiz-1))or (c = "110" and a(wSiz-1)/=b(wSiz-1) and a(wSiz-1) /= result(wSiz-1))or (c = "111" and a(wSiz-1)/=b(wSiz-1) and b(wSiz-1) /= result(wSiz-1))else '0';

end a1;

3.47 - Jon Turner - 04/19/23

Alternate Architecturearchitecture arithuv_arch of arithuv issignal result: STD_LOGIC_VECTOR(4 downto 0);signal ax, bx: STD_LOGIC_VECTOR(4 downto 0);signal en_a, en_b, neg_a, neg_b: STD_LOGIC;begin

process(a,b,c,en_a,en_b,neg_a,neg_b) beginen_a <= '1'; en_b <= '1'; neg_a <= '0'; neg_b <= '0';v <= '0';case c is

when "000" => en_b <= '0';when "001" => en_a <= '0';when "010" => en_b <= '0'; neg_a <= '1';

if a = "1000" then v <= '1'; end if;when "011" => en_a <= '0'; neg_b <= '1';

if b = "1000" then v <= '1'; end if;when "100" => v <= result(4);when "101" => if a(3) = b(3) and result(3) /= a(3) then

v <= '1';end if;

when "110" => neg_b <= '1';if a(3) /= b(3) and result(3) /= a(3) then

v <= '1';end if;

when "111" => neg_a <= '1';if a(3) /= b(3) and result(3) /= b(3) then

v <= '1';end if;

when others => -- do nothingend case;

case statement specifies alternatives based on signal value.

others required when not all alternatives listed.

en_a high when a used to generate result.neg_a high to produce a or ba.

3.48 - Jon Turner - 04/19/23

for i in 0 to 3 loopax(i) <= (a(i) xor neg_a) and en_a;bx(i) <= (b(i) xor neg_b) and en_b;

end loop;ax(4) <= en_a and (a(3) xor neg_a);bx(4) <= en_b and (b(3) xor neg_b);result <= ax + bx + (neg_a or neg_b);

x <= result(3 downto 0);end process;

end arithuv_arch;

for-loop modifies a, b

Original architecture synthesizes redundant components.

Alternative architecture uses single adder and disables or negates inputs to implement different operations.» circuit uses about half as many circuit components as original» synthesis report provides detailed description

extend a, b to 5 bits with correct sign

3.49 - Jon Turner - 04/19/23

entity adder4 is port(A, B: in std_logic_vector(3 downto 0);Ci: in std_logic;S: out std_logic_vector(3 downto 0);Co: out std_logic);

end adder4;architecture a1 of adder4 iscomponent fullAdder

port(A, B, Ci: in std_logic; S, Co: out std_logic );end component;signal C: std_logic_vector(4 downto 0);begin

C(0) <= Ci; Co <= C(4);b0: fullAdder port map(A(0),B(0),C(0),S(0),C(1));b1: fullAdder port map(A(1),B(1),C(1),S(1),C(2));b2: fullAdder port map(A(2),B(2),C(2),S(2),C(3));b3: fullAdder port map(A(3),B(3),C(3),S(3),C(4));

end a1;

Structural Spec. for 4 Bit Adder

component statement used to form complex circuits from simpler

parts.

Positional association of signals. Explicit

assignment (A=>A(0)) also allowed.

Component definitions required

in every architecture using a

component.

3.50 - Jon Turner - 04/19/23

Defining Constants To define constants for use by multiple entities, use separate

package.package commonConstants is

constant wordSize: integer := 8;end package commonConstants;library IEEE; use IEEE...use work.commonConstants.all;entity adder is

port( A, B: in std_logic_vector(wordSize-1 downto 0);Ci: in std_logic;S: out std_logic_vector(wordSize-1 downto 0);Co: out std_logic );

end adder;

... Local constants can be declared as part of each architecture. HDL bencher does not handle constants in packages

correctly.» use Options Map Package Constants/Defines

3.51 - Jon Turner - 04/19/23

Structural Specs. using for-generate

beginC(0) <= Ci;

bg: for i in 0 to 3 generate b: fulladder port map(A(i),B(i),C(i),S(i),C(i+1));

end generate;Co <= C(4);          

end a1; for-generate makes it easy to generate adder of any size.Note: labels are required.