FPD-Link ProDuCt FAmiLieS

The FPD-Link product family is designed for serial interfaces of embedded displays and camera sensor systems, ❶. The first generation of the FPD-Link product family was designed in the mid-1990s targeting towards a simplification of the video inter-face between the motherboard in notebook computers and embedded notebook dis-plays. By serialising the video and syn-chronization data into three to four differ-ential pairs and a clock channel running in parallel the design engineers were able to design the hinge much slimmer and they were finally able to achieve a much more EMC-friendly design.

The FPD-Link II family introduced to the market in 2005/2006 was from scratch targeted towards automotive applications. The serialization with embedded pixel clock over just one pair of wires enabled the use of very thin and flexible cables. Furthermore, the ESD resistivity was sig-nificantly increased in order to comply with the requirements of the standards ISO 10605 and IEC 61000-4-2. In this application the control data are still transmitted in paral-lel – e. g. through CAN or LIN bus systems.

Finally, the FPD-Link III product family introduced in 2010 integrates a bidirectional control channel, which is terminated in an I2C controller interface enabling the exchange of control data in addition to the

Dr. thomAS wirSChem works in National Semiconductor’s

high-Speed Data Path Division in Santa Clara (USA).

PAuL mCCormACk works in the high-Speed

Product Group europe at National Semiconductor in Fürstenfeldbruck

(Germany).

AUthORS

❶ Basic overview of the FPD-Link product families

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Multi-caMera design for parking assistantsAccording to studies conducted by IMS Research the number of automotive camera modules will grow from

6.1 million units in 2010 to more than 34 million units in 2017, whereas parking assistant systems are said

to cover the majority of these cameras’ application market. As the resolution of CMOS image sensors within

camera modules permanently increases the video interfaces will have to cope with ever rising data rates of

several Gbit / s. For this application SerDes chipsets (serializer / deserializer) using differential signalling provide

an outstanding interface solution for thin flexible cable connections without the need for additional protocol

overhead of a controller / video processor. National Semiconductor shows appropriate solutions.

video and synchronization signals in both directions between the transmit and the receive modules.

FPD-Link iii ChiP Set For Driver ASSiStAnCe APPLiCAtionS

The video interfaces of the FPD-Link III product generation significantly simplify the architecture of driver assistance sys-tems. In this context the innovative implementation of a full-duplex control channel is very remarkable. In addition to the Forward drivers and receivers the I/Os contain specific Back Channel driv-ers and receivers within the relevant counterparts. In forward direction the control data are embedded into the video data stream The back channel exchanges its data simultaneously at the same time as the video data over the same set of differential transmission lines. This ena-bles a continuous data exchange in real-time with the lowest latencies – inde-pendent of timing considerations like the length of blanking intervals, ❷.

Parking assistant systems with several distributed camera heads need a very pre-cise synchronization in order to avoid possible artefacts during the computation of the combined panoramic image. In order to enhance the EMC compliance the receiver is equipped with specific reduc-

tion methods like spread-spectrum clock-ing. With this he additional functionalities allow for an implementation with further decreased RF emissions. There is no need for an additional physical transmission channel, and this function makes addi-tional control busses ((s. o.)) like CAN or LIN obsolete for this purpose.

This allows for a reduced number of connector and cable connections, decreas-ing in turn the system costs as well as the weight of the wiring harness, which will have a positive ecological effect.

❸ shows a system diagram of the cam-era-specific FPD-Link III chipset based on DS90UB901QSQ-DS90UB902QSQ. This

❷ Simultaneous data exchange by using the FPD-Link III family

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chipset supports up to 14 data bits on top of the timing reference signals HS (Hori-zontal Sync, or respectively, Line Valid) and VS (Vertical Sync, or respectively, Frame Valid). At the end of the data pay-load the serializer attaches a 4-bit CRC (Cyclic Redundancy Check) checksum which allows for supervision in terms of data integrity for safety-critical applications.

Furthermore, up to 6 GPIOs (General-Purpose I/Os) may be programmed – e. g. in order to synchronize several distributed CMOS imager heads in applications like parking assistant systems. These GPIO data are transmitted with the minimum latencies and deviations, which reduces artefacts during the computation of the entire image.

In some applications it is mandatory to address several cameras with the same fixed address on the same I2C bus. For this purpose the chipset offers its “Slave Address Remapping” capability, where every connected component is automati-cally assigned a unique address by using an identifier. This feature is quite practical whenever camera modules are removed or, respectively, replaced. The system sup-

ports up to 8 ID indexes. The chipset syn-chronizes without a default external refer-ence clock just by using the embedded clock information. This reduces the com-ponents costs and potential sources of EMC disturbance. Finally, the serializer is integrated into a space-saving 32-LLP pack-age with a footprint of 5 mm x 5 mm in order to enable the design of more com-pact cameras with reduced volumes.

reFerenCe DeSign with Four CAmerAS For PArking ASSiStAntS

In cooperation with OmiVision Technolo-gies, Xilinx and Xylon a four-camera refer-ence design was created as a multi-cam-era system for a driver assistance/parking assistance system, ❹. Four OV10620 CMOS image sensors from OmniVision are con-nected to serializer boards employing the DS90UB901QSQ transmitter and standard RJ-45 plugs. The signal is transmitted through a single pair of wires from an unshielded CAT6 network cable, which is 10 m long. Four DS90UB902QSQ receivers are consolidated on an FMC (FPGA Mezza-nine Card). This FMC board is a daughter

card stacked on top of a VSK (Video Starter Kit) Spartan FPGA Base-Board from Xilinx. The FPGA contains IP from Xylon (Branding: logicBRICKS) running image-stitching and surround-view algo-rithms. The entire configuration including the dynamic re configuration of the OmniVision image sensor is performed solely by the FPGA control unit via the I2C interface of the SerDes chipset. The cameras may be operated individually as well as in combination. Switch-over times between the individual modes are very short because they are in the 10-micro-seconds range. The bidirectional control channel operating in parallel to the video data enables minimum latencies and finally the synchronization of the camera video data on a frame-by-frame basis. Consequently, the combined total image avoids any kinds of artefacts due to uncal-ibrated image delays.

overview: the BASiC ProPertieS oF the ChiPSet

The operating frequency range for the pixel clock (PCLK) is between 10 MHz and 43 MHz. On both the send as well as the receive side there is no crystal (quartz) or oscillator needed in order to provide a reference clock for the presyn-chronization of the PLL (Phase-Locked Loop). The PLL automatically autono-mously locks to any kind of data pattern received as long as start/stop clock bits are embedded into the signal. Further-more, the PLL provides phase-synchro-nous impulses to the demultiplexer. As soon as the deserializer has synchro-nized to the serializer data stream it shows the completion of this action at the external LOCK pin. From now on the output data e. g. to the LCD timing controller are provided with the correct

❸ System diagram of the DS90UB901-DS90UB902 FPD-Link III chipset

❹ Block diagram of a reference design with the FPD-Link III chipset and four cameras

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polarity. In order to transmit data over long cable distances of up to 15 m the receiver stage contains an equaliser, which compensates the frequency-depending attenuation of the transmis-sion media and cleans the signal from deterministic phase jitter. Input and out-put data busses may be flexibly aligned with either the rising or the falling edge of the pixel clock signal.

The relevant I/O banks may either be powered by a 1.8 V or a 3.3 V power supply, which means that there is addi-tional flexibility when components on the graphical source and on the graphical drain are connected together. In order to reduce the electromagnetic radiation the deserializer is equipped with an inte-grated Spread-Spectrum Clock Generator (SSCG) output, with an adjustable output driver and with staggered outputs which are time-delayed relative to the recovered clock signal.

In addition the PLLs of the chipsets are designed in a flexible way which means that they are tolerant towards external spread-spectrum clocking on the trans-mitter module. This feature is needed in order to use the maximum advantage of the frequency-spreading over the entire data path from the graphics host via the parallel in put interface up to the serial and parallel output interface.

The ESD robustness is qualified according to the automotive-relevant standard ISO 10605 and according to the IEC 61000-4-2 standard. The very broad temperature range from –40 °C up to +105 °C opens up use cases in a multi-tude of applications, e. g. if the imager camera head needs to be positioned in exposed areas susceptible to intensive heat irradiation like in front of the radia-tor grille of a passenger car. The compo-nents are integrated in space-saving com-pact LLP packages. This industry-stand-ard package in “no pullback” implemen-tation is excellently suited for process-ing/handling and inspection and is avail-able in a lead-free version. Of course, all components are qualified according to the standard AEC-Q100 Grade 2.

SummAry

The product definition of the new LVDS-based family of FPD-Link III Serialiser/Deserialiser chips is oriented towards a total-system concept of a camera-based driver assistance system. The problematic nature of imager configurations at the ECU side was solved elegantly with an embed-ded control channel function at very low, deterministic latency with minimal timing variations. Through the integration of a continuously working control and return

channel conventional control busses are no longer needed, resulting in savings in terms of cost, complexity and weight. The two-wire solution with additional AC-cou-pling allows for the use of ultrathin and long cable connections at exposed loca-tions and facilitates the placement within the car chassis. The combination of high bandwidth, low EMI, noise immunity, autonomous synchronization and support of cost-effective twisted pair cable media assure that these chipsets are a real plug-and-play solution. Equipped with these features the SerDES chipsets are well-suited for a variety of video and control data transmission functionalities in a mul-titude of automotive applications but also in industrial applications.

The FPD-Link III technology enables a two-wire solution for camera connections.

This is in contrast to conventional solu-tions, which required an additional con-trol bus (e.g. CAN or LIN) with further cabling requirements.

The FPD-Link III interfaces exchanges both video and control data simultan-ously.

In addition a remote power transfer from the control unit to the camera image sen-sor is feasible as well, so that all necessary functions can be implemented on merely two wires as interconnect, while maintain-ing minimal latency for data exchange.

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3705I2011 Volume 6