muhammad nawaz, secrc/pt, 12 september 2016

© ABB GroupSeptember 12, 2016 | Slide 1

Characterization and Modeling of SiC MOSFETPower Modules:ABB Corporate Research, Västerås, Sweden

Muhammad Nawaz, SECRC/PT, 12 September 2016

14th MOS-AK ESSDERC/ESSCIRC Workshop, Lausanne, 12th September 2016

ABB internaluse onlyOutline

§ Introduction (Motivation of SiC)

§Semiconductor Device Modeling

§Semiconductor Device and Circuit Characterization

§Challenges

§Conclusion

© ABB GroupSlide 2

ABB internaluse only

© ABB GroupSlide 3

Why Silicon Carbide Offers Potential Replacement to Silicon ?

SiC now visible in• Traction• Hybrid electric vehicle• PV inverters• Air conditioning

SiC OffersØ More system compactness:Ø Efficient heat extraction: relaxed cooling requirementØ Lower conduction and switching losses: higher power

conversion efficiencyØ Well suited for high temperature electronics (already

proven upto 500 - 600 oC: Good for oil and gas)Ø Radiation hard (1000x resistant than Si) materialØ Lower environmental impact and well-suited material for

harsh environment

1.1

3.21.0

2.0

1400 950

1.5

3.3 – 4.9 0.25

2.4

Bandgap (eV)

Saturation velocity (*107 cm/s)

Electron mobility (cm2/V.s)

Thermal conductivity (W/cm.K)

Breakdown field (MV/cm)

Silicon Carbide: SiCSilicon: Si

GaN:§ Lacks substrate (-)§ Horizentol transport (-)§ Gate oxide ? (-)§ Low thermal conductivity (-)§ Mostly Normally on (-)§ Reliability ?§ Cost (+)§ Integration/Functionality (+)

© ABB GroupSlide 4

DesignSystem

.MODEL NMOS BSM3V32K1=0.2 K3=0.5U0=100 VTH0=0.5LINT=50E-09 A0=1.0WINT=10E-09 A1=0CJ=1.0E-03 CGDO=2.0E-10CJSW=1.0E-10 CGSO=2.0E-10......

Test Structures

Technology

Characterization Modeling

CircuitDesign

Thirsty Customer Need

(e.g., IBM/Panasonic/AMD)

ProcessSimulation

DeviceSimulation

Intelligent MOS

Semiconductor Product Value Chain

Die size~ nm - µm

§© ABB Group

§ April 09, 2014

IGBT chipSubmodule

StakPak™

collectorGate unit

heatsink

Gate units and voltage divider

Coolers 2 x 8 StakPak moduleTightening frame 100 kN

Cooling Pipes

Optical Fibers

Support Insulators

mass 3,000 kgCurrent Conductors Converter arm

Valve hall

Presspak IGBT4.5 kV, 2.0 kA

Si-wafer

T2

CDC

MSW1

MSW2

L=20 – 30 mW=15 – 25 mH=15 – 25 m

1 GWInsulationReactorsTransformersBushing

Input Gate

High Power Electronics Value ChainTailor-made for transmission applicationsDie size

~ mm - cm

Major Cost Down DriversØ High ampere per chip Area

- Probably next generation Trench devices

Ø Large Wafer (From 4 to 6” will lead to 20 – 30 % reduction of cost)

- Transition to 6-inch wafer manufacturing process

Ø Higher Yield with higher volume

Ø More Asian (China, Korea, Japan) SiC players are entering into the SiC

Market. Thus competition drives down the cost

Ø Matured Fabless concept (Commercial foundary service like earlier Si

devices)

SiC Material Supply and Cost Down Potential

Cost current status• SiC diodes cost 5x – 7x than that of silicon• SiC MOSFETs cost 10x – 15x than that of Si• Cost of 6” today is 1200 – 2000 USD

(depending on the wafer quality)

• Base Material Supply: OK

• Epi Cost Dominates ForHigh Voltage Devices

Mitsubishi SiC module (1.2kV/800A):FMF800DX-24A: 1500 EuroCree SiC module (300A):CAS300M12BM2 (1.2kV): 500 EuroCAS300M17BM2 (1.7kV): 850 USDROHM SiC module (1.2kV/300A):BSM300D12P2E001: 600 Euro


Semiconductor Device Modeling: Simulation Hierarchy

Quantum Transport

Semiclassical TransportBoltzmann Equation

Drift-diffusion , Hydrodynamic

TCADTechnology Based Computer

Aided Design

Compact Models

Spe

ed

Accuracy

Com

plex

ity• Complex band structures• Detailed scattering models• Only material-dependent parameters• Hot-carrier analysis• DC, AC and noise analysis• No adjustable parameters in the RF noise model

Process SimulationOxidation, diffusion, Ion implanation, deposition,

etching, lithography, metallization etc.,

Device Simulationgeometry, carier statistics, transport models, bandgapengineering, traps/defects model, tunneling model etc.,

Quantum Hydrodynamics and Quantum Monte Carlo:Keep all hydrodynamic features plus quantum correction

Quantum-Kinetic Equation:(Liouville, Wigner-Boltzmann: Accurate upto single particle description)

Green Functions Methods:

Direct solution of n-body Schrödinger equation

Pros• Realistic device structure• Microscopic, accurate

physicsCons• Numerically challenging• Limited device detail

(2D, only few parasitics)• Very slow

Simple physics based, Fast enough and

accurate description of circuit behavior

Few SiC MOSFET MODELsName Year Model Level Contributions Simulation tool

McNutt 2003, 2007 Physics Improved channel current description as the sum of two componenents IMPACT

Hasanuzzman 2003, 2006 Physics Drift region divided into three parts PSPice

Hasanuzzman 2004 Semi-Physics Temperature dependent compensating currents ----------

Power 2007 Numerical Comprehensive numerical model considering position dependent mobilty -----------

and interface states

Wang 2008 Semi-physics Simple Spice model for DMOSFETs with some specific modifications in the PSpice

conventional Si lateral MOS channel modeling approach

Potbhare 2008 Semi-numerical Comprehensive physical model incorporating interface trap densities, ----------

surface roughness scattering, phonon scattering, velocity saturation …

Cui 2012 Semi-physics nth power law MOSFET model used to simulate high voltage SiC power transistors PSpice

Yin 2013 Semi-physics Foster RC network used for thermal modeling PSPice

Lu 2013, 2014 Semi-physics Modified SiC MOSFET model valid at low temperature, the effect of negative gate PSPice

drive voltage on gate source capacitance also included

Alexakis 2014 Behavioral Model has drain-source resistance and three constant interelectrode capacitance MATLAB

D’Alessandro 2014 Semi-physics Temperature dependent gate threshold voltage and carrier mobility model Pspice

Merkert 2014 Behavioral A pure mathematical model topredict device losses Matlab

Fu 2010, 2012 Physics Non uniform current distribution in the JFET region modeled using a nonlinear PSpice

voltage source and a resistance network

Mudholkar 2011, 2014 Physics New parameter extraction strategy based on McNutt model relies only on the datasheet SABERRainer 2015 Physics A compact model is based on a thorough consideration of the physical phenomena PSPice

which are important for the device characteristics and its electro-thermal behavior.

Introduction: model development flow

Ranked list of the main quantities to be optimized1. Switch losses2. Driving requirements and external circuit impact on the di/dt and dv/dt3. Capability of fitting different voltage and current levels4. Current peak at turn-on (diode reverse recovery)5. Voltage overshoot at turn-off (stray inductances)

Tunableparameter

Extractionroutine

Ø The only available measurements are at module level.Ø Parameter extraction is based on these measurements, thus internal parasitics are averaged and paralleling issues

and other nonidealities cannot be accounted for specifically but of course affect the parameter values.

IGBT models: Hefner vs. Lumped Charge


Hefner:Ø Good accuracy and reliability

Ø Introduced NQS effects analysis (fast penetration of SCL in base)

Ø Both NPT and PT structures were modeled

Ø Originally implemented in SABER, later adapted for PSpice (even in simplified versions).

Ø Needs device manufacturing parameters (doping, layer thickness etc.):

Ø Difficult and costly technological parameter extraction (special for our module)

Lauritzen Lumped Charge:Modular approach for power semiconductor device modeling (diode, GTO, MOSFET, BJT, IGBT etc.)

Easier and faster parameter extraction procedure:

Only 3 exp. setups required: DC IC-VCE characteristic, Gate charge, Inductive load switching

No need for device manufacturing parameters

Third party device characterization possibleLauritzen Device parameters17 for IGBTs and 7 for diodes

Hefner Device parameters42 for IGBTs

Lumped Charge Modeling Technique: some concepts


Steps involved:1. Discretize the device in critical regions characterized by constant doping and/or constant carrier

lifetimes2. Assign each region one charge storage node (if relevant) and up to two connection nodes

1. Each node describe the carrier distribution and behavior as if they were all lumped into that point3. Link the regions with physical and circuital equations:

i. Current Density Equationsii. Current Continuity Equationsiii. Charge Neutrality Equationsiv. Boltzmann’s relations (P-N Junction Equations)v. Poisson’s Equationsvi. KCL and KVL Equations

Equations (i) through (v) describe carrier distribution and transport between charge nodesEquations (vi) relate the internal variables to the terminals of the deviceThis method can be applied systematically to power device if we see them as a combination of the followingrepresentative structures:P+N- structure (or N-P+)N-N+ structure (or P-P+)MOS structure

Lauritzen Model was implementation into Pspice platformand semiconductor evaluation:


Lauritzen’s IGBT model

Parameter Description Unit SPICE name

kp MOSFET transconductance coefficient A kp_m

kv Turn-on Voltage fitting parameter n. u. kv_m

VT Threshold Voltage for turn-on V v_thr

b Fitting parameter for MOSFET transconductance n. u. bp

VJ Built-in Voltage for p-n junctions V v_j

VPT IGBT internal punch-through Voltage V v_pt

ILH Threshold between high and low level injection A ilh

T0 Base transit time s t_0

τB Base carrier lifetime s t_b

τE Internal emitter efficiency expressed as a lifetime s t_a

RH High Voltage & current charge compensation Ω r_h

RE Emitter parasitic series resistance Ω r_k

LE Emitter parasitic series inductance H l_k

COX Gate-Collector oxide capacitance F cox_m

γ Gate-Collector body effect coefficient V½ gamma_m

Cge0 Gate-Emitter capacitance F cgk_0

Cce0 Collector-Emitter capacitance F cak_0

• IGBT PARAMETER SET

Capacitive parameters

Conduction parameters

Parasites

Dynamic parameters

Simplified division!

4.5 kV

ü Blocking voltage: 4.5 kVü Nominal current: 2.0 kA

4.5 kV StakPak™ K Series Press-pack IGBT


Comparison of Static Characteristics of Pspice model and Experiment

© ABB GroupSlide 13 M. Nawaz et al., IEEE, ECCE-2013

P. O. Lauritzen et al.,“A basic IGBT model with easy parameter extraction,”in Proc. IEEE PESC’01 Conf., vol. 4, 2001, pp. 2160–2165.

1. The device is discretized, or partitioned, into several critical regions,each of which contains one charge storage node and up to twoconnection nodes; each region is then assumed to present constantdoping or constant carrier lifetimes

2. The hole and electron charge values at each node are obtained bymultiplying the carrier concentration and its critical volume

3. The nodes are finally linked using the following six equations, derivedfrom device physics and circuit theory:I. Current density equationsII. Current continuity equationsIII. Charge neutrality equationsIV. Boltzmann’s relations (P-N junction equations)V. Poisson’s equationsVI. KCL and KVL (Kirchhoff Current Law and Voltage Law)


Dynamic Comparison of Pspice mode and experiment

© ABB GroupSlide 14

Voltage pulse is applied at the gate terminal and no gate driver

M. Nawaz et al., IEEE, ECCE-2013 P. O. Lauritzen et al.,“A basic IGBT model with easy parameter extraction,”in Proc. IEEE PESC’01 Conf., vol. 4, 2001, pp. 2160–2165.


Cell verification using Pspice and its performance evaluation with StakPak modules

Turn off gate current unitTurn on gate current unit

M. Nawaz et al., IEEE, ECCE-2013 P. O. Lauritzen et al.,“A basic IGBT model with easy parameterextraction,” in Proc. IEEE PESC’01 Conf., vol. 4, 2001, pp. 2160–2165.


© ABB GroupSlide 16

Dynamic comparison of PSpice model and experiment

+

M. NawazM. Nawaz

Development of a Simple Analytical PSpice Model for SiC Based BJT Power Modules

Current-voltage characteristics (i.e., ICE Vs VCE) at different base currents for 4H-SiC BJT power module at 300 K (a) and 425 K (b).

Daniel Johannesson and Muhammad Nawaz, In IEEE Trans On Power Electronics Vol. 31, No. 6, pp. 4516 – 4525, June 2016

Gummel-Poon Model of BJT

300 K 425 K

The measured and simulated dynamic performance of 4H-SiC BJT power module at collector-emitter voltage levels VCE=600 V (a) 300 K.

Development of a Simple Analytical PSpice Model for SiC Based BJT Power Modules

1.2 kV, 800A

Daniel and Nawaz, Microelectronics Journal (MEJ), Vol. 53, pp. 167-176, -2016

T.R.McNutt et al., Silicon carbide power MOSFET model and parameterextraction sequence, IEEE Trans.Power Electron. 22(2), (2007), pp. 353–363.

MOSFET Model for Mitsubshi Power Module

Development of Pspice Modeling Platform for SiC MOSFETsStatic Characterization M. Nawaz, ECCE-2016, 20th September, USA

1.7 kV/300 A: Cree

1.2 kV/300 A: Microsemi

1.2 kV/120 A: ROHM

Development of Pspice Modeling Platform for SiC MOSFETs: CreeParallel MOSFETs

M. Nawaz, ECCE-2016, September, USA

Turn On Turn Off

Turn Off Turn OnVariation of gate resistance from 2. 7 – 10.0 Ω

Model accurately predicts dynamic behavior with influence of Rg variation on• dI/dt, dV/dt• Current/Voltage overshoot

Parameters Extraction


ROOM TEMPERATURE PARAMETERSParameter Unit Module 1 (Cree) Module 2 (Microsemi) Module 3 (Rohm)

VBD Module Rated Breakdown Voltage kV 1.7 1.2 1.2ID Module Rated Drain Current A 325 357 180VT Gate Threshold Voltage V 5.287 4.960 6.648Kp Saturation Transconductance A/V2 28.04 32.012 10.392Kfl Low Current Transconductance Factor - 0.055 0.067 0.085θ Transverse Electric Field Parameter - 0.001 0.005 0.006

dVtl Low Threshold Voltage Difference V 2.129 2.322 3.943Kf Linear Transconductance Factor - 1.043 1.205 1.059Rs Drain Series Resistance Ω 1.2 1.7 1.1A Active Area cm2 0.174 0.123 0.112

Nb Bulk Doping Concentration cm-3 0.906×1016 1.283×1016 1.283×1016

Wb Bulk Thickness µm 14 10 10Pvf Pinch-off Voltage Factor - 0.65 0.65 0.45Cgs Gate-Source Capacitance nF 20.05 15.43 20

Coxd Oxide Capacitance nF 12.14 12.34 12Agd Gate-Drain Depletion Area cm2 0.054 0.091 0.052VTd Gate-Drain Depletion Threshold V -9 -9 -11

Fxjbe Depletion Charge Factor - 0.5 0.5 0.5

§ A set of room temperature parameters and temperature dependency coefficients has been obtained for each of the three devices(from three different manufacturers)

§ Only minor tunings have been performed to optimize and refine the agreement with experimental results

TEMPERATURE DEPENDENCY PARAMETERS

Parameter Module 1 Module 2 Module 3

VT0 Gate Threshold Temperature Coeff. 5.609 5.017 7.002

VT1 Gate Threshold Temperature Coeff. -0.0166 -0.0137 -0.0178

Kp0 Saturation Transconductance Temperature Coeff. 28.04 32.2 10.392

Kp1 Saturation Transconductance Temperature Coeff. 2 0.58 1

Model Verification: Series ConnectionThe series connection of power devices• Attractive way to scale up the voltage and power

rating of the setup.

• The model needs to be verified for the seriesconnection as well.

• Dynamic and static voltage sharing are crucialfrom a reliability point of view.

• Auxiliary circuits are used to overcome theaforementioned problems.

Total Voltage ~1.6kV.Gate resistance 20 Ω.Slow transient resultsin equal sharing.

M. Nawaz, ECCE 2016, September, USA

• Gate voltage waveforms for intentionalmismatch of gate resistances.

• The gate driver imposes a 4ns delayto the lower device.

• Lower device Rg=8.2 Ω• Upper device Rg = 9.0 Ω

• 1.2 kV – 400 A: Turn off waveforms• Accurate prediction of the dynamic and static

balance sharing.• Conclusion: The model can be used to facilitate the

design of auxiliary circuits for the series connection.

Model Verification: Single DeviceOver-voltage prediction• Crucial for voltage limiting circuit design.• Device has to operate within its Safe

Operational Area.• Unnecessary design margins have to be

avoided. Need for high precision.

Switching losses prediction• Very good prediction regardless of

the load current.• Conclusion: The model can be used

to facilitate the design of auxiliarycircuits for the single device.

M. Nawaz, ECCE 2016, 20th September, USA

MOSFET RON Comparison PowerSiC

TCAD

M. Nawaz, PEDS 2013

IGBT RON Comparison PowerSiC

Pcond = (Vknee.I+I2.Ron).δ is the conduction loss where δ is the duty cycle (=0.5), I (A) is the given rated currentof a chip for each voltage class and Ron is the on-resistance (mΩ-cm2).Psw= EON + EOFF is the total switching loss for each voltage classPtotal = Pcond + Psw

TCAD

M. Nawaz, PEDS 2013

ABB internaluse onlyWhat is Expected From Wide Bandgap Semiconductors ?

Ø RON of SiC-IGBT is superiorthan that of SiC-MOSFETsand Si-IGBTs.

Ø ECOND of SiC-IGBT for highvoltage class device is betterthan that of SiC-MOSFET andSi-IGBT. However thedifference in conduction lossis minimal at lower voltageclass device.

Ø ESWITCH (at 1 KHz) of SiC-MOSFET is far better thanthat of other two devices (i.e.,Si-IGBT and SiC-IGBTs).Compared to Si, SiC device isbeneficial for high frequencyapplications.

25M. Nawaz, PEDS 2013

1.4 cm X 1.4 cm 1.7 cm X 1.7 cm

2016 A 2850 A 4200 A 2016 A 2850 A 4200 A

f=100 Hz

Si-IGBT Si-BIGT 10-kV SiC 15 kV-SiC 20 kV-SiC2013 2015 2017 2018 2022

Compactness: Si Vs SiC

Pcond = (Vknee.I+I2.Ron).δ is the conduction losswhere δ is the duty cycle (=0.5),I (A) is the given rated currentPsw= EON + EOFF is the total switching lossPtotal = Pcond + Psw is the total loss

Compactness: Si Vs SiC

2016 A 2850 A 4200 A 2016 A 2850 A 4200 A

Comparison of SiC-MOSFET and Si-IGBTs: 1.7 kV, 300 AMuhammad Nawaz, Kalle, Ilves, APEC – March 2016, USA

SiC-MOS Si-IGBTs

SiC-MOS Si-IGBTs

Turn on Turn off

From Microsemi

Parameter

SiC (Si)

1000 V

230A, 25oC

1000 V

230A, 75oC

1000 V

230A,125oC

Eon (mJ) 12 (68) 9 (89) 8 (--)

Eoff (mJ) 28 (86) 26 (99) 27 (--)Etotal (mJ) 40 (154) 35 (188) 35 (--)

ENERGY LOSSES AT VARIOUS TEMPERATURESFOR SiC-MOSFETS AND Si-IGBTS (INSIDE BRACKET).

Losses SiC-MOSFETs Vs SiC-IGBTs: Microsemi

SiC MOS Losses: Temperature insensitiveNo reverse recovery

Si-IGBT Losses: Temperature sensitiveHigh reverse recovery loss

Muhammad Nawaz, Kalle, Ilves, APEC – March 2016, USA

SiC-MOSFETs: Influence of gate resistance with GDUTurn Off Turn ON

Rgon = Rgoff =10 Ω (white)Rgon=10 Ω, Rgoff =4 Ω (red)

“Static and Dynamic Performance Assessment of Commercial SiC MOSFET Power Modules”Muhammad Nawaz, Filippo Chimento, Kalle, Ilves, pp. 4899 – 4906, IEEE, ECCE-2015

Short Circuti Tests: 1.7 kV SiC MOSFETs

Ø Devices have SCcurrent of 11 – 13 xthan nominal currentrating (300A)

Ø Devices survived fora period of 4 – 5 µstested between 800– 1000 V

Ø Devices survived for10 µs when tested at< 700 V

T = 300 K

T = 300 K

T = 300 K

T = 300 K

Device 2 @ 800 V Device 2 @ 800 V

Device 1 @ 1000 V Device 1@ 800 V

M. Nawaz, 20th September, ECCE 2016

• Devices have SC current of11 – 13 x than nominalcurrent rating (i.e., 180 A)

• Few devices did notsurvive for a period ofeven 2.0 µs testedbetween 700 - 800 V

• Generally, devicessurvived for 10 µs whentested at < 700 V

Short Circuti Tests: 1.2 kV SiC MOSFETsVds=600 V, T = 300 K

10 µs

Vds=700 V, T = 300 K

10 µs

Vds=700 V, T = 300 K

10 µs

Vds=600 V, T = 300 K

10 µs

M. Nawaz, ECCE, 20th September, 2016

Unclamped Inductive Switching Tests (UIS)

For 1,2 kV Si-IGBTs: 0.6 – 0.05 J tested from 25 – o200 CU Schlapbach and M. Rahimo, ISPSD 2007

Cree: 1.2 kV, 80 mΩ SiC MOSFET: 2.20 J1.2 kV Si-IGBTs: 0.01 – 0.1 J

www.power-mag.com, pp. 16 – 19, Issue 1, 2013, Power Electronics Europe

SiC Future Technological Challanges• Availability of defect free large wafer size (6” – 8”) so as to reduce overall device cost.

• Development of good quality large area p-doped substrate.

• Defect free thick (> 100 µm), good quality p and n-epitaxial layers for realizing 10 - 20 kV devices.

• Reliable gate dielectric and passivation process (kSiO2 = 3.9, kAl2O3 = 9.0, kSiC = 9.6).

• Stable and mature ion implantation and activation process.

• Good quality low resistance ohmic contacts (i.,e stable annealing process) to n and more important to p-doped SiC layers.

• Development of stable and reliable edge termination extension (JTE) process so as to get close to idealsemiconductor breakdown.

• Good quality MOS interface (low interface state density, high channel mobility)

• Development of packaging technology (die-attach, toping material) for high power and high temepratureapplications.

• Lingering questions about reliability, Vth stability, dV/dt and dI/dt control1.2 kV 1.7 kV 1.7 kV 1.7 kV 3.3 kV 6.5 kV 6.5 kV 10 kV 10 kV 15 kV 20 kV 25 kV2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2025

IGBT/GTOs/IGCTsMOSFETsMOSFETs

CONCLUSIONsØSi based IGBTs, BIGTs and IGCTS (BGCTs) will keep going on the delopment track until some time with major

focus to further improve the power rating and high temperature operation.

ØABB still keeps SiC business on its wish list with diodes, MOSFETs, IGBTs, GTOs future candidates.

ØDiscrete devices and power modules with 1.2 - 1.7 kV rating (BJTs/MOSFETs/JFETs) are now available fromvarious manufacturers (e.g., Cree, Rohm, Microsemi, Mitsubishi, Infineon, Powerex etc.,)

ØReliability data from these SiC devices is just now coming in to strengthen the end-user confidence level.

ØMost producton is currently on 3 - 4 ” substrate. 6” SiC substrates are now available that may leads to 20 – 30 %cost reduction.

ØProducing high voltage SiC devices are now feasible. Engineering (R & D) 1.2 - 10 kV SiC MOS dies are nowavailable. But still there is a lot of wait for the time to market. SiC business atleast for HV class is now in mode

muhammad nawaz, secrc/pt, 12 september 2016

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