ms thesis of al ameen 1.5 2010

F~COMPSYNTH: A TOOLKIT FOR VARIOUS

AUTOMATIC MATCHING AND SYNTHESIS OF

VARIABLE SIZED ANALOG AND DIGITAL VLSI

COMPONENT

MS Thesis by

Mahmudul Faisal Al Ameen

Department of Computer Science & Engineering

East West University

Dhaka, Bangladesh

F~COMPSYNTH: A TOOLKIT FOR VARIOUS AUTOMATIC

MATCHING AND SYNTHESIS OF VARIABLE SIZED

ANALOG AND DIGITAL VLSI COMPONENT

By

Mahmudul Faisal Al Ameen

A thesis submitted in partial

fulfillment of the requirements for the

degree of

MS in CSE

East West University

2007

SUPERVISORS

Syed Akhter Hossain Md. Didar Islam

Chairman & Associate Professor CEO

Dept. of CSE, East West University Power IC Ltd.

Dhaka, Bangladesh Dhaka, Bangladesh

This work is done with the financial support of

“Imdad-Sitara Khan Foundation, Saratoga, California,

USA” under AABEA Imdad-Sitara Khan Foundation

Fellowship program

DEDICATED TO

GRANDPARENTS AND PARENTS, MY PAST

ALL THE TEACHERS, MY PRESENT

YOUNGERS & AZWAD AHNAF, MY FUTURE

DECLARATION

I hereby declare that this thesis entitled ―F~CompSynth: A Toolkit for

Various Automatic Matching and Synthesis of Variable Sized Analog and

Digital VLSI Component‖ has been composed by me and all the works

presented herein are original and my own. I further declare that this work

has not been submitted any where for any academic degree.

[Mahmudul Faisal Al Ameen] MS Student Department of Computer Science & Engineering

East West University Dhaka, Bangladesh

ABSTRACT

This research work intends to solve an industrial problem in the area of

highly efficient analog and digital IC production. It formulates and

implements series of techniques for parameterized and inter-component

matched automatic VLSI device layout synthesis. In the field of Analog

VLSI layout design, large variation of components‘ sizes, doping intensity

variation and different stress level at etching, etc. (Hastings, 2001) cause

mismatches and reduce the performance of IC. Some design rules, slicing

of large components and placements of the segments in a certain

arrangement is suggested to avoid mismatches. A symmetry and average

positioning of the segments of the components ensure as average imposing

as possible and the efficiency increases. Although some matching patterns

(methodology) for good matching are followed by the layout designers, still

this process is manual and is absent in the current CAD tools for

automation, hence it is costly and requires much time with ―design

correction-fabrication-testing‖ iteration process. In this thesis, automation

algorithms of some well established arrangement patterns are proposed

with implementation as a CAD tool. A mathematical model has been

proposed to measure or predict the performance how good they can match

each other. An object base dynamically typed scripting language, Device

Template Scripting (DTS), also has been designed to synthesize different

sizes of VLSI components based on fully customizable technology specific

DRC rule set. All the algorithms are implemented as a commercial

simulation toolkit that has been developed on Java 6.0 which guarantees

cross platform execution of the application. For commercial use and

flexible portability the synthesized layout can be exported as GDSII file. A

large set of experimental data has been provided at the end of the thesis to

show the efficiency of the algorithms and their implementations.

F~COMPSYNTH: A TOOLKIT FOR VARIOUS AUTOMATION MATCHING AND SYNTHESIS

OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT i

TABLE OF CONTENTS

1. INTRODUCTION 2

2. PROBLEM DESCRIPTION AND PREVIOUS WORKS 7

2.1. Concept on Some Basic Devices 7

2.1.1. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 7

2.1.2. Resistances 8

2.1.3. Capacitors 9

2.1.4. Bipolar Transistors 10

2.1.5. Logic Gates 10

2.2. CMOS Mask Layers 10

2.3. Matching Issues 12

2.3.1. Causes of Mismatches 13

2.3.2. Objective of Matching 14

2.3.3. Different Matching Issue 14

2.3.4. Matching Pattern 15

2.4. Previous Work 22

3. BASIC ARCHITECTURE AND SYNTHESIS FLOW 27

3.2. Component Block Diagram 27

3.3. Process Flow 28

4. DESIGN OF ALGORITHMS AND DATA STRUCTURES 31

4.2. Pre-Input 31

4.2.1. Device Template Scripting 31

4.3. Input 39

4.3.1. Device Name 39


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT ii

4.3.2. Number of Components and their Name 39

4.3.3. Length and Width 40

4.3.4. Number of Fingers of the Components 40

4.3.5. Matching Pattern 41

4.4. Process 41

4.4.1. Matching of the Components 41

4.4.2. Mathematical Model for Analog Device Matching Prediction 48

4.4.3. Component Synthesis 52

4.4.4. Placement 54

4.4.5. Editing 57

4.5. Output 58

4.5.1. Screen Output 58

4.5.2. GDSII Output 59

5. DESCRIPTION OF F~COMPSYNTH: A MATCHING AND SYNTHESIS

TOOLKIT 62

5.2. Functional Flow Chart 62

5.3. Interactive Layout Editor 63

5.4. Matching Wizard 67

6. EXPERIMENTED RESULT 74

6.2. Algorithms and its’ Complexities 74

6.3. Variable Sized Component Synthesis 76

6.4. Component Matching 78

6.5. Mathematical Pattern Testing 80

6.6. Placement of the Fingers of the Components 82

7. CONCLUSION AND RESEARCH DIRECTION 85


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT iii

LIST OF FIGURES

Number Page

Figure 1 Layout Top-view of an NMOS and Identical NMOS Cross-

section view 8

Figure 2 Layout Top-view of an NMOS and Identical NMOS Cross-

section view 8

Figure 3 Typical symbol and layout view of a 3-pin PWELL res 9

Figure 4 Symbol and top view of an oxide-cap 9

Figure 5 NPN Transistor and Substrate PNP 10

Figure 6 MOS MN1, ND1, MN4, MN4 & MN5 with standard matching:

1. Diode ND1 at middle, 2. All MOS are on same orientation and 3.

All MOS are at minimum spacing 15

Figure 7 NPN with Common-centroid matching and MOS with Cross-

coupled matching 21

Figure 8 Resistances with inter-digitized matching 21

Figure 9 Sample interditization patterns for two dimensional common

centroid arrays 22

Figure 10 four major components and information flow between them 27

Figure 11 the process flow diagram 28

Figure 12 The DRS rule file "nmos_rules.drs" scripted by the dynamic

script language and used in next file 38


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT iv

Figure 13 The NMOS template file written in the dynamic script language

(DTS) 38

Figure 14 A 2x2 Matrix arrangement with 0.1 micron horizontal distance

and 0.2 micron vertical distance 55

Figure 15 A 2x2 Matrix arrangement with 0.0 micron horizontal distance

and 0.0 micron vertical distance 56

Figure 16 A 2x2 Matrix arrangement with negative horizontal distance and

0.1 micron vertical distance. The consecutive fingers have common

contact array 56

Figure 17 The typical object oriented model of visual output of a

component 59

Figure 18 Bachus Naur representation of the GDSII stream 60

Figure 19 Flow Chart of the functionalities of F~CompSynth 63

Figure 20 The basic visual components of F~CompSynth marked in red

boundaries: A. The Editing Canvas, B. Menus, C. Layer Tool, D.

Toolbar and E. Component List. 66

Figure 21 Components: the first step of the 'Matching Wizard' 67

Figure 22 Component Fingers: the second step of the 'Matching Wizard' 68

Figure 23 Matching Simulator: the third and principal step of the 'Matching

Wizard' 69

Figure 24 Layout Info: the last step of the 'Matching Wizard' 72

Figure 25 The synthesized components in transparent rectangle mode 72


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT v

LIST OF TABLES

Table 1 Some layers used in CMOS VLSI process 11

Table 2 Format of dynamic script language, DTS base device template file37

Table 3 The real processing time of the implementation of the algorithm

"Single Symmery Row" over some data set 76

Table 4 Some tests of variable sized component synthesis 77

Table 5 Various result from various inputs of matching simulation 80

Table 6 Mathematical measurement of different arrangements of the

components 82

Table 7 Placement test of different input choices 83


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT vi

LIST OF ALGORITHMS

Algorithm 1 Inter-digitized Common Centroid 42

Algorithm 2 Cross Coupling 43

Algorithm 3 Common Centroid Symmetry 44

Algorithm 4 Single Symmetry Row 46

Algorithm 5 Average Dual 47

Algorithm 6 Parse 53

Algorithm 7 Evaluate 53

Algorithm 8 Iterate 54

Algorithm 9 Placement 57


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT vii

LIST OF EQUATIONS

Equation 1 Relation between device and mask layers 12

Equation 2 Measuring mismatches between two specific devices 13

Equation 3 The System Unit and Block Sets 29

Equation 4 The set of matching patterns 41

Equation 5 Mathematical Model of Analog Component Matching 48

Equation 6 Average Coordinate Position 49

Equation 7 Measurement of Symmetry 50

Equation 8 2-Dimensional disparity 51


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT viii

ACKNOWLEDGMENTS

At first I like to acknowledge and express gratefulness to Imdad-Sitara

Khan Foundation so that the research has been completed with the full

financial support and as one of the requirements of the fellowship

provided by this American foundation.

I wish to express sincere appreciation to my supervisor Syed Akhter

Hossain, Associate Professor, Department of Computer Science and

Engineering, East West University for his help in selecting the problem

area, helpful guidance, continuous back-up and ever observant supervision

during the total period of this study.

My co-supervisor, Mr. Didar Islam, CEO, Power IC Ltd. is the person to

whom I am grateful the largest part. All his aids are the bases of the

platform of the entire research work. Specially his help in finding particular

research matter as well as identifying base of solution and ever vigilant

direction with his big appreciations to my little exertions encourages me

most and brought swiftness in my accomplishments.

Special thanks to Professor Mozammel Haque Khan Azad, Professor,

Department of Computer Science and Engineering, East West University

for arranging the fellowship as well as his friendly and inspiring

consultation.

Mr. Md. Harun-ur-Rashid was my course teacher of the MS course

―Layout Synthesis and Optimization‖. Therefore, my basics on VLSI and

layout synthesis were totally built-up from his lectures and right directions.

I am very indebted to him.


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT ix

With the active inspiration of the above fellows, it is compulsion for me to

mention my career idol, A.S.M. Ameen Uddin, my maternal grandfather,

who is always harmonizing in my neurons from my childhood. I also

mention my parents, sister, grandparents, cousins, uncles (especially my

―Boro Mama-Mamee‖ - Dr. Md. Serajul Islam and Dr. Tasmin Akter) and

aunts for their passive but very important stimulation. I also remember my

late maternal grandmother, because she would be happiest with my

successes. The remote but most melodious accompanying of Farhana

Rakhy is the main cooler of my brain-processor. I always keenly want to

make them smiling with the inspiration of my achievements.

I also like to acknowledge Dr. Zahedul Hassan, PSO, BAEC for his so

hard effort to see me the best programmer, Dr. Shorif Uddin, Dept. of

CSE, Jahangirnagar University, who pour enormous endeavor to bring

maturity in my research activities, Mr. Ershad Haque Chowdhuri, Associate

Professor, Dept. of CSE, East West University, who often expresses his

willing to cooperate me in theoretical researches, and Mr. Enayetur

Rahman, Dept. of CSE, Darul Ihsan University, for his first lesson

regarding carrying research activities.

Thanks also to all the faculty members of Dept. of CSE, East West

University, Mr. Mohiuddin Panna and Mr. Md. Zakir Hossain, Power IC

Pvt. Ltd. for their continuous supply of resources with positive criticisms.

At last but not least I must thank Mr. Abdur Rashid, Nafisa Khanam

Siddika, Tithi Sarkar, my other course mates and all other well wishers.

They endlessly encouraged me that always cheer me up.


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT x

GLOSSARY

VLSI Very Large Scale Integration

DRC Design Rule Checker

MOS Metal Oxide Semiconductor

CMOS Complimentary Metal Oxide Semiconductor

DTS Dynamic Device Template Script

DRS Device Rule Script

Device Analog VLSI device like NMOS, PMOS, Resistor

Component Instance (may be of different sized) of Device

1 INTRODUCTION

C h a p t e r 1

IINNTTRROODDUUCCTTIIOONN


OF VARIABLE SIZED ANALOG AND DIGITAL VLSI COMPONENT 2

1. INTRODUCTION

Automation of ANALOG circuit design is likely to play a key role in the

design process of the next generation of mixed-signal integrated circuits

(ICs) and application specified integrated circuits (ASICs) (Martin, 2001).

In the digital domain, computer-aided design (CAD) tools are fairly well

developed and commercially available to the design community.

Unfortunately, the story is quite different on the analog side. Today, analog

circuits are still largely being handcrafted with only a SPICE-like simulation

shell and an interactive layout environment as the supporting facilities. Due

to the special and necessary constraints imposed on analog layouts (e.g.,

large variation of MOS transistor sizes, sensitivity to parasitic capacitance,

crosstalk, device matching, symmetry requirements, voltage drops, current

density, temperature gradients, piezoelectric effects, electromigration, etc.),

the analog layout design is intrinsically more difficult than its digital

counterpart (Gielen, et al., 2000). Due to technology scaling, the device

electrical properties worsen in analog circuits and the design window

decreases. Electrical parameters caused by different layout topologies with

geometrical parameters have already become necessary for high-

performance circuits even at the circuit design stage.

One of the parameters is the device matching (between same type device)

which impact only found at the IC testing, at the end of fabrication.

Mismatches occur from microscopic fluctuations in dimensions, doping,

oxide thicknesses, and other parameters that influence component values.

Although these statistical fluctuations cannot be entirely eliminated, their

impact can be minimized (Hastings, 2001). As a result, although analog

3 INTRODUCTION

circuits typically occupy only a small fraction of the total area of mixed-

signal ICs, their designs have become the bottleneck, both in design effort

and time, as well as test cost. Moreover, analog circuits are often

responsible for the design errors and the expensive design iterations.

Therefore, mismatching is very difficult to measure at design time but it

can be minimized through following some special design rules is

preferable. One crucial of the rules is splitting the larger components and

arranging the slices/segments of the components (finger) such that as

much mismatches as possible can be avoided. In literature and practical,

there are some topologies which are still very useful but fully manual.

So far, several CAD tools (Conway, et al., 1992) (Meyer zu Bexten, 1993)

(Bruce, et al., Feb) have been developed to automate the generation of

analog layouts. However, as some of these tools (such as (Conway, et al.,

1992), (Meyer zu Bexten, 1993), and (Rijmenants, et al., 1989)) are

developed for the analog devices synthesis at various stage but they were

not able provide automation to device matching. CADENCE, CALIBRE,

L-EDIT, etc. are very popular and strong VLSI CAD tools but still

automatic arrangement of the components‘ fingers is absent there. Some

researches have been carried out to model the mismatches (Shyu, et al.,

1984), (Shyu, et al., 1982), (McCreary, 1981) but the model can only be

applicable with the fabrication level parameters (areal and peripheral

fluctuations) and cannot be applicable to estimate the degree of matching

at the design time. Common centroid layout methodology is a very good

solution and there are few more matching patterns and rules to achieve

good matching (Hastings, 2001) but automation of these patterns or even

their algorithms are still absent in the literature. Even though this problem

has been addressed in KOAN/ANAGRAM II (Cohn, et al., 1994) and



LAYLA (Lampaert, et al., 1999), the construction of an entire analog layout

in these systems is based on manually drawn or fixed sized devices rather

than variable sized automatic matched layouts, which inevitably increases

the design complexity, especially for circuits with various different sized

devices.

To tackle the aforementioned problem, in this paper, it is demonstrating a

novel mathematical model to estimate a degree of device matching of a

specific matching pattern. Algorithm of some popular matching patterns

are proposed and implemented. Automatic placement of the layout of the

matched devices is implemented and a descriptive language, Device

Template Scripting (DTS) is designed for variable sized device synthesis to

create high-quality analog layouts. The designers also can construct layouts

made of these parameterized templates in a technology-independent

fashion.

Through the thesis, ‗Set theory‘ is used often for clear and concise

understanding of the components of the synthesis tools and their inter-

relationships in both the theoretical models and the implemented tools.

Referenced equations are labeled only to limit the total number of

equations and reduce unnecessary understanding and referencing overhead.

The rest of the paper describes the entire system in detail. Section II

surveys the previous work related to the layout automation, followed by

the introduction of the basic architecture and the layout synthesis flow of

the system in Section III. In the next sections, the consecutive phases of

layout synthesis are detailed one after the other. In particular, the technique

of device generation is explained in Section IV, the algorithms and data

structures used are shown in Sections V and the detail description of

5 INTRODUCTION

F~CompSynth is provided in Section VI, respectively. Section VII reports

the experimental results, and finally, the conclusions are drawn in Section

VIII.



C h a p t e r 2

PPRROOBBLLEEMM DDEESSCCRRIIPPTTIIOONN AANNDD PPRREEVVIIOOUUSS

WWOORRKKSS

7 PROBLEM DESCRIPTION AND PREVIOUS WORKS

2. PROBLEM DESCRIPTION AND PREVIOUS

WORKS

Before discussing the entire problem it is necessary to demonstrate the

analog and digital devices in the VLSI point of view and the mask layers.

They are important and the building blocks of integrated circuit. This

discussion is followed by the principal problem area and previous works

that influence the study of matching of VLSI devices.

2.1. Concept on Some Basic Devices

Below some basic devices are given with some important key points and

figures.

2.1.1. MOSFET (Metal Oxide Semiconductor Field Effect

Transistor)

Conductivity of a MOS can be changed by adding impurity. It is a voltage

controlled device. It is considered as a good switch also. Two types of

MOS are NMOS and PMOS. The figures and layer models are given

below.

• Layers of NMOS are N+ implantation, OD and poly silicon Gate

• Layers of PMOS are P+ Implantation, OD and poly silicon Gate



Figure 1 Layout Top-view of an NMOS and Identical NMOS Cross-section view (Courtesy by Power IC Pvt. Ltd.)

Figure 2 Layout Top-view of an NMOS and Identical NMOS Cross-section view (Courtesy by Power IC Pvt. Ltd.)

2.1.2. Resistances

The main purpose of resistance is to control the voltage of the device.

Several types of resistances are used:

1. Nwell Res. 2. Pwell Res.

3. Poly Res. 4. Metal Res.


2.1.3. Capacitors

Capacitors are used as the memory which can store current.

Several types of capacitor are used:

1. Oxide cap or MOS cap

2. Poly1-poly2 cap

3. Double poly-oxide cap or stack cap 3. Metal-metal cap

Figure 4 Symbol and top view of an oxide-cap (Courtesy by Power IC Pvt. Ltd.)

Figure 3 Typical symbol and layout view of a 3-pin PWELL res (Courtesy by Power IC Pvt. Ltd.)



2.1.4. Bipolar Transistors

3 types of bipolar transistors (BJT) are used.

1. Substrate PNP

2. NPN

3. Lateral PNP

Figure 5 NPN Transistor and Substrate PNP (Courtesy by Power IC Pvt. Ltd.)

2.1.5. Logic Gates

1. INVL

2. STRL (smith trigger logic)

3. NOR

4. NAND

5. TGL (Transmission gate logic)

2.2. CMOS Mask Layers

Different CMOS mask layers represent the presence of different materials

in an integrated circuit during CMOS process. GDSII is popular file format

for storing variety of architectural models. Layout data can be stored in

GDSII file. To store an element which belongs to an specific mask layer

requires a numeric value which represents the layer in GDSII file. The


GDSII file is directly acceptable as the fabrication input. Some layers are

not necessary for fabrication, but used to recognize differently by several

CAD applications. Some of the necessary layers for a CMOS process those

are also supported by GDSII standard are given in Table 1.

Short Name GDSII Layer No. Short Name GDSII Layer No.

TEXTREF 0 MET2_ID 24

OD 1 MET1_ID 25

NWELL 2 NW_ID 34

HVNW1 4 NBASE 28

PWELL 6 PW_ID6 33

POLY1 7 PW_ID2 36

POLY2 8 DPN 37

NIMP 9 NBASEZER 50

PIMP 10 LVNPN 51

CONT 11 LVPNP 52

METAL1 12 ELVSCR 82

VIA1 13 ELVNP 86

METAL2 14 ELVNPN 80

PAD 15 ESD_IMP 18

CAP 17 CAP_P2 16

VTLO 20 HR_P2_ID 32

RES_ID 23 LAT_PNP 58

Table 1 Some layers used in CMOS VLSI process

Different CMOS technology may use different layers. On the other hand

different devices require different set of layers. It can be expressed by

defining D, L, G and R such as,



𝑎) 𝐷 = 𝑑 | 𝑑 𝑖𝑠 𝑎 𝑑𝑒𝑣𝑖𝑐𝑒 [D is the set of all devices Di]

𝑏) 𝐿 = 𝑙 𝑙 𝑖𝑠 𝑎 𝑙𝑎𝑦𝑒𝑟 𝑠𝑢𝑝𝑝𝑜𝑟𝑡𝑒𝑑 𝑏𝑦 𝐺𝐷𝑆𝐼𝐼 𝑠𝑡𝑎𝑛𝑑𝑎𝑟𝑑}

[L is the set of all layers supported by GDSII standard]

𝑐) 𝑃 𝐿 [P is the subset of L]

𝑑) 𝑑 𝑃 [𝑑 implies 𝑃 that means 𝑃 is the requirements for 𝑑]

Equation 1 Relation between device and mask layers

For example, let the device 𝑑 is NMOS. In this case,

𝑃 = {𝑂𝐷, 𝑃𝑂𝐿𝑌 1, 𝑁𝐼𝑀𝑃, 𝐶𝑂𝑁𝑇, 𝑀𝐸𝑇𝐴𝐿 1}

The above mathematical expression states that for an NMOS the required

layers are fixed and they are Oxide, Polysilicon 1, Negative Implant,

Contact and Metal 1. The above statement is one of the principal platforms

of the thesis.

2.3. Matching Issues

Most integrated resistors and capacitors have tolerances of 20 to 30%.

These tolerances are much poorer than those of comparable discrete

devices, but this does not prevent integrated circuits from achieving a

high degree of precision matching. All of the devices in an integrated

circuit occupy the same piece of silicon, so they all experience similar

manufacturing conditions. If one component‘s value increases by 10%,

then all similar components experience similar increases. The ratio

between two similar components on the same integrated circuit can be

controlled to better than 1%, and in many cases, to better than 0.1%.

Devices specifically constructed to obtain a known, constant ratio are

called matched devices. A wide variety of analog circuits use matched

MOS transistors. Some circuits, such as differential pairs, rely on


matching of gate-to-source voltages, while others, such as current

mirrors, rely on matching of drain currents. The biasing conditions

required to optimize voltage matching differ from those required to

optimize current matching. One can optimize MOS transistors either for

voltage matching or for current matching. Matching is very important in

layout. Analog circuit works on matching actually. We never should

compromise in this issue wherever it is asked for unless the designer

allows. Equation 2 computes the mismatch of one specific pair of devices.

𝛿 = 𝑌2

𝑌1 −

𝑋2

𝑋1

𝑋2

𝑋1

=𝑋1𝑌2

𝑋2𝑌1

− 1

Equation 2 Measuring mismatches between two specific devices

Here, the intended values of the devices are X1 and X2. The measured

values are Y1 and Y2. The same measurement performed on a second pair

will yield a different mismatch. Measurements of a large number of device

pairs will produce a random distribution of mismatches. Average and

Standard deviation of mismatches are used to get a picture of overall

mismatches. Other equations of mismatch measurement are available in

(Hastings, 2001).

2.3.1. Causes of Mismatches

Systematic mismatches stem from various causes. Some of they are-

1. Random statistical fluctuations

2. Process biases

3. Contact resistances



4. Non-uniform current flow

5. Diffusion interactions

6. Mechanical stresses

7. Temperature gradients and a host of other causes.

Some special causes of MOS transistor mismatches are the geometric

effects (gate area, gate oxide thickness, channel length modulation and

orientation) and etch effects. A major goal of designing matched

components consists rendering them insensitive to various sources of

systematic error. A detail discussion on the effects and techniques for

combating them can be found in (Hastings, 2001).

2.3.2. Objective of Matching

As mismatching causes the reduction of efficiency of the integrated circuit,

minimizing its effect is very necessary. The objectives of device matching

is-

1. Reducing offset at input

2. Implement and assure ratio-metric design

3. Reduction of process variation of the same wafer & between lots to lot.

4. Uniform distribution of thermal effect.

2.3.3. Different Matching Issue

Gradient-induced mismatches can be minimized by reducing the distance

between the centroid of the matched devices. Some types of layout can

actually reduce the distance between the controids to zero. These

common-centroid layouts can entirely cancel the effects of long-range


variations as long as these are linear functions of distance. Some issues

regarding matching is followed up here-

2.3.3.1. Standard issue

1. Orientation (all device should be placed either horizontally or

vertically)

2. Placement (to place at closest distance)

3. Co-location (all nodes i.e. VDD, VSS or S/D from matched devices

should be one metal line)

Figure 6 MOS MN1, ND1, MN4, MN4 & MN5 with standard matching: 1. Diode ND1 at middle, 2. All MOS are on

same orientation and 3. All MOS are at minimum spacing (Courtesy by Power IC Pvt. Ltd.)

2.3.3.2. High- accuracy issue

1. Inter-digitization

2. Cross coupling

3. Same isothermal plane (i.e. equidistance from power device)

4. Common-Centroid

5. Separate & aloof from high voltage node.

6. Cross-cell matching.

2.3.4. Matching Pattern

It is assumed that the components to be matched have one or more

fingers. The type of arrangement of the fingers which has target to



establish a matching situation will be called matching pattern through the

entire thesis. Matching patterns are evolved from different philosophical

and experimental aspects. In general no concrete definition exists for

these patterns. Rather some heuristics has been applied based on

experiences in different cases to realize a pattern to meet the objectives

stated at Section 2.3.2.

Some matching patterns are widely used in VLSI device matching by

various layout designers and researchers. The patterns are evaluated from

the different matching issues of Section 2.3.3. It is important to keep in

mind that the objectives of all the patterns are common but used in

different considerations. It can be used for different VLSI devices. For

many ratios of the number of fingers of the matching components

different patterns may produce same result.

The patterns for matching device component arrays are often difficult to

construct, as it is not easy to satisfy all the rules of good matching. The

ultimate five basic rules for component matching (Hastings, 2001) are

discussed below.

2.3.4.1. Five Rules for Matching

a) Coincidence: The centroids of the matched devices should at

least approximately coincide. Ideally, the centroids should exactly

coincide.

b) Symmetry: The array should be symmetric around both the X-

and Y-axes. Ideally, this symmetry should arise from the

placement of segments in the array and not from the symmetry of


the placement of segments in the array and not from the

symmetry of the individual segments themselves.

c) Dispersion: The array should exhibit the highest possible degree

of dispersion; in other words, the segments of each device should

be distributed throughout the array as uniformly as possible.

d) Compactness: The array should be as compact as possible.

Ideally, it should be nearly square.

e) Orientation: Each matched device should consist of an equal

number of segments oriented in either direction; more generally,

the matched devices should possess equal chirality.

The most popular patterns those are modeled based on the rules given

above are given below:

2.3.4.2. Inter-digitization

The concept of Inter-digitization is to distribute the fingers of the

components one after another evenly. It is a one dimensional

arrangement. For example,

a) ABAB

b) ABCABCABC

c) AABAABAAB

A set of resistors which are arranged in inter-digitized pattern is shown at

Figure 8. Some times the pattern can be mutated to ABBA pattern for

symmetry and with dummy for some other reasons (Hastings, 2001).



2.3.4.3. Cross coupling

Cross coupling is the two dimensional version of inter-digitization. Here

no two fingers of same component are placed in consecutive position

horizontally or vertically. Therefore, their placement is visualized as

proper zigzag. Equal number of fingers is necessary for cross coupling.

For example,

a) ABABAB

BABABA

ABABAB

BABABA

b) ABCABCABC

BCABCABCA

A set of MOS which are arranged in cross-coupled pattern is shown at

the right side illustration of Figure 7.

2.3.4.4. Common-Centroid

The theme of common centroid pattern is to place the fingers of the

components in a two dimensional space so that they have a common

center and they are in symmetry along the equal dividing diagonal line

(2D Symmetric). For example,

a) AAA

ABA

AAA

b) ABA

BCB

ABA


c) A A B B B C C

D F D E D F D

C C B B B A A

2.3.4.5. Inter-digitized Common Centroid

It is a combination of Inter-digitized and Common Centroid patterns.

But the placements may not visualize in proper zigzag rather wave. The

inter-digitations patterns for common centroid MOS transistor arrays are

often difficult to construct (Hastings, 2001). This pattern obeys most of

the rules given at Section 2.3.4.1. Few examples of this pattern are

exampled in Figure 9.

2.3.4.6. Average Dual

In most of the cases it is necessary to match the fingers of only two

components in 2D plane. In this case sometimes, the above patterns

cannot be applied to place some combination of fingers that can

guarantee at least average distribution.

For example, let component ‗A‘ has 3 fingers and component ‗B‘ has 6

fingers. ‗Cross coupling‘ and ‗Inter-digitized Common Centroid‘ cannot

be applied because the numbers of fingers are not equal. Only ‗Common

Centroid‘ can be applied but the arrangement will be look like-

ABB BAB

BAB or BAB

BBA BAB

(a) (b)



None of the arrangement is fully satisfying because of their failure to

meet the objective no. 4 of Section 2.3.2. Rather the following

arrangement may be accepted as a better solution.

ABB

BBA

BAB

(c)

Here, it is guaranteed that each row and column will get as equal as

possible number of fingers of both the components and the inter distance

of the fingers of the same component will maximize. In this case,

symmetry is not considered as a major issue.

In this thesis, a pattern, Average Dual is proposed to meet the solution

stated above. The primary considerations of the ‗Average Dual‘ pattern

is-

a) Average distribution of the fingers of each component in the rows

as well as columns.

b) The variance of the average distances of the fingers of same

components should be maximal.

The above three arrangements meet the first consideration but only (c)

meets the second consideration. Another example is-

A A B A B A A A A B A A

B A A A is better than A B A A or B A A A

A A A B A A B A A A A B

A B A A A A A B A A B A


Figure 7 NPN with Common-centroid matching and MOS with Cross-coupled matching (Courtesy by Power IC Pvt.

Ltd.)

Figure 8 Resistances with inter-digitized matching (Courtesy by Power IC Pvt. Ltd.)



Figure 9 Sample interditization patterns for two dimensional common centroid arrays (Courtesy by Power IC Pvt. Ltd.)

2.4. Previous Work

With few exceptions, the existing analog layout synthesis tools (Conway,

et al., 1992) (Meyer zu Bexten, 1993) (Bruce, et al., 1996) apply a top-down

design approach that takes the already optimized circuit netlist as the

input and subsequently generates the layout. The use of procedural

generators is one of the most mature layout automation techniques used

for analog circuits. A major disadvantage of this technique, however, is

that the generators require considerable coding effort for each new

topology. Conway and Schrooten developed a template-driven analog

layout system (Conway, et al., 1992). Although this technique produces

good quality layout in a reasonable amount of CPU time, a template has

to be created for each new type of circuits, which limits its generality

because of the absence of grammar of template. However, the concept of


using template is very useful and the concept is extended to a dynamic

typed variable sized device synthesizer template construction.

Meyer zu Bexten et al. developed a successful rule-based analog layout

system called ALSYN (Meyer zu Bexten, 1993). The quality of the

resulting layout greatly depends on the quality of the rule set, which is

difficult to be formulated in a general context-independent manner. The

constructive technique proposed in (Bruce, et al., 1996) and (Mathias, et

al., Jan-1998), generates the analog layouts by mapping special design

constraints and features of an analog circuit into an effective

construction. However, a variety of interacting quality measures in the

analog layouts make it only suitable for the layout generation at the device

level, as opposed to the more desirable circuit level.

Algorithm-based tools can incorporate the analog layout knowledge into

the design flow. ILAC is a process-independent tool that automatically

generates layout for analog CMOS circuits (Rijmenants, et al., 1989). Its

placement is based on simulated annealing using slicing structures.

However, the direct incorporation of certain features from the digital

layout styles, e.g., the slicing style placement and the channel routing, into

the ILAC tool limits its ability to achieve high-quality dense and matched

analog circuit-level layouts.

Cohn et al. introduced KOAN-ANAGRAM II for analog device-level

layout automation (Cohn, et al., 1994). The flat Jepsen-Gelatt simulated

annealing model is used in its placer KOAN and ANAGRAM II is a line-

expansion router. A methodology for the automatic synthesis of full-

custom integrated circuit layout with analog constraints is presented.

Performance specifications are translated into lower-level bounds on



parasitics or geometric parameters using sensitivity analysis. The result is

naturally approaching a optimal solution but difficult to assure guarantee

or it will take much time. Lampaert et al. developed a performance-driven

analog layout tool LAYLA (Lampaert, et al., 1999). The performance

degradation associated with an intermediate layout solution is evaluated at

runtime using predetermined sensitivities. Similarly, simple module

generators are also employed in (Cohn, et al., 1994) and (Lampaert, et al.,

1999). The advantage of these tools is that they consider all the possible

geometry sharing optimizations during the placement. However, they

suffer from a few potential disadvantages. First, the modules used in

these tools are limited to non-optimal single devices, which tend to shift

the computation burden to the placement and the routing algorithms.

Secondly, the optimal solutions in the module generation step are

generally not easy to be made up in the subsequent placement and

routing stages. As a matter of fact, no matter how complex a placement

algorithm is, some structures (e.g., interdigital cascode structures (Bruce,

et al., Feb)) are very hard to be constructed using the geometry sharing

techniques. ALADIN (Zhang, et al., August 2006) is a very good layout

toolkit having its own module description language and various

functionalities for analog layout synthesis but lacks of having automated

matching process. Matching considerations has been brought to it but

still it requires some complex manual tasks. Popular matching patterns

are not included for automation. In (Bhattacharya, et al., 2004), an

algorithm to generate symmetry distribution of the components is

presented, but disparity is not provided, which is also important in

matching. Moreover, it doesn‘t discuss about algorithmic complexity that

is greater than O(N) in observation. Placement by neural network

modeling also consumes much time and doesn‘t provide highest accuracy.


From the discussion above it is easily understandable that there is

numerous research activities has been carried out and they are successful

and contributes from different point of views. However, a very important

key necessity in analog (as well as digital and mixed) layout design,

matching between components (i.e. devices), as an implemented form is

still absent, which, till now leads difficulties in matched device layout

synthesis. Now it is a quite obvious to develop algorithms to simulate and

synthesize the arrangements in a specified pattern like given in (Hastings,

2001). The aforementioned problems have motivated us to develop a

novel analog layout synthesis tool—F~CompSynth. This tool introduces

a flexible strategy of module generation to allow layout designers to

construct matched devices modules in a technology and application-

dependent fashion. The knowledge, experiences and automated

suggestions, thus, can be readily represented in the generated layouts.

Moreover, since the proposed placement or matching algorithms in

F~CompSynth are designed based on modules rather than single devices,

this tool can be further expanded to synthesize the layout of a larger

analog circuit/system following a hierarchical design methodology.



C h a p t e r 3

BBAASSIICC AARRCCHHIITTEECCTTUURREE AANNDD SSYYNNTTHHEESSIISS FFLLOOWW

27 BASIC ARCHITECTURE AND SYNTHESIS FLOW

3. BASIC ARCHITECTURE AND SYNTHESIS

FLOW

In this chapter the basic architecture and the process flow diagram and

relation between them are discussed.

3.2. Component Block Diagram

The entire system consists of four major components those are illustrated

in Figure 10. A general system usually consists of ‗Input‘, ‗Process‘ and

‗Output‘. Unlike the general case, this system includes an additional unit

that is ‗Pre-Input‘. This is a unit which can be done by manual script

writing. An auxiliary tool for template drawing and template file generator

can be used in this unit. ‗Input‘ simply indicates to select the required

abstract device by choosing specific device template file, entering the

required parameters (length and width) and the matching type. ‗Process‘

unit covers synthesize of the file by interpretation of the script, cross

matching of the components and placements. ‗Output‘ unit is nothing

more but only representing the device graphically and export it to GDSII

file format.

Figure 10 four major components and information flow between them



3.3. Process Flow

In particular, the process flow diagram of the proposed and developed

system is depicted in Figure 11.

Figure 11 the process flow diagram

‗Template Drawing‘ is a process where an interactive tool is used to draw

templates of devices. The template can be considered as an abstract device

also. ‗Template Processing‘ processes to convert the drawn objects into a

description that defines the polygons‘ relative positions and sizes. ‗Device

Template Generation‘ is a process that generates a file for a device. This

file is considered as the template. The file can be written manually also.

This file should be written in a description language that is discussed later.

‗Selection of Device‘ indicates user action to select a device template file

for implementation through parameterization that is indicated as ‗Input the

Parameters‘. ‗DRC Rule Checking‘ is not always necessary for concern

users. But it is integrated to avoid design errors. ‗2-D Rectangular Object

Graph‘ is necessary for actual representation of the device. This is the

29 BASIC ARCHITECTURE AND SYNTHESIS FLOW

actual synthesize time. ‗Visual Representation‘ is necessary for realizing

what is synthesized and how the chip will be looked. ‗Export to GDSII

File‘ is necessary for converting the device information into GDSII file

format for global use. ‗GDSII‘ file is the portable file type that is used by

commercial industries mostly.

The relation between major components and the process flows are like

this,

𝑎) 𝐶 = {𝑃𝑟𝑒 − 𝐼𝑛𝑝𝑢𝑡, 𝐼𝑛𝑝𝑢𝑡, 𝑃𝑟𝑜𝑐𝑒𝑠𝑠, 𝑂𝑢𝑡𝑝𝑢𝑡}

Let, Pi is a process unit shown at Figure 11 and ‗i‘ is the number of a

process.

𝑏) 𝑃𝑟𝑒 − 𝐼𝑛𝑝𝑢𝑡 = {𝑃1}

𝑐) 𝐼𝑛𝑝𝑢𝑡{ 𝑃2 , 𝑃3, 𝑃4, 𝑃5 , 𝑃6 , 𝑃2 , 𝑃4 }

𝑑) 𝑃𝑟𝑜𝑐𝑒𝑠𝑠 = 𝑃7 , 𝑃8 , 𝑃9, 𝑃10

𝑒) 𝑂𝑢𝑡𝑝𝑢𝑡 = 𝑃11 , 𝑃12

Equation 3 The System Unit and Block Sets



C h a p t e r 4

DDEESSIIGGNN OOFF AALLGGOORRIITTHHMMSS AANNDD DDAATTAA

SSTTRRUUCCTTUURREESS

31 DESIGN OF ALGORITHMS AND DATA STRUCTURES

4. DESIGN OF ALGORITHMS AND DATA

STRUCTURES

In this chapter the designed and implemented algorithms with necessary

data structures in the process units illustrated in Figure 10 will be

demonstrated. For a clear understanding the Set representations of the

components are provided where necessary.

4.2. Pre-Input

Actually the Pre-Input unit is the most complex unit. The main purpose is

to write device template file using a description language. This unit is called

Pre-Input in the sense that for a single template this phase will be used

once and the stored templates can be implemented several times to

generate different size of devices.

4.2.1. Device Template Scripting

A device template file format is designed so that dynamic length and width

based devices can be generated. Writing script with a particular language

that supports the format is the goal of the component ‗Pre-Input‘.

A language, ―Device Template Script‖ (DTS) for device template has been

evolved that is one kind of script language. It is chosen because of its

dynamicity in typing and strict rule based script language. The possibility of

typos and runtime error is very less in using this script language, because

the scope of the language is very limited and only applicable to this

purpose. The main features of this language are as follows:



Object Base Scripting

o Numeric Object

8 Byte Integer or 8 Byte double precision floating point

numeric values supported. For example,

x = 2

POLYa.L = 0.5

o Rectangle Object

Polygon masks at different CMSO layers are the main

platform of a layout. A polygon can be easily constructed

with different rectangles. Number of properties of a

rectangle is less than that of a polygon. Therefore, writing

rectangle data is more atomic. The properties of a rectangle

are GDSII layer (N), left (L), right (R), top (T) and bottom

(B). For example,

NIMPa.N = 9

NIMPa.L = ODa.L - OD_IN_NIMP

NIMPa.R = ODa.R + OD_IN_NIMP

NIMPa.T = ODa.T - OD_IN_NIMP

NIMPa.B = ODa.B + OD_IN_NIMP

o Rectangle Array Object

Array of a rectangle is inherited from Rectangle object. It

represents a collection of rectangles at same layer having


similar size (W), fixed interval or spacing (S) in placement,

array orientation (A) and dynamic number of elements.

Orientation may be Horizontal (1), Vertical (2) or Both (3).

Number of elements is dynamically defined based on

properties of other objects.

CONTb.W = CONT_WIDTH

CONTb.S = CONT_SPACE

CONTb.A = 2

o File Object

For device layout, it is often necessary to use particular

technology. For different technology, internal width of a

mask, different type of distances between masks, etc. may

vary. It is also necessary to use one technology in

synthesizing layouts of different devices, which is stated in

Equation 1. File object facilitates inclusion of ―Device Rule

Script‖ (DRS) file, a variation of DRC rule set. For example,

ruleFile = "NMOS_Rules.drs"

o Input Object

Some time it is necessary receive and use parameters from

environment. Input object is written as,

L = INPUT

W = INPUT



Two types of source are supported. The keyword, ―INPUT‖

is replaced with the values supplied from the sources. The

sources are,

Soft source

Soft source means ‗comma‘ seperated passed

arguments with the inclusion of a DTS file. The

application order of the parameters is as of the

corresponding arguments‘ order. For example,

ruleFile = "NMOS.dts", 2.6, 5.5

Hard source

Hard source is due to absence of arguments with the

DTS file inclusion. In that case, an input dialog box

is appeared to the user during its application. It is

hardware passed (keyboard, etc.) argument. For

example,

ruleFile = "NMOS.dts"

Dynamically Managed Typing

The script writer doesn‘t need to declare the type of the variables.

At the first use of a variable, the types of the objects are

automatically defined by the interpreter during parsing. If it is used

later differently, the type will be dynamically changed. For example,


Abc = 5 //The type of Abc is Integer

Abc = 10.5 //The type is changed to Double

Abc.L = Abc//The type is changed to Rectangle

Strict Rule base

Different type of object must be used in different rules. Such as,

filename must be double quoted, rectangle object must be used

along with a property at a time, etc.

Object Orientation

Though all the object oriented features are not supported in a

conventional way as like other OO programming languages does,

but through file inclusion it can be partially supported.

o Abstraction

A DTS file which contains only the rectangle objects and

rectangle array objects with their GDSII layers can be

considered as an abstract device.

o Inheritance

A DTS file which contains one or more DTS files as parent

devices and enhance them with modify or addition of more

objects can be considered as Inheritance.

o Polymorphism

A DTS file inclusion with different number of arguments

may be considered as polymorphism.



o Objects and Properties

A DTS file with full description of a device is considered as

a device object. The properties of the objects are the

rectangles and rectangle arrays.

Iteration

Iteration is supported in the sense that, arrays of rectangle objects

are featured as mentioned above. But this doesn‘t meant supporting

of conventional loops (for loop, while loop, etc.).

Arithmetic Operations

Four types of basic operations are supported. They are addition,

subtraction, multiplication and division.

DRC Rule Set file

The DRC rule set file must be defined by this dynamic language

also. This file should contain only variables assignment with

constant values.

The dynamic file format of DTS file, which is implemented in this thesis, is

described in Table 2.


Line Format Description

TEMPLATE <HEADER> ‗\n‘ <DATA>

Symantec: The header followed by the data

HEADER ‗//‘ [File Version] ‗,‘ [Creation Date]

Symantec: File version followed by creation date (optional)

DATA {<LINE> ‗\n‘}+

Symantec: A set of text line

LINE {<FILE>|<VARIABLE>|<RECT

DATA>|<INPUT>}

Symantec: A file inclusion, a variable or a rectangle data

RECT DATA [Rectangle name] ‗:‘ <PROPERTY> ‗=‘ <VALUE>

Symantec: set value to a property of a Rectangle

PROPERTY [‗L‘ | ‗R‘ | ‗T‘ | ‗B‘ | ‗N‘ | ‗W‘ | ‗S‘]

Symantec: indicates left, right, top, bottom, GDSII layer, etc.

VALUE [Constant | <EXPRESSION>]

Symantec: a double value or an iteration for a set of objects

INPUT <VARIABLE> ‗= INPUT‘

Symantec: get value from user for length and width

VARIABLE {‗A‘ – ‗Z‘ | ‗a‘ – ‗z‘ | ‗0‘ – ‗9‘ | ‗ ‘}+

Symantec: A series of alphanumeric characters including space

FILE [Rectangle name] ‗=‘ ‗‖‘ [File path] ‗‖‘ {‗,‘ Constant}*

Symantec: Parsing of the file before going to next line and

include all objects of the file in the current file. Specially

necessary for include DRC rule set for an specific technology

EXPRESSION [<VARIABLE > <OP> < EXPRESSION > |

<VARIABLE > ]

Symantec: a variable or set of variables with operators

OP [ ‗+‘ | ‗-‘ ]

Symantec: operators are limited to add (+) and sub (-)

Table 2 Format of dynamic script language, DTS base device template file



Below two figures are given as sample of DRS (Device Rule Script) file

consists of DRC rules set requires for NMOS and a DTS file for NMOS

template.

CONT_OUT_POLY = 0.4

CONT_WIDTH = 0.5

CONT_IN_OD = 0.3

OD_IN_NIMP = 0.4

CONT_SPACE = 0.5

FILE = "NMOS_Rules.drs"

L = INPUT

W = INPUT

POLYa.N = 7

ODa.N = 1

NIMPa.N = 9

CONTa.N = 11

CONTb.N = 11

POLYa.L = 0

POLYa.R = POLYa.L + L

ODa.T = 0

ODa.B = ODa.T + W

POLYa.T = ODa.T - POLY_OUT_OD

POLYa.B = ODa.B + POLY_OUT_OD

CONTa.R = POLYa.L - CONT_OUT_POLY

CONTa.L = CONTa.R - CONT_WIDTH

CONTa.T = ODa.T + CONT_IN_OD

CONTa.B = ODa.B - CONT_IN_OD

CONTb.L = POLYa.R + CONT_OUT_POLY

CONTb.R = CONTb.L + CONT_WIDTH

CONTb.T = CONTa.T

CONTb.B = CONTa.B

ODa.L = CONTa.L - CONT_IN_OD

ODa.R = CONTb.R + CONT_IN_OD

NIMPa.L = ODa.L - OD_IN_NIMP

NIMPa.R = ODa.R + OD_IN_NIMP

NIMPa.T = ODa.T - OD_IN_NIMP

NIMPa.B = ODa.B + OD_IN_NIMP

CONTa.W = CONT_WIDTH

CONTa.S = CONT_SPACE

CONTa.A = 2

CONTb.W = CONT_WIDTH

CONTb.S = CONT_SPACE

CONTb.A = 2 + POLY_OUT_OD

Figure 13 The NMOS template file written in the dynamic script language (DTS)

Figure 12 The DRS rule file "nmos_rules.drs" scripted by the dynamic script language and used in next file


4.3. Input

Inputs of the system are the device name (d), two parameters – Length (l)

and Width (w) defined at Table 2 in ‗INPUT‘, number of fingers of the

components (p) and the matching pattern (m). It can be expressed by –

𝐼 = 𝑑, 𝑙, ℎ, 𝑝, 𝑚 𝑑 ∈ 𝐷 ⋀ 𝑚 ∈ 𝑀 ⋀ 𝑙, 𝑤 ∈ ℕ ⋀ 𝑝 ∈ 𝑁}

Here, 𝑁 is the set of natural numbers.

4.3.1. Device Name

Device name can be chosen from either template file or from a complex

database of device templates. In the implementation, choose from template

file is used for flexibility. Theoretically it can be expressed as,

𝐹 = 𝑓 𝑓 𝑖𝑠 𝑎 𝑑𝑒𝑣𝑖𝑐𝑒 𝑡𝑒𝑚𝑝𝑙𝑎𝑡𝑒 𝑓𝑖𝑙𝑒}

𝐵 = 𝑏 𝑏 𝑖𝑠 𝑎 𝑑𝑒𝑣𝑖𝑐𝑒 𝑜𝑓 𝑡𝑒𝑚𝑝𝑙𝑎𝑡𝑒 𝑑𝑎𝑡𝑎𝑏𝑎𝑠𝑒}

𝐷 = 𝑑 𝑑 ∈ 𝐹 ⋁ 𝑑 ∈ 𝐵}

4.3.2. Number of Components and their Name

In this step, number of components to be matched is received. In addition,

their name is also received to show as label for identifying at output.

Let C be the set of components. Therefore, number of components,

𝑁𝑐 = |𝐶|. The names of the components can be expressed by 𝑛𝑎𝑚𝑒𝑐 .



4.3.3. Length and Width

Input parameters ‗Length‘ and ‗Width‘ are taken by an input dialog box.

They are often called unit length (𝑙𝑢 ) and unit width (𝑤𝑢 ). In manual

scripting it is also possible to define more than two parameters. It is a great

flexibility of the dynamic scripting used in template generator.

4.3.4. Number of Fingers of the Components

Generally, matching is performed between differently sized components.

Virtually there exists a unit sized component, where other sizes of the

components are multiple of the unit size.

Let C be the set of components and ℕ is the set of numbers of fingers of

the components. Relation between unit size (𝑠𝑢 ) and number of fingers

(𝑛𝑐) of the components can obtain by

𝑠𝑐 = 𝑛𝑐𝑠𝑢 ,𝑤ℎ𝑒𝑟𝑒 𝑐 ∈ 𝐶 ⋀ 𝑛𝑐 ∈ ℕ

𝑛𝑐 can be obtain also from the total size of a component. Let the size of a

component 𝑠𝑐 be composed of length ( 𝑙𝑐 ) and width ( 𝑤𝑐 ) of the

component c.

𝑠𝑐 = 𝑙𝑐 , 𝑤𝑐 , 𝑤ℎ𝑒𝑟𝑒 𝑙𝑐 ∈ 𝐿 ⋀ 𝑤𝑐 ∈ 𝑊

𝑙𝑢 = 𝐺𝐶𝐷 𝐿

𝑤𝑢 = 𝐺𝐶𝐷 𝑊

𝑛𝑐 =𝑙𝑐

𝑙𝑢 ×

𝑤𝑐𝑤𝑢

)


4.3.5. Matching Pattern

The matching patterns implemented in this thesis are –

1. Inter-digitization Common Centroid

2. Cross coupling

3. Common Centroid Symmetry

4. Single Row Symmetry

Mathematically it can expressed as -

𝑀 = {𝑖𝑑, 𝑐𝑝, 𝑐𝑐, 𝑠𝑦𝑚}

Equation 4 The set of matching patterns

Here M is the set of the supported matching patterns. id represents ‗Inter-

digitization Common Centroid‘, cp represents ‗Cross-coupling‘, cc

represents ‗Common Centroid Symmetry‘ and sym represents ‗Single Row

Symmetry‘.

4.4. Process

The process unit is the heart of a system. From the Equation 3 at Section

3.3, the full process unit of this system is composed of four sub-units or

functions. They are discussed below.

4.4.1. Matching of the Components

As stated in Equation 4 of Section 4.3.5, the implemented matching

patterns are inter-digitization, cross coupling, common centroid and single

row symmetry. The algorithms of the matching patterns are illustrated

below. We should note that, in all the cases the common inputs are the

placement matrix size (R and C) with the number of fingers of the



components (ℕ) and output is a matrix (𝕄) which contains the identities

of the fingers arranged as the specified pattern. Here, identity of a finger is

the serial number of the corresponding component. All the discussions

about matching issues and matching patterns are given at Section 2.3. Here

only proposed algorithms, which are implemented, are mentioned.

4.4.1.1. Inter-digitized Common Centroid

Algorithm Inter-digitized Common Centroid

Input: ℕ (Vector) – Set of numbers of fingers of the components

ROW (Integer) – Number of rows

COL (Integer) – Number of columns

Output: 𝕄 (Matrix) – Placement matrix of ROW rows and COL columns

1. If COL is a prime number Return Single Symmetry Row (ℕ)

2. If 𝐺𝐶𝐷(ℕ) = 1 Then Return Common Centroid Symmetric (ℕ, ROW, COL)

3. 𝔸, 𝔹: Smallest Vector of length greater than 2 and factor of COL

4. 𝕟i = ℕi/(ROW × (COL/|𝔸|))

5. 𝔸 = Single Symmetry Row (𝕟)

5. 𝔹i = |ℕ| − 𝔸i + 1

6. ℂ, 𝔺: A row vector of length COL

7. ℂ = {𝔸, 𝔹, 𝔸, 𝔹, ⋯ }

8. 𝔺 = {𝔹,𝔸, 𝔹, 𝔸, ⋯ }

9. 𝕄 =

𝔸

𝔹𝔸⋮𝔸𝔹

𝔸

10. Return 𝕄

Algorithm 1 Inter-digitized Common Centroid


The time complexity of the above algorithm is O(N), where N = the

number of total fingers. The worst case memory complexity is O(2N),

where N = Number of cells in 𝕄 + ℕ and Number of cells in 𝕄 = |ℕ|.

4.4.1.2. Cross coupling

Algorithm Cross Coupling





1. l = 0

2. For i = 0 to ROW

3. k = l

4. For j = 0 to COL

5. If k = |ℕ| Then

6. k = 0

7. If ℕk > 0 Then

8. 𝕄i,j = k

9. ℕk = ℕk − 1

10. k = k + 1

11. l = l + 1

12. If l = |ℕ| Then

13. l = 0

14. Return 𝕄

Algorithm 2 Cross Coupling

The time complexity of the above algorithm is O(N), where N = ROW

COL = = ℕ, that is the number of total fingers. The worst case memory

complexity is O(2N), where N = Number of cells in 𝕄 + ℕ .



4.4.1.3. Common Centroid Symmetry

Algorithm Common Centroid Symmetry





1. 𝕊 = Single Symmetry Row (ℕ)

2. If 𝕊COL = 𝕊COL +1 Then Change = false

3. Else Change = true

4. Direction = Right

5. k = 1

6. For i = 0 to ROW

7. If Direction = Right Then

8. For j = 0 to COL

9. 𝕄i,j = 𝕊𝑘

10. k = k + 1

11. If Change = true Then Direction = Left

12. Else

13. For j = COL to 0 in reverse direction

14. 𝕄i,j = 𝕊𝑘

15. k = k + 1

16. Direction = Right

17. Return 𝕄

Algorithm 3 Common Centroid Symmetry

The time complexity of the above algorithm is O(N), where N = ℕ =

ROW COL, that is the number of total fingers. The worst case memory

complexity is O(2N), where N = Number of cells in 𝕄 + ℕ and Number

of cells in 𝕄 = ℕ.


4.4.1.4. Single Symmetry Row

Algorithm Single Symmetry Row

Input: ℕ (Vector)

Cells (Integer): Length of ℝ

Output: ℝ (Vector) : length is ‘Cells’

1. Counter: Vector of length ‘Cells’

2. Max = ℕ / Cells

3. Full = 0

4. For k = |ℕ| − 1 to 0 Backward

5. Probability = Carry = ℕk / (Cells - Full)

6. If ℕk > 1 And (Cells – full) Mod ℕk = 0 And (Cells – full) / ℕk > 1 Then

7. i = 1

8. len = Ceil((Cells)/2-1)

9. While i <= len And len > 1

10. While i <= len And Counter i = max

11. i = i + 1

12. Mantissa = Round (Carry)

13. Carry = Carry – Mantissa + Probability

14. ℝi = k

15. ℝCells −i+1 = k

16. Counter i = Counter i + Mantissa

17. Counter (Cells – i + 1) = Counter(Cells – i + 1) + Mantissa

18. i = i + 1

19. While i < len And Counter i = max

20. i = i + 1

21. If ℕk Mod 2 = 1 Then

22. ℝi = k

23. Counter i = Counter i + 1

24. Else



25. i = 0

26. While i < Cells

27. While i < Cells And Counter i = max

28. i = i + 1

29. Mantissa = Round (Carry)

30. Carry = Carry – Mantissa + Probablity

31. If i < Cells Then

32. ℝi = k

33. Counter i = Counter i + Mantissa

34. i = i + 1

35. For all Cells

36. Full = Number of ‘Max’ filled in Counter

37. Return ℝ

Algorithm 4 Single Symmetry Row

The time complexity of the above algorithm is O(N), where N = ℕ, that

is the number of total fingers. The worst case memory complexity is

O(2N), where N = Cells + ℕ And Cells = ℕ.

4.4.1.5. Average Dual

Algorithm Average Dual





1. X: Vector of length ℕ0

2. Y: Vector of length ℕ0

3. x_capacity = Capacity Distribute (ℕ, COL)

4. y_capacity = Capacity Distribute (ℕ, ROW)

5. i = 0


6. ind = 0

7. Do while i < |X|

8. If x_capacityind > 0 Then

9. x_capacityind = x_capacityind – 1

10. Xi = ind

11. i = i + 1

12. ind = ind + 2

13. If ind >= |x_capacity| Then

14. If ind is even number Then

15. ind = 1

16. Else

17. ind = 0

18. i = 0

19. ind = 0

20. Do while i < |Y|

21. If y_capacityind > 0 Then

22. y_capacityind = y_capacityind – 1

23. Yi = ind

24. i = i + 1

25. Else

26. ind = ind + 1

27. For i = 0 to ROW and j = 0 to COL 𝕄i,j = 0

28. For i = 0 to |X|

29. 𝕄Xi ,Yi= 1

30. Return 𝕄

Algorithm 5 Average Dual

The time complexity of the above algorithm is O(N), where N = ℕ0 + ℕ1 ,

that is the number of total fingers. The worst case memory complexity is

O(N+ROW+COL) = O(2N), where N >= ROW+COL.



4.4.2. Mathematical Model for Analog Device Matching

Prediction

In literature, no mathematical model of prediction of matching has been

found. It means that there is no mathematical model which can predict

how good matching an arrangement could approach. Therefore, a

mathematical model of matching of VLSI components is proposed in this

thesis based on some characteristics of the placement matrix (average

positioning (A), symmetry (S) and disparity (D)) stated at Section 2.3.4

which have negative or positive impact on the overall matching of the

components. It is easy to understand mismatch, which has negative relation

to matching. Therefore, the rate of matching,

𝑃 = 𝑓 𝑓 𝐴 , 𝑓 𝑆 , 𝑓 𝐷

The equation given below is evaluated by positive and negative impacts

and weights (or priority) that must be a subject to tune to a better shape.

Single layer artificial neural network is a good way to get the weights.

Let ‗Point (P)‘ be the weight of mismatching. Therefore, negation of Point

indicates matching. More negative value means better matching. The input

is the placement matrix ‗M‘ and the number of fingers or the set of

multiples of the component ‗N‘. Point P can be calculated from,

𝑃 = 𝐴 × 𝑊𝑎 + 𝑆 × 𝑊𝑠 − (𝐷 × 𝑊𝑑) 𝑊ℎ𝑒𝑟𝑒 𝑊𝑎 ≫ 𝑊𝑠 > 𝑊𝑑

Equation 5 Mathematical Model of Analog Component Matching

Below definition of ‗A‘, ‗S‘ and ‗D‘ is given. C is the set of components and

|C| is the number of components. Ci is the set of the fingers of the

component i.


4.4.2.1. Average 2-Dimensional Placement

𝐴𝑥𝑖 =

𝑥𝑖𝑗

|𝐶𝑖|𝑗 =1

|𝐶𝑖|

𝐴𝑦𝑖 =

𝑦𝑖𝑗

|𝐶𝑖 |𝑗 =1

|𝐶𝑖 |

𝐴 =

(𝐴𝑥

𝑖 − 𝐴𝑥 |𝐴𝑥 |𝑖=1 )2

|𝐴𝑥 |+

(𝐴𝑦𝑖 − 𝐴𝑦 |𝐴𝑦 |

𝑖=1 )2

|𝐴𝑦 |

/2

Equation 6 Average Coordinate Position

Proof:

𝑥𝑖𝑗 [y instead of x] is the horizontal [vertical] matrix position of a finger j of

the component i. 𝑥𝑖𝑗

|𝐶𝑖|𝑗=1 [y instead of x] is the summation of the

horizontal [vertical] position. Therefore, 𝐴𝑥𝑖 [y instead of x] is the average

horizontal [vertical] position of fingers of each component i.

𝐴𝑥𝑖 − 𝐴𝑥 2 𝐴𝑥

𝑖=1 /|𝐴𝑥| [y instead of x] is the standard deviation of the

components‘ average horizontal [vertical] positions. Therefore, A is the

average of horizontal and vertical standard deviation.

4.4.2.2. Measurement of Symmetry

For |M| = 1,

𝑆 = 𝑀1,𝑗 − (𝑀1, 𝑀1 −𝑗 +1)

𝑀1 /2

𝑗 =1



For |M| = 2,

𝑆 = 𝑀1,𝑗 − ( 𝐶 − 𝑀 𝑀 −1+1, 𝑀1 −𝑗 +1 + 1)

𝑀1

𝑗 =1

For |M| > 2,

𝑆 = 𝑀𝑖,𝑗 − 𝑀 𝑀 −𝑖+1, 𝑀𝑖 −𝑗 +1

𝑀𝑖

𝑗 =1

𝑀 /2

𝑖=1

Equation 7 Measurement of Symmetry

Proofs:

M is the placement matrix. 𝑀 is the number of row and 𝑀𝑖 is the

number of column. 𝑀 /2 is the mid vertical position. 𝑀𝑖,𝑗 is the

numeric representation or numeric value of the finger at the 𝑖𝑡ℎ row and

𝑗𝑡ℎ column. ( 𝑀 − 𝑖 + 1)𝑡ℎ row is the opposite row of 𝑖𝑡ℎ of the matrix

M and ( 𝑀𝑖 − 𝑗 + 1)𝑡ℎ column is the opposite or reverse column of 𝑗𝑡ℎ

column. 𝑀 𝑀 −𝑖+1, 𝑀𝑖 −𝑗+1 is the element at the 2 dimensional reverse

position of the position 𝑀𝑖,𝑗 in the matrix M. Reverse component finger at

the 2- dimensional reverse position of the component finger 𝑀𝑖,𝑗 is

( 𝐶 − 𝑀 𝑀 −𝑖+1, 𝑀𝑖 −𝑗+1 + 1). Subtraction between same elements at a

position and its 2 dimensional reverse position only produces the result

zero. Other than zero every result is positive and therefore the summation

never decreases and indicates the asymmetry of matrix. Thus less value of S

always ensures better symmetry. For the single row matrix, horizontal

symmetry ensures the symmetry of the entire matrix. In the case of double

rowed matrix, for a very good matching of analog component, it is obvious

to find reverse component symmetry. For other case, 2-dimensional

symmetry is required.


4.4.2.3. 2-Dimensional Disparity

Disparity indicates how far an element is placed from its required position.

To cancel the effect of the cancellation of a positive value by a negative

value at the summation, the entire difference value is squared.

𝑉𝑥𝑖 =

(𝑥𝑖𝑗−

( 𝑀𝑖 𝑚𝑜𝑑 |𝐶𝑖|) × 𝑥𝑖𝑗

|𝑀𝑖|+

12 )2|𝐶𝑖 |

𝑗=1

|𝐶𝑖|

𝑉𝑦𝑖 =

(𝑦𝑖𝑗−

( 𝑀 𝑚𝑜𝑑 |𝐶𝑖|) × 𝑦𝑖𝑗

|𝑀|+

12 )2|𝐶𝑖 |

𝑗=1

|𝐶𝑖|

𝐷 =1

𝐶 ((𝑉𝑖

𝑥 − 𝑉𝑥 )2 + 𝑉𝑖𝑦− 𝑉𝑦

2)

𝐶 −1

𝑖=1

Equation 8 2-Dimensional disparity

Proofs:

𝑀𝑖 𝑚𝑜𝑑 |𝐶𝑖| [ 𝑀 instead of 𝑀𝑖 ] means the effective number of

horizontally [vertically instead] dispersed fingers. In each case number of

fingers equal to number of columns [rows instead] will be distributed

horizontally [vertically instead] evenly and their disparity is 0. 𝑎 +1

2

indicates the nearest integer of 𝑎 (round). 𝑉𝑥𝑖 [y instead of x] is horizontal

[vertical] disparity of the fingers of the component Ci . ((𝑉𝑖𝑥 − 𝑉𝑥 )2 +

(𝑉𝑖𝑦− 𝑉𝑦 )2) is the 2 dimensional disparity or sum of horizontal and

vertical disparity of the variance of the component Ci . D is the 2-

dimensional disparity of the components‘ fingers placements.



4.4.3. Component Synthesis

In the process unit, the second functionality is to create necessary instances

(fingers of components) of the implemented device. The size of each

instance should be equal to the unit size ( 𝑠𝑢 ). The number of total

instances is, N = 𝑛𝑐 . Here, an instance represents a finger of a

component.

The processes are completed by parsing the template file. Two auxiliary

functions are used by the process Parse. The algorithms are given at

Algorithm 6 Parse, Algorithm 7 Evaluate, and Algorithm 8 Iterate.

Algorithm Parse

Input: T (Template)

D (Data Hash Table)

P (Parameters)

Output Component

1. H: new Hash table of String to Rectangle

2. If D is EMPTY Then D: new Hash table of String to Numeric

3. For L = each line of T

4. Let L can be decoded as ID = EXP

5. If EXP is a File Inclusion Then

6. Split EXP into File Name and Parameters (May be EMPTY)

7. Parse (File Name, D, Parameters)

8. Else If EXP is ‘INPUT’ Then

9. If p < |Parameters| Then

10. VAL = Parametersp

11. p = p + 1

12. Else

13. VAL = Get input as parameter from user

14. Else If EXP is a constant Then VAL = EXP


15. Else If EXP is not a constant VAL = Evaluate (D, EXP)

16. Put an entry (ID, VAL) in D

17. If ID contains ‘.’ Then

18. It can be separated as RECT.PROP

19. If RECT doesn’t exists in H Then

20. Add an entry (RECT, rectangle object) in H

21. Get the rectangle object and assign it’s the property PROP to VAL

22. For all RECT in H which are Iteration supported

23. Iterate (RECT, H)

24. Return Component = Instance made from rectangles of H

Algorithm 6 Parse

Algorithm Evaluate

Input: D: Data Hash Table

E: Expression

Let OP be ‘+’ or ‘-’

From left to right of E, Find the first occurrence of OP

If an OP is not found Then Return value of E in D

If an OP is found Then separate E as X OP Y

If OP is ‘+’ Then Return value of X in D + Evaluate (Y)

If OP is ‘-’ Then Return value of X in D - Evaluate (Y)

End

Algorithm 7 Evaluate

The algorithm Evaluate is a simple algorithm where it‘s functionality is just

evaluate the value from the variables, constants, object properties and

operators.

Algorithm Iterate

Input: RECT (The Rectangle)

H (Rectangle Hash Table)



1. top = RECT.TOP

2. While top < RECT.BOTTOM

3. left = RECT.LEFT

4. While left < RECT.RIGHT

5. URECT = new rectangle object

6. URECT.LEFT = left

7. URECT.TOP = top

8. URECT.LAYER = RECT.LAYER

9. URECT.RIGHT = left + RECT.MINWIDTH

10. URECT.BOTTOM = top + RECT.MINWIDTH

11. left = left + RECT.MINWIDTH + RECT.MINSPACE

12. Add an entry (name of RECT, URECT) in H

13. top = top + RECT.MINWIDTH + RECT.MINSPACE

Algorithm 8 Iterate

The whole parsing process is made somewhat complex due to introduce

dynamicity. If type declaration would be made required then the algorithms

will be simpler.

It can be mention that the complexity of the algorithms are O(n), but the

actual processes are extremely depends on the value of parameters if an

iterated object exists.

4.4.4. Placement

After achieving the specific arrangement and synthesis the instances of the

components it comes naturally to place the fingers at specific locations. At

this stage the name of the components are also to be placed on the

corresponding fingers as label.


Two parameters, horizontal distance and vertical distance is necessary to

place the fingers. The distances may be zero to mean merging or negative

to mean overlap. Overlap is necessary sometimes so that the consecutive

fingers have common contact array. Figure 14, Figure 15 and Figure 16

illustrates the necessity and effects of the two types of distances.

Figure 14 A 2x2 Matrix arrangement with 0.1 micron horizontal distance and 0.2 micron vertical distance



Figure 15 A 2x2 Matrix arrangement with 0.0 micron horizontal distance and 0.0 micron vertical distance

Figure 16 A 2x2 Matrix arrangement with negative horizontal distance and 0.1 micron vertical distance. The consecutive

fingers have common contact array


At Figure 16, the horizontal distance (Hd) is calculated by negation of

addition of some constants mentioned at the DRS file shown at Figure 12

as,

Hd=-(OD_IN_NIMP+CONT_IN_OD+CONT_WIDTH+OD_IN_NIMP+CONT_IN_OD)

Algorithm Placement

Input: M (Placement Matrix)

Hd (Horizontal distance)

Vd (Vertical distance)

T (Device Template)

Su (Unit Size)

1. COMPONENT = Parse (T, Empty, {Su.LENGTH, Su.WIDTH})

2. VP = 0

3. For i = 0 to ROW

4. HP = 0

5. For j = 0 to COL

6. NEWCOMP = clone of COMPONENT

7. RECTS: Set of rectangles in NEWCOMP

8. For k = 0 to |RECTS|

9. Increment RECTSk.LEFT and RECTSk.RIGHT to HP

10. Increment RECTSk.TOP and RECTSk.BOTTOM to VP

11. HP = HP + Hd

12. VP = VP + Vd

Algorithm 9 Placement

4.4.5. Editing

Though placement may be the final stage, an additional stage may be

useful. It is often necessary to add extra devices or masks. Resizing and

deletion may be other useful features.



In this thesis implementation, a component is a collection of some mask

rectangles. The supported editing features are-

a) Component

a. Create new

b. Add from DTS file

c. Move

d. Delete

b) Mask Rectangle

a. Add

b. Resize

c. Delete

4.5. Output

After process has completed the collection of rectangle objects are used to

produce output. The output of the system is of two types. They are –

1. Screen Output

2. GDSII File

The short descriptions of the two outputs are given below.

4.5.1. Screen Output

Screen output is the visual representation of the rectangles with placed

according to their properties. Different layers are indicated as different

colors. Some examples of screen output are given at Chapter 7. Screen

output is necessary to realize and understand the component layouts and

their matching in an interactive way.


The visual output is composed of different colored mask rectangles and

the memory is managed in an Object Oriented fashion. The typical object

oriented model is given below.

4.5.2. GDSII Output

GDSII standard is used widely in VLSI layout as one of the most popular

file format for portability. Most of the professional VLSI CAD tools

support GDSII file format. As the generated device should be used further

in other CAD tools, the GDSII conversion of the device is very necessary.

In this thesis a subset of GDSII file format is implemented to generate and

carry necessary layout information. The below is a Bachus Naur

representation of the subset of GDSII stream syntax.

Component

+ left + top - width - height - name

+Component(name) +AddRect(Rect) +DeleteRect(Rect) +Move(Position)

Layer

- color - layer id

+Layer(color, layer) +AddRect(Rect) +DeleteRect(Rect) +Draw(Graphics)

Rectangle

- left - top - width - height

+Rectangle(left,top) +Resize(new size) +Draw(Graphics)

1

* *

1

Figure 17 The typical object oriented model of visual output of a component



stream HEADER BGNLIB [LIBDIRSIZE] [SRFNAME] [LIBSECUR]

LIBNAME [REFLIBS] [FONTS] [ATTRTABLE]

[GENERATIONS] [<formattype>] UNITS {<structure>}*

ENDLIB

formattype FORMAT | FORMAT {MASK}+ ENDMASKS

structure BGNSTR STRNAME [STRCLASS] {<element>}* ENDSTR

element {<boundary> | <text> }

boundary BOUNDARY [ELFLAGS] [PLEX] LAYER DATATYPE XY

text TEXT [ELFLAGS] [PLEX] LAYER <textbody>

textbody TEXTTYPE [PRESENTATION] [PATHTYPE] [WIDTH]

[<strans>] XY STRING

strans STRANS [MAG] [ANGLE]

In the implementation, all the mask rectangles are transformed into

‗boundary‘ elements and labels are transformed as 90O rotated ‗text‘

elements where the center of the text and center of the corresponding

entire component finger is common.

Figure 18 Bachus Naur representation of the GDSII stream

61 DESCRIPTION OF F~COMPSYNTH: A MATCHING AND SYNTHESIS TOOLKIT

C h a p t e r 5

DDEESSCCRRIIPPTTIIOONN OOFF FF~~CCOOMMPPSSYYNNTTHH :: AA MMAATTCCHHIINNGG AANNDD

SSYYNNTTHHEESSIISS TTOOOOLLKKIITT



5. DESCRIPTION OF F~COMPSYNTH: A

MATCHING AND SYNTHESIS TOOLKIT

A toolkit, F~CompSynth, has been developed where the algorithms and

data structures mentioned earlier are implemented such as it can be used in

industry. The name F~CompSynth stands for ―Fast and Dynamic

Component Synthesizer‖. The toolkit has been developed using Java6

platform (jdk 1.6). Java is chosen because of its cross platform execution

facilities. In general, OS platform of most of the VLSI CAD software is

Windows and Linux. F~CompSynth is a supporting toolkit. Therefore, a

single version of the toolkit is enough to execute on both the platform. As

a result, a ―jar‖ file is produced that can be distribute as the desktop

application as well as web application.

The entire implementation can be considered as a composition of an

Interactive Layout Editor and a Matching Wizard. In this section, the

features with some screenshots of F~CompSynth is discussed in details

below.

5.2. Functional Flow Chart

The entire functionality of F~CompSynth can be charted to simplify the

understanding how to use the software. The flow chart is prepared in

‗Input‘-‗Process‘-‗Output‘ fashion.


5.3. Interactive Layout Editor

The auxiliary but very important finger of the thesis is the development of

Interactive Layout Editor. This is the platform for automatic as well as

manual layout editing.

Its main graphical user interface is consists of five components. A

screenshot with marking of the components is given at Figure 20.

Descriptions of the components are given below. At the specified figure

the components are labeled with alphabetic symbols. The functionalities of

the tools are kept as minimal as possible to facilitate user learning. For

industrial needs they can be expanded.

Start

Add From

DTS File

Matching

Wizard

Manual Draw

Editing / Resizing /

Export to GDSII File

End

Figure 19 Flow Chart of the functionalities of F~CompSynth



5.3.1. Editing Canvas

The editing canvas is the place where the rectangles of devices are

visualized. It is possible to add rectangles, resize and delete them. Addition

of rectangle is done by drawing it using mouse. At resizing, the border will

be highlighted and dragging the border will cause the change of its size.

The entire canvas can be zoomed in and out. At a certain level of zoom,

the canvas is divided by grids. Drawing is bound to the grids. Generally,

one grid call represents 0.1 micron.

5.3.2. Menus

Menus are the main command area. There are five main menus. The

menus with their menu items are listed along with a short description.

a) File

a. New: Clearing all the components

b. Add Device: Add a device from a DTS file

c. Save: Save the current layout information in a text file

d. Save As GDSII: Save the current layout information in a

GDSII file

e. Exit: Closing the application

b) Options

a. Fill Rectangles: Toggle between transparent and filled

visualization of the rectangles

b. Show Grid: Toggle between showing and not the grid

c. Scaling Factor: Set 1 grid unit = x micron


c) Tools

a. Matching Wizard: The wizard to synthesis matched

components.

b. Read GDSII: A test tool which parse a GDSII file and

translated it into text format

c. Go To: Go to specified coordinate

d) Component

a. New Component: Add a new empty component

b. Move Component: Move the specified component to a

specified location

c. Show Component: Move to the coordinate of the specified

component to bring it in the visible area

d. Component List: Show the list of rectangles of the

components and layers

e) Help

a. Help: Show a quick help

b. About: Show the development information of the tool

5.3.3. Layer Tool

Layer tool contains the list of the mask layers. The layers can be loaded

dynamically from a layer database or data file. Before drawing a rectangle, it

is necessary to select the specific layer. The color shown as background of

the layer label is also used as the color of the rectangle of that layer. A

visibility option of the layer is attached with the layers. With the unselect of

the visibility of a layer, all the rectangles of that layer will be invisible.



5.3.4. Toolbar

Only quick action modes are given at the toolbar. The default action mode

is ‗Draw‘. Moreover, ‗Edit‘, ‗Delete‘, ‗Zoom In‘ and ‗Zoom Out‘ are also

placed on the toolbar. To resize a rectangle, it is necessary to select the

‗Edit‘ mode. Selection of ‗Delete‘ will cause deletion with a click on a

rectangle‘s top-left corner. ‗Zoom In‘ and ‗Zoom Out‘ should be selected

to zoom in or out an area.

5.3.5. Component List

Component List contains the entire currently loaded components. A

component can be selected as the ‗Current Component‘ by double clicking

on it. To delete a component a component should be selected and it

should be followed by the ‗Delete‘ key press.

Figure 20 The basic visual components of F~CompSynth marked in red boundaries: A. The Editing Canvas, B. Menus,

C. Layer Tool, D. Toolbar and E. Component List.


5.4. Matching Wizard

The principle implementation of the thesis is the Matching Wizard. It is a

four step wizard that is designed to be used in a very flexible way. All the

algorithms stated above are implemented in this finger. The main purpose

of the tool is to synthesis the components so that they match themselves in

an appropriate way.

With illustration the steps are discussed below.

5.4.1. Component

First step of Matching Wizard is to collect the basic information of the

component. At first number of total components must be mentioned.

Dummy should be considered as also a component. This is followed by the

selection of the DTS file of the device or component.

Figure 21 Components: the first step of the 'Matching Wizard'



‗Browse‘ button facilitates browsing the computer file system and selection

of the file. Next user has to put the unit size (L for length and W for width)

of the component finger. The length and width can be double precision

floating number and measured in micron. ‗Next‘ button always forward the

wizard steps.

5.4.2. Component Fingers

At the second step, all of the component name which will be appeared as

finger label also should be entered. It is followed by entering the number

of fingers or ‗Multiple‘ of the components. ‗Previous‘ button causes

reappearance of the previous step.

Figure 22 Component Fingers: the second step of the 'Matching Wizard'

5.4.3. Matching Simulator

The most principal and challenging area of the thesis is the implementation

of Matching Simulator. Here the matching patterns are implemented and


an interactive model simulator is provided. The entire simulator can be

divided horizontally in two fingers. At right the placement matrix is shown.

This is a very compact arrangement of the simulation tools.

Figure 23 Matching Simulator: the third and principal step of the 'Matching Wizard'

5.4.3.1. Matrix Size

The ‗Matrix‘ labeled combo box enlists the possible matrix sizes for the

arrangements. This is calculated from the factors of the total number of the

fingers. Every time the numbers of fingers are changed, the items are also

changed in the combo box.



5.4.3.2. Matching Pattern

The ‗Matching Pattern‘ labeled combo box contains the implemented

‗Matching Patterns‘. Some patterns are variation of others. The following

four labels are some measurement of the matching of the fingers. Last of

them indicates the total weight or point of the arrangement. The less point

indicates better matching. These calculations are derived from Section

4.4.2.

5.4.3.3. Customize

At the customize tool, the components‘ name and their multiples (number

of fingers) are shown and it is possible to change the multiples as necessity.

It is often necessary for dummy component. Changing of number of

component requires going to the first step.

5.4.3.4. Commands

‗Re Calculate‘ button adopts the changes of matrix size, matching pattern

and component multiples and rearranges the placement matrix. ‗Suggest‘

button suggests the best pattern based on the point calculation.

5.4.3.5. Placement Matrix

At the right, the placement matrix is visualized where the cells contain the

representation of the fingers of the components. Each fingers of a

component are indicated with the same colored rectangle cells. On the

other hand, fingers of the different components are represented by

different colors.


5.4.3.6. Interactivity

The placement matrix is an interactive tool. It has brought a great flexibility

in design of component matching that accelerates user choice fully. The

arrangement can be changed manually by drag and drop fashion.

Dragging a finger of a component and dropping on a finger of different

component will cause a swap action between the fingers.

‗Right Click‘ on a finger will cause changing its membership to other

component (the next component). The finger of last component can be

changed to the first component in circular rotation fashion. At each

arrangement, the point will be recalculated.

5.4.4. Layout Info

In this step, two parameters, horizontal distance and vertical distance are

received as mentioned in Section 4.4.4. The parameters may be manual or

automatic. Automaticity is done by addition of the variables listed in the

DRS file and DTS file. Selecting a variable item and clicking on ‗Add‘ will

build an expression of addition of current variable with the previous

expression. A negative checkbox is provided to negate the entire

expression. At the right of the expression textbox the evaluated value is

shown. At last the ‗Finish‘ clicking will cause final synthesis and physical

placement of the components.



Figure 24 Layout Info: the last step of the 'Matching Wizard'

At the end of the wizard, the physical devices are visualized on the canvas

eliminating all previous components. The synthesized components are

given at Figure 25.

Figure 25 The synthesized components in transparent rectangle mode

73 EXPERIMENTED RESULT

C h a p t e r 7

EEXXPPEERRIIMMEENNTTEEDD RREESSUULLTT



6. EXPERIMENTED RESULT

In this chapter, the experimented results are shown. Neither any tool nor

any algorithm found to automate the device matching, it is not possible to

present comparable study of the results generated from F~CompSynth or

from the algorithms of this study with other. Still layout designers do the

matching manually (or through any unpublished process). If the

automation tool produce some correct results and the cost of the

algorithms are nearly linear, it is also must that the process is faster than the

manual process. Therefore, it is enough to prove the cost of algorithms are

linear and they produce correct result.

To proof correctness with experimented data, the entire operations of

F~CompSynth can divided into four major functionalities. They are

discussed with necessary data set below (from section 6.2). Exported

GDSII files are successfully imported by one of the popular layout editors,

‗L-Edit‘.

6.2. Algorithms and its’ Complexities

All the algorithms presented in this thesis for device matching are of time

complexity O(N), where N is the total number of fingers those are to be

placed in a cell of a matrix. The memory complexity is also linear and is

limited to O(2N), that indicates memory consumption is also very low. In

addition a table with real processing data of algorithm ―Single Symmetry

Row‖ (to generate symmetry and properly distributed data row) over some

sets of fingers is presented below. Note that, ―Algorithm for Symmetry

Detection‖ in (Bhattacharya, et al., 2004) is similar to the above algorithm

and its running cost must be greater than O(N) because symmetry is


checked for each group finger placement although the complexity analysis

of the algorithm is absent and ―checkSymmetry‖ is undefined in

(Bhattacharya, et al., 2004). Moreover, uniform dispersed distribution is

built in by default in the algorithm ―Single Symmetry Row‖ and transpose

of the placement matrix represents other topology of symmetry. In the

table below it is shown that the implemented method is very efficient and

practically it is a huge amount times of faster than human done manual

process. A Java 6 (jdk1.6) implementation on Windows XP platform in a

2.88 MHz Pentium-D desktop computer with 512MB RAM is used to

simulate it. First 15 rows are not practical case but for realization of linear

ordering. Because matching of one component is impossible; number of

components must be greater than two.

Set of Fingers Time

𝑵 Nano Sec Milli Sec

{1} 170852 0 1

{2} 24912 0 2

{3} 200305 0 3

{4} 24243 0 4

{5} 177674 0 5

{6} 201085 0 6

{7} 172048 0 7

{8} 172925 0 8

{16} 202786 0 16

{32} 216032 0 32

{100} 229613 0 100

{1000} 882814 0 1000

{10000} 5447588 6 10000

{100000} 31305261 32 100000



{1000000} 188019011 188 1000000

{1,1} 176153 0 2

{10,10} 909598 0 20

{100,100} 366100 0 200

{1000,1000} 2009888 2 2000

{1000, 10000} 11141103 11 11000

{10000, 10000} 15384529 16 20000

{100000, 100000} 52924703 53 200000

{1000000, 1000000} 390956755 391 2000000

{1,1,1,1,1,1} 197734 0 6

{10,10,10,10,10,10} 303231 0 60

{1,1,2,4,6,10,20,100,100,210,1000} 3543731 3 <2000

{10,10,20,40,60,100,200,1000,1000,

2100,100000} 43134077 43 <200000

{100,100,200,400,600,1000,2000,

10000,10000,21000,100000} 70571768 70 <200000

{1000,1000,2000,4000,6000,10000,

20000,100000,100000,210000,1000000} 599237423 600 <2000000

Table 3 The real processing time of the implementation of the algorithm "Single Symmery Row" over some data set

6.3. Variable Sized Component Synthesis

Variable sized component synthesis is tested with different sizes of NMOS.

NMOS is one of the analog devices which are widely used. Results of the

some tests are given below:

Test Case Device Information Screen Output (0.1 =1 grid cell)


1

Device Name:

NMOS

Length = 2.6

Width = 5.5

2

Device Name:

NMOS

Length = 4.6

Width = 3.5

3

Device Name:

NMOS

Length = 5.0

Width = 5.0

4

Device Name:

NMOS

Length = 2.0

Width = 1.2 Table 4 Some tests of variable sized component synthesis

From the table 3, it is shown that the devices are generated with the

specified parameters. For a good measurement the readers are suggested to



zoom in the current page and count the number of grid cells as 0.1 micron.

All other tested results are also proved correct.

6.4. Component Matching

Here, a table is presented with 24 dataset which proofs the success of the

algorithms of various matching patterns by visual output of arrangements.

To proof it correctness it is enough to find the similarity between the

patterns generated by the algorithms and the patterns suggested in

(Hastings, 2001), which are discussed in details at Section 2.3, Matching

Issues.

Set of Multiple

of Components

Matrix

Size

Matching

Pattern

Matched Arrangement

(Different colors represent

different components)

{1, 2} 1 x 3 Interdigitized

Common

Centroid


Common

Centroid


Common

Centroid

{8, 8} 4 x 4 Cross

Coupling

{8, 8} 4 x 4 Common

Centroid

Symmetry


{8, 8} 1 x 16 Single

Symmetry

Row


Common

Centroid

{4, 12} 1 x 16 Single

Symmetry

Row

{4, 12} 4 x 4 Average Dual

{2, 12} 2 x 7 Common

Centroid

Symmetry


Common

Centroid

{4, 5} 1 x 9 Single

Symmetry

Row

{1, 4, 4} 3 x 3 Interdigitized

Common

Centroid

{1, 2, 4} 1 x 7 Single

Symmetry

Row

{1, 3, 4} 1 x 8 Single

Symmetry

Row

{4, 4, 4} 3 x 4 Cross

Coupling




Common

Centroid


Common

Centroid

{4, 4, 4, 4} 2 x 8 Interdigitized

Common

Centroid


Common

Centroid

{4, 4, 4, 4} 4 x 4 Cross

Coupling


Common

Centroid

{1,2,2,4,4,8,8,16} 5 x 9 Interdigitized

Common

Centroid

{1,2,2,4,4,8,8,16} 5 x 9 Common

Centroid

Symmetry

Table 5 Various result from various inputs of matching simulation

6.5. Mathematical Pattern Testing

A table of mathematical measurement of various arrangements of different

component set is presented at Table 6. From the Equation 2, 3, 4 and 5 the

value of A, S, D and P is evaluated. At Equation 2, the value of

𝑊𝑎 , 𝑊𝑠 , 𝑊𝑑 is assumed roughly to 60, 20 and 10 (weight ratio 6:2:1 with

magnification factor 10). Note that, the values must not empirical one.


Test

No.

Arrangement Average

Coordinate

Position, A

Measurement

of Symmetry,

S

Inter

Distance,

D

Matching

Point, P

1

Inter-digitized

Common Centroid

0.0555 0.0 9.65 -93.23

0.5 0.0 8 -50

0.05 1.0 9.3 -69.67

2

Inter-digitized

Common Centroid

0.0 0.0 22.6 -226.0

0.125 2.0 22.12 -173.78

0.5 0.0 20.0 -170.0

3

2.0 6.0 12.0 120.0

Cross Coupling

0.0 5.33 17.43 -67.62

0.22 6.0 16.94 -36.11

4

0.0 0.0 87.03 -870.30



Inter-digitized

Common Centroid

5.02 13.0 69.14 -130.06

0.82 3.0 84.99 -740.48

5

Inter-digitized

Common Centroid

0.0 0.0 365.09 -3640.9

3.69 1.0 360.72 -3365.96

0.0 0.0 404.23 -4042.36

Table 6 Mathematical measurement of different arrangements of the components

From the table it is shown that with few exceptions most of the times the

lowest value of P represents an implemented matching pattern. Moreover,

it also indicates a very good visualization. Note that, the best arrangement

of a component set of a test case is marked by gray color shade. An

arrangement with no caption does not belong to any implemented

matching pattern.

6.6. Placement of the Fingers of the Components

It is enough to present some test cases of components‘ placement to proof

(by induction) its correctness in their placement.


Test 1:

Device: NMOS

Unit Size: 2 x 5.2 micron

Set of Multiples: {3, 3}

Matching Pattern: Inter-digitized

Common Centroid

Horizontal Distance: 0.5 micron

Vertical Distance: 1.0 micron

Test 2:

Device: NMOS


Set of Multiples: {1, 2, 4, 8}

Matching Pattern: Inter-digitized

Common Centroid

Horizontal Distance: -1.9 micron


Test 3:

Device: NMOS


Set of Multiples: {4, 4, 4, 4}

Matching Pattern: Cross Coupling

Horizontal Distance: 0.0 micron


Table 7 Placement test of different input choices



C h a p t e r 7

CCOONNCCLLUUSSIIOONN AANNDD RREESSEEAARRCCHH DDIIRREECCTTIIOONN

85 CONCLUSION AND RESEARCH DIRECTION

7. CONCLUSION AND RESEARCH DIRECTION

The principal achievements of the thesis are the evaluation of the

mathematical model for matching prediction and the developed toolkit for

successful synthesis flow of the matched components. The mathematical

model is a unique one and offers great opportunity in VLSI layout design

especially in placement. The successful prediction of the matching at

design time (before the fabrication phase) significantly reduces the overall

design time with its cost. Therefore, it has a great economical and

commercial value indeed. The mathematics can also be used as the fitness

function in a genetic algorithmic process of matching.

The proposed description language, DTS successfully offers a minimal set

of attributes which can be used generally to describe the VLSI devices in a

dynamic way. The language is developed with simple relational description.

The vocabulary consists of the basic types only - other scripted file or

technology file, data variable, input from outside or environment and

rectangle object. Rectangle object is treated as singular object by default

and defining the width and spacing property transforms it into the

rectangle array.

The developed algorithms for different matching patterns are very accurate

and tested with various inputs also. The implementations are also too

accurate those have been used already in several simulations. The running

cost of all the algorithms are kept in O(N) in worse case where memory

complexity is also limited to O(2N). This proofs the efficiency of the

algorithms. The algorithms never use the mathematical model of matching

prediction. To estimate which pattern is better for a particular set of some



components‘ fingers, mathematics can be applied on the placement

matrixes generated from the applications of the algorithms on that set.

The toolkit developed in this thesis offers great flexibility that allows analog

circuit designers to bring their special design knowledge and experiences

with an automation process into the synthesis of high-quality analog VLSI

layouts. This tool includes a complete tool suite that covers the following

three major analog physical designs stages. 1) Device Template Scripting:

designers can write and maintain their own technology-dependent template

files for layouts using an in-house developed descriptive language. 2)

Placement: a three-stage placement technique, tailored for the analog

placement design, is proposed. In particular, the matching placement

algorithms feature a dynamic rule base placement stage followed by a fast

iteration scheme. In automated matching arrangement, it is possible to edit

it manually in a very flexible interactive way. 3) Publishing: the ultimate

goal is to publish the layout into GDSII file format and screen output that

is successfully done and it has been imported the files by other application.

Although the device template scripting language is very easy to learn and is

used once per device, a visual tool to generate the script will be very helpful

to the designers. It can eliminate the necessity of learning the language and

shorten the development time. Moreover, the vocabularies and the

syntaxes used in DTS can be used as the superset of some extensions of

the language for describing future devices, which have more complex

description that is out of its scope.

In this thesis, automatic routing has not been integrated although it is not

one of the aspects. Therefore, in future, the work can be extended to auto

routing that will eliminate the necessity of availability other auto routing


tools or the manual routing. DRC rules checking are not implemented

because it is assumed that the DTS files are written with correct DRC

rules. But it can be provided for manual device generation to avoid fault

during design time.

Exporting to GDSII file is a good but a one way communication. It

facilitates only importing of that GDSII file by other software. GDSII file

generated from other software cannot be imported in the current

implementation. Both way communications is necessary for faster

integration and matching prediction of the arrangements by other software.

At the current stage in particular, at the development of the mathematical

model, three matching issues are implemented which can be extended to

include another properties, average internal distance of the fingers of same

components. The measurement of the matching patterns was not tested on

a big volume of data set. The particular expressions of P, f(A), f(S) and f(D)

are the subject to change for better accuracy in prediction. Especially the

weights of A, S and D is taken based on rough assumption which also

provides 75% accurate results over 30 data set. The values can be obtained

by artificial neural network or some other complex numerical methods.

With those limitations, still the tools are fully usable one. Its usability is

tested in an analog IC industry, Power IC Ltd., Bangladesh. Though the

work has some limitations, however due to effective experimental findings

we can expect its wide acceptability in IC fabrication industries. For further

improvement, the paper is planned to send to some EDA developers with

layout designers for constructive criticisms. For testing purpose, the demo

version of the implementation is available at the url

―www.geocities.com/phaysaal/FtiledCompSynth.html‖ and emails with



discussion, criticism and suggestion are invited to the email address

―[email protected]‖.


BIBLIOGRAPHY

Bhattacharya, Sambuddha, et al. 2004. Hierarchical Extraction and Verification of Symmetry Constraints for Analog Layout Automation. s.l. : U.S. Defense Advanced Research Projects Agency‘s NeoCAD program, 2004.

Bruce, J. D., et al. 1996. Analog layout using ALAS! IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 271–274. 1996.

Cohn, J. M., et al. 1994. Analog Device-Level Layout Automation. Boston : MA: Kluwer, 1994.

Conway, J. D. and Schrooten, G. 1992. An automatic layout generator foranalog circuits. Proc. Euro. Des. Autom. Conf. 1992, pp. 513–519.

Gielen, G. and Rutenbar, R. A. 2000. Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE, vol. 88, no. 12. Dec. 2000, pp. 1825–1852.

Hastings, Alan. 2001. The Art of Analog Layout. Upper Saddle River, New Jersey 07458 : Prentice Hall, Inc., 2001. 0-13-087061-7.

Lampaert, K., Gielen, G. and Sansen, W. 1999. Analog Layout Generation for Performance and Manufacturability. Boston : MA: Kluwer,, 1999.

Martin, B. 2001. Automation comes to analog. IEEE Spectrum, vol. 38, no.6. Jun 2001, pp. 70–75.

Mathias, H., et al. Jan-1998. FLAG: A flexible layout generator for analog MOS transistors. IEEE J. Solid-State Circuits, pp. 896–903. Jan-1998, Vol. 33, 6.

McCreary, J. B. 1981. Matching Properties, and Voltage and Temperature Dependence of MOS Capacitors. IEEE J. Solid-State Circuits. 1981, Vols. SC-16, 6, pp. 608-616.

Meyer zu Bexten, V. 1993. ALSYN: Flexible rule-based layout synthesis for analog IC‘s. IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 261–268. Mar 1993.

Rijmenants, J., et al. 1989. ILAC: An automated layout tool for analog CMOS circuits. IEEE J. Solid-State Circuits, vol. 24, no. 4, pp. 417–425, Apr. 1989.

Shyu, J. B., Temes, G. C. and Krummenacher, F. 1984. Random Error Effects in Matched MOS Capacitors and Current Sources. 1984, Vols. SC-19, 6, pp. 948-956.

Shyu, J. B., Temes, G. C. and Yao, K. 1982. Random Error in MOS Capacitors. IEEE J. Solid-State Circuits. 1982, Vols. SC-17, 6, pp. 1070-1076.



Zhang, Lihong, Kleine, Ulrich and Jiang, Yingtao. August 2006. An Automated Design Tool for Analog Layouts. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. August 2006, Vol. 14, 8.

91 INDEX

IINNDDEEXX

A

Algorithm 23

ANALOG 2

Automation 2, 7

Average Coordinate Position 49, 81

Average Dual 19, 20, 46, 52, 79

Average Inter-distance 51

B

Bipolar Transistors 10

C

CAD 2, 3

Capacitors 9

CMOS 10, 11, 23

Coincidence 16

Common Centroid Symmetry 41, 44, 78, 79, 80

Common-Centroid 15, 18

Compactness 17

Component Block Diagram 27

Component Synthesis 52

constraints 2, 23

Cross coupling 15, 18, 19, 41, 43

D

Device 28

Device Template Script x, 31

Different Matching issue 15

Dispersion 17

DRC vii, x, 28, 33, 36, 37

DRC Rule Checking 28

DTS vii, x, 31, 34, 35, 36, 37, 58, 64, 67, 71

Dynamically Managed Typing 34

E

Editing 57

F

F~CompSynth i, ii, v, 61, 62, 66, 74

G

GDSII vii, 11, 12, 27, 29, 32, 35, 37, 58, 59, 64,

65, 74, 86

I

Inheritance 35

Inter-digitization 17

Inter-digitized Common Centroid19, 42, 81, 82,

83



M

Matching i, ii, v, 12, 13, 14, 15, 16, 24, 41, 48,

49, 61, 62, 65, 67, 68, 69, 70, 72, 78, 81, 83

Matching Issues 12, 13

Matching Model 15, 41, 70, 78, 83

Matching Wizard 67

Measurement of Symmetry 50, 81

Menus 64

MOS 7

N

NMOS 7

O

Object Base Scripting 32

Object Orientation 35

Objects and Properties 36

Orientation 17

P

parameters 2, 24, 27

Placement 15, 42, 43, 44, 46, 55, 57, 70, 82, 83,

86

PMOS 7

Polymorphism 35

Pre-Input 27, 31

R

Resistances 8, 21

Result 74

S

Symmetry 16

system 4, 22, 23, 25, 27, 28

T

technology 2, 4, 25, 86

template 22, 27, 28

Template Drawing 28

Toolbar 66

ms thesis of al ameen 1.5 2010

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