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© 2016 NXP B.V.

MPC5748G Low Cost EVB User Guide

NXP Semiconductors Document Number: MPC5748GLCEVBUG

User Guide Rev. 0 , 05/2016

MPC5748G Low Cost EVB User Guide, Rev. 0, 05/2016

2 NXP Semiconductors

Contents

1. INTRODUCTION .............................................................................................................................................................. 3

2. LCEVB FEATURES.......................................................................................................................................................... 3

2.1. Differences to the Customer EVB ..................................................................................................................................... 4

3. CONFIGURATION OVERVIEW ..................................................................................................................................... 6

4. INITIAL SETUP ................................................................................................................................................................ 7

4.1. Power Supply Configuration.............................................................................................................................................. 7 4.1.1. Power Input Connector ................................................................................................................................................. 7 4.1.2. Power Switch ................................................................................................................................................................ 7 4.1.3. Power Status LED ......................................................................................................................................................... 8 4.1.4. MCU and Peripheral Voltage Configuration ................................................................................................................ 8

4.2. Reset Control (SW3) .......................................................................................................................................................... 8 4.2.1. Reset LEDs ................................................................................................................................................................... 9

4.3. MCU Clock Configuration .............................................................................................................................................. 10 4.4. Debug Connector (P1) ..................................................................................................................................................... 10

4.4.1. Debug Connector Pinout ............................................................................................................................................. 10

5. COMMUNICATIONS & MEMORY INTERFACES: .................................................................................................... 11

5.1. CAN Interfaces (P2, P3) .................................................................................................................................................. 11 5.2. LIN Interfaces (P6, P7) .................................................................................................................................................... 12 5.3. USB RS232 Serial Interface (P11) .................................................................................................................................. 12 5.4. USB HOST Interface (P4) ............................................................................................................................................... 12 5.5. Ethernet Interface (P5) ..................................................................................................................................................... 13 5.6. FlexRay (P8, P9, P10)...................................................................................................................................................... 13

6. USER INTERFACE (I/O) ................................................................................................................................................ 14

6.1. GPIO Matrix .................................................................................................................................................................... 14 6.2. User Switches (SW4, SW5) ............................................................................................................................................. 15 6.3. Hex Encoded Switch (SW1) ............................................................................................................................................ 15 6.4. User LED’s (DS1, DS2, DS3, DS4) ................................................................................................................................ 16 6.5. ADC Input Potentiometer (RVAR, RV1) ........................................................................................................................ 16

7. MCU PORT PIN LCEVB FUNCTIONS ......................................................................................................................... 17

8. APPENDIX ...................................................................................................................................................................... 18



1. Introduction

This user guide details the setup and configuration of the NXP MPC5748G Low Cost Evaluation Board

(hereafter referred to as the LCEVB). The LCEVB is intended to provide a mechanism for easy

evaluation of the MPC5748G family of microcontrollers, and to facilitate basic hardware and software

development.

Note that the LCEVB has a limited feature set compared to the main MPC574xG customer EVB and is

intended for evaluation purposes. Customers moving to serious development activities are recommended

to purchase the fully functional customer EVB which also has device specific daughter cards.

The LCEVB is intended for bench / laboratory use and has been designed using normal temperature

specified components (+70° C).

This product contains components that may be damaged by electrostatic discharge. Observe precautions

for handling electrostatic sensitive devices when using the LCEVB.

The user guide is intended to be read alongside the respective MCU documentation available at

www.nxp.com and includes:

Reference Manuals

Product Data Sheets

Application notes

Device Errata

2. LCEVB Features

The LCEVB provides the following key features:

Single 5 V DC external power supply input with on-board 3.3 V regulator. Power is supplied via

a 2.1 mm barrel style power jack.

Simple jumperless configuration (enhanced configuration is possible via 0 Ohm Resistors and

optional jumpers if required).

Master power switch and regulator status LED.

USB Serial interface.

2 x High Speed CAN transceiver routed to 3-way headers.

2 x LIN interfaces routed to 3-way headers.

Main clock supplied from on board crystal.

User reset switch with reset status LED’s.

Ethernet PHY and RJ45 socket (configured for MII mode).

USB Type A Host interface.

2 x FlexRay interfaces with standard 2-pin connectors.

14-pin JTAG connector.

http://www.nxp.com/



4 user LED’s wired to MCU ports.

2 user pushbutton switches wired to MCU ports.

Hexadecimal encoded switch wired to 4 MCU ports.

Simple potentiometer connected to analogue input channel.

2.1. Differences to the Customer EVB

Note that the GPIO pins used for peripherals on the LCEVB are the same as those used on the customer

EVB. This ensures maximum code compatibility between the 2 boards, making it easy to migrate from

one board to the other

Table 1. Customer EVB vs LCEVB features

Feature Customer EVB LCEVB

MCU Support Custom MCU Daughtercards for

multiple devices (socketed)

Soldered 176QFP MPC5748G

Power Supply External 12 V External 5 V (Caution)

On Board Regulators (and LED’s) 5 V, 3.3 V, 1.25 V (combination of

Linear and /or Switching regulators)

3.3 V Switching Regulator

Master Power Switch Yes Yes

Reset Control Reset button with MCU and External

Reset LED’s

Reset button with MCU and External

Reset LED’s

USB FTDI Serial Interface Yes Yes

CAN Physical Interfaces 2 (routed to 0.1” headers) 2 (routed to 0.1” headers)

LIN Physical Interfaces 2 (routed to Molex headers) 2 (routed to 0.1” headers)

FlexRay Physical Interfaces 2 (routed to 0.1” headers) 2 (routed to 0.1” headers)

Ethernet Physical Interface 1 (MII and RMII Support) 1 (MII only mode)

USB Physical Interface 2 (USB Host and OTG) 1 (USB Host)

MLB Daughtercard Connector Yes No

SAI Audio / TWRPI Connectors Yes No

SDHC Connector Full Size SDHC Socket No

Fast External Osc (FXOSC) Daughtercard Crystal * and

SMA input connector

40 MHz Crystal

Slow External Osc (SXOSC) Daughtercard Crystal * 32.768 KHz Crystal

CLKOUT signals available Yes (GPIO Matrix) Yes (Standalone pads)

User LEDS 4 4

User Pushbutton Switches 4 2

Hex Encoded Switch Yes Yes

Test Potentiometer for ADC Yes Yes

GPIO Matrix All Available Pins not otherwise used

for peripherals

Selection of Pins available from 5

GPIO Ports

Debug 14 Pin JTAG and 50 pin Nexus 14 Pin JTAG

Configuration Highly configurable via jumper shunts Fixed (limited configuration via 0 ohm

resistors)

* Daughtercard crystals are typically 40 MHz for FXOSC and 32.768 KHz for SXOSC but may vary

between daughtercards.

LCEVB Features

MPC5748G Low Cost EVB User Guide, User Guide, Rev. 0, 05/2016

NXP Semiconductors 5

The figure below shows the customer EVB (left) next to the LCEVB(right).

Figure 1. Customer and LCEVB side by side



3. Configuration Overview

Out of the box, there is no configuration required for the LCEVB to function. Unlike the customer EVB,

the LCEVB is primarily designed for a single mode of operation with no requirement for user

configuration. If you wish to have a more flexible configuration the recommendation is that the fully

configurable customer EVB is purchased.

There are however some jumper footprints and zero ohm resistors populated in positions that would

normally have jumper headers fitted (for example on the MCU power supply lines and tracking to the

peripheral interfaces). If required these can be de-soldered to modify functionality. Any such

modification is done at the full risk of the user and no support or warranty repairs will be provided for a

board that has been modified. Modifications should only be attempted by appropriately trained

personnel using the correct equipment and Personal Protective Apparel

The diagram below gives an overview of the functional blocks of the LCEVB

Figure 2. EVB Functional Blocks

Initial Setup



4. Initial Setup This section details the power, reset, clocks, and debug configuration which is the minimum

configuration needed in order to power ON the LCEVB.

4.1. Power Supply Configuration

The LCEVB requires an external power supply voltage of 5 V DC, minimum 1 A. There is a single 3.3

V switching regulator on the LCEVB providing MCU and peripheral power.

CAUTION

Connecting a power supply with a voltage greater than 5 V will result

in irrecoverable board damage. Check the power supply voltage

before connecting the plug to the LCEVB.

4.1.1. Power Input Connector

Power is supplied to the LCEVB via a 2.1 mm connector from the wall-plug mains adapter as shown

below. Note – if a replacement or alternative adapter is used, care must be taken to ensure the 2.1 mm

plug uses the correct polarisation as shown below:

Figure 3. 2.1 mm Power Connector

4.1.2. Power Switch

Slide switch SW2 can be used to isolate the power supply input from the EVB voltage regulators if

required.

Moving the slide switch to the right (away from the power connector) will turn the EVB ON.

Moving the slide switch to the left (towards the power connector) will turn the EVB OFF.

The Power supply section is located in the bottom left corner of the LCEVB



4.1.3. Power Status LED

When power is applied to the LCEVB, two green LED’s adjacent to the regulator and power connector

show the presence of the supply voltages as follows:

LED DS5 – Indicates that the 5.0 V supply voltage is present

LED DS6 – Indicates that the 3.3 V switching regulator is functioning

If no LED’s are illuminated when power is supplied to the LCEVB and the power switch is in the “ON”

position, the power adapter may be faulty or there may be a fault with the LCEVB. If only one LED is

illuminated there may be a short in that power supply rail – check there is nothing shorting on the EVB.

If you continue to have problems, contact NXP for support.

CAUTION

In the event of a short on the regulator output (in which case one of the

LED’s would be off or dimly illuminated), the regulator and/or the shorted

component will likely be hot.

4.1.4. MCU and Peripheral Voltage Configuration

The following MCU supply rails are connected to the 3.3 V switching regulator:

VDD_HV_ADC0

VDD_HV_ADC1

VDD_HV_ADC1_REF

VDD_HV_A

VDD_HV_B

VDD_HV_FLA

External Ballast Transistor Supply

Similarly all of the peripheral interfaces (or the I/O power in the peripheral interface) are supplied from

3.3 V as is the reset circuitry and the voltage sense wire on the JTAG connector.

4.2. Reset Control (SW3)

The MCU has a single bi-directional open drain Reset pin. Rather than connect multiple devices to the

reset pin directly, a reset-in and reset-out buffering scheme has been implemented on the LCEVB as

shown in Figure 4. The reset “in” from the reset switch (SW3) and the debug connectors are logically

OR’d together using an AND gate and then connected to the buffer to provide an open-drain output.

The “reset-out” circuitry provides a buffered reset signal that can be used to drive any circuitry requiring

a reset control from the MCU.

The reset circuitry is located in the bottom left quarter of the LCEVB next to the power switch connector

Initial Setup



This scheme is not required if it is guaranteed that anything driving the reset pin has an open drain drive

and that there is no significant output load on the MCU reset pin.

Figure 4. EVB Reset Control

4.2.1. Reset LEDs

As can be seen above, there are two reset LED’s that can be used to identify the source / cause of a reset:

RED LED DS8 (titled “MCU”) will illuminate if:

The MCU issues a reset (in this condition ONLY this LED will be illuminated and LED DS1

will be off)

There is a target reset (ie from the reset switch or from the debugger in which case LED DS1

will be ON)

YELLOW LED DS7 (titled “EXT”) will illuminate when an external hardware device issues a reset to

the MCU:

The reset switch is pressed

There is a reset being driven from one of the debug connectors

Table 2. Reset LED Decoding

LED DS7 (Yellow) LED DS8 (Red) Description

OFF OFF No Reset being issued from MCU or external logic

OFF ON MCU has issued a reset

ON OFF External reset issued from switch or debug BUT not being issued to MCU

(check R137 has not been removed)

ON ON External reset issued from reset switch or debug and has been issued to MCU.



4.3. MCU Clock Configuration

There is an external 40MHz crystal connected to the MCU Fast External Oscillator (FXOSC) pins

EXTAL and XTAL.

There is also a 32.768 crystal connected to the MCU Slow External Oscillator (SXOSC) pins

OSC32K_EXTAL and OSC32K_XTAL. This can be used for accurate time keeping.

There are 2 pads PG6 and PG7 (located just below the MCU) on the LCEVB to facilitate measurement

of the CLKOUT1 and CLKOUT0 signals.

Note – there is no external clock input on the LCEVB

4.4. Debug Connector (P1)

The LCEVB has a single 14-pin keyed JTAG connector for connection to an external debugger.

Before attaching or removing the debug cable from the LCEVB remove power from the EVB to prevent

damage to the LCEVB or debug hardware.

4.4.1. Debug Connector Pinout

The following tables list the pinout for the JTAG connector used on the LCEVB

Table 3. 14-Pin JTAG Debug Connector Pinout

Pin No Function Connection Pin No Function Connection

1 TDI PC0 2 GND GND

3 TDO PC1 4 GND GND

5 TCLK PH9 6 GND GND

7 EVTI PL8 8 N/C ---

9 RESET JTAG-RSTx 10 TMS PH10

11 VREF PER_HVA 12 GND GND

13 RDY --- 14 JCOMP 10K Pulldown

TDI, TDO and TMS have 10K pullup resistors on the LCEVB. TCLK has a 10K pulldown (R147) to

facilitate STANDBY exit without any additional code (at the sacrifice of slightly higher STANDBY

current), however this can be changed to a pullup if required by removing R147 and fitting the resistor

on R56.

The JTAG debug connectors is located in the top left corner of the LCEVB

Communications & Memory Interfaces:



Table 4. JTAG Pins Pull State (from MPC5748G Reference Manual)

5. Communications & Memory Interfaces:

This section details the communication interface and storage peripherals that are implemented on the

LCEVB.

5.1. CAN Interfaces (P2, P3)

The LCEVB incorporates two identical CAN interface circuits connected to MCU CAN0 and CAN1

using MC33901 transceivers. Both transceivers are configured for high speed operation by pulling pin 8

to GND via a 4.7 KOhm resistor. There are test points to allow the Select pin to be driven high if

desired. The MC33901 is pin compatible with other CAN transceivers supporting full CAN FD data

rates.

For flexibility, the CAN transceiver I/O is connected to a 0.1” header (P2 for CAN0 / P3 for CAN1)

rather than using non-standard DB9 connectors. The pinout of these headers is shown below.

Figure 5. CAN Physical Interface Connectors

H

L

GND

1

The CAN circuitry is located on the top right edge of the LCEVB



5.2. LIN Interfaces (P6, P7)

The LCEVB incorporates two LIN transceiver circuits connected to MCU LIN0 and LIN1, using an

NXP MC33662 transceiver. The MPC5748G LIN0 supports both master and slave modes whereas LIN1

only supports master mode.

On the LCEVB, the LIN0 transceiver is configured as slave mode by default. Master mode operation is

possible by either populating a zero ohm resistor (R143) or buy fitting a jumper header (J2) – see the

schematics for details. The LIN0 transceiver is hard wired for master mode.

To save on board space and cost, both LIN transceivers are connected to 0.1” pitch 3x1 headers as

shown below rather than the usual LIN Molex header.

Figure 6. LIN Physical Interface Connector

Note that in order for the LIN transceiver to function, external 12v must be supplied via pin 2 of the

connector

5.3. USB RS232 Serial Interface (P11)

The LCEVB incorporates a USB RS232 serial interface providing RS232 connectivity via a direct USB

connection between the PC and the EVB. The circuit contains an FTDI FT2232D USB to Serial

interface which should automatically install the drivers for two additional COM ports on your PC. Note

that only one of these ports is used so you will need to try both (usually the higher numbered COM port

is the active one). For more information on the USB drivers and general fault finding, consult the FTDI

website at http://www.ftdichip.com/

The MCU LIN2 signals are routed to the FTDI transceiver (UART TX and RX). No handshaking

signals are implemented and no board configuration is required.

5.4. USB HOST Interface (P4)

The LCEVB includes a Type A (Host) USB interface, routed to a USB type A female connector. The

USB circuit contains a USB83340 transceiver with a MIC2026-1YM USB power switch. There is no

hardware user configuration required to use the USB circuit.

The USB RS232 interface is on the left hand edge of the board (USB Type B socket)

The USB Host interface is on the top left corner of the LCEVB on the left side

The LIN Physical interface circuits are located on the right edge of the LCEVB

Vsup

Lin

GND

1

http://www.ftdichip.com/

Communications & Memory Interfaces:



5.5. Ethernet Interface (P5)

The EVB incorporates a single DP83848c Ethernet transceiver with the circuitry configured for MII

mode. The transceiver is connected to a pulse J1011F21PNL RJ45 connector which includes a built-in

isolation transformer. There is no hardware configuration needed.

If you require RMII mode or access to both Ethernet ports on the MPC5748G, please purchase the

MPC5748G customer EVB and appropriate daughter cards.

Note that the MCU Ethernet signals are all in the VDD_HV_B domain. The Ethernet PHY will only

function with 3.3 V I/O so if you have made any modifications to the EVB power domain configuration

(via the zero ohm resistors), you need to ensure the VDD_HV_B domain is at 3.3 V before attempting to

use the Ethernet module. If VDD_HV_B is set to 5 V, the signals routed to the Ethernet PHY (see the

EVB schematics) must be left as tristate to prevent damage to the transceiver.

5.6. FlexRay (P8, P9, P10)

The LCEVB incorporates two FlexRay TJA1080TS/N interfaces connected to MCU FlexRay channels

A and B and routed to two Molex 1.25 mm pitch PicoBlade shrouded headers (standard on many NXP

EVB’s). There is no hardware configuration required to use FlexRay.

Note that the LCEVB is supplied with a 40 MHz crystal by default. If FlexRay is configured to use the

external clock source, then the crystal should be left at 40 MHz.

The Ethernet interface is mid-way along the top edge

of the LCEVB

The FlexRay interfaces are midway down the left hand

edge of the LCEVB



6. User Interface (I/O)

This section details the user I/O available on the LCEVB and includes the GPIO matrix, switches,

LED’s and the ADC variable resistor.

6.1. GPIO Matrix

A sub-set of available GPIO pins (available pins being those not already routed to LCEVB peripherals)

are available at the GPIO matrix as detailed below. The matrix provides an easy to follow, intuitive,

space saving grid of 0.1” header through-hole pads. Users can solder wires, fit headers or simply insert a

scope probe into the respective pad.

To use the matrix, simply read the port letter from the top or bottom row of text then the pad number

from the columns on the left or right of the matrix. For example, the 1st pad available on Port B is PB5

as outlined below.

Figure 7. GPIO Matrix

If a pad is populated in the matrix, it means this is available for exclusive use as GPIO. The exception to

this are the port pins detailed below which are also shared with switches or user LED’s (shaded red in

the matrix diagram above).

PD0, PD1, PD2, PD3 – HEX Encoder Switch

PA1, PA2 – User pushbutton Switches

If you require access to all of the available GPIO pads, the customer EVB and daughtercard provides

this additional functionality.

The GPIO matrix is on the right hand edge of the LCEVB

User Interface (I/O)



6.2. User Switches (SW4, SW5)

There are two active high (pulled low, driven to 3.3 V) pushbutton switches on the LCEVB connected

directly to MCU GPIO ports. No configuration is required to use the switches.

SW4 is connected to port PA1 (which is also the NMI pin) and SW5 is connected to port PA2

NOTE

The MCU ports used on the user pushbutton switches are also routed to

the GPIO matrix.

6.3. Hex Encoded Switch (SW1)

There is a single hex encoded 16 position rotary switch on the LCEVB. This outputs a binary encoded

hex value (active high) on four MCU ports (Port D[0..3]).

Table 5. Hex Encoder Switch (SW2)

Position HEX_SW4

(PD3)

HEX_SW3

(PD2)

HEX_SW2

(PD1)

HEX_SW1

(PD0)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

B 1 0 1 1

C 1 1 0 0

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

Note that POSN 0 will ensure that no voltage is applied to the pads. This allows the pads to be used as

normal GPIO (with 10K pulldown) and accessed at the respective pads on the GPIO matrix area.

The user pushbutton switches are in the bottom right corner of the LCEVB

The hex encoder switch is located to the left of the GPIO Matrix



6.4. User LED’s (DS1, DS2, DS3, DS4)

There are four active low user LED’s, DS1 to DS4, connected directly to 4 MCU ports (PG[2..5]) as

shown below. No configuration is required to use the LED’s.

Table 6. Use LED’s (DS1, DS2, DS3 and DS4)

User LED MCU Pin

DS1 PG2

DS2 PG3

DS3 PG4

DS4 PG5

6.5. ADC Input Potentiometer (RVAR, RV1)

There is a small variable resistor RV1 on the LCEVB which routes a voltage between 0v and 3.3 V to

MCU pin PB4. This is useful for quick ADC testing. Test point RVAR can be used to probe the voltage

with a voltmeter.

Note that this circuit provides a very rough way to evaluate the ADC. There is a small current limiting

series resistor network to limit the injection current to around 4.4 mA.

The user LED’s are above the user switches in the lower right corner

The ADC Pot is above the hex switch to the left of the GPIO matrix

MCU Port Pin LCEVB Functions



7. MCU Port Pin LCEVB Functions

The table below shows what each MCU pin is used for on the LCEVB.

Table 7. LCEVB 176QFP Port Pin Functions

No Port A Port B Port C Port D Port E Port F Port G Port H

0 GPIO CAN0 JTAG GPIO 3 --- GPIO Ethernet Ethernet

1 GPIO 2 CAN0 JTAG GPIO

3 --- GPIO Ethernet Ethernet

2 GPIO 2 LIN0 USB1 GPIO

3 FlexRay A GPIO GPIO

4, Ethernet

3 Ethernet LIN0 USB1 GPIO 3 FlexRay A GPIO GPIO

4 ---

4 GPIO ADC Pot FlexRay B GPIO FlexRay B GPIO GPIO 4 ---

5 GPIO GPIO FlexRay A GPIO FlexRay B GPIO GPIO 4 ---

6 GPIO GPIO LIN1 GPIO --- GPIO GPIO ---

7 Ethernet GPIO LIN1 GPIO --- GPIO GPIO ---

8 Ethernet EXTAL32 RS232 GPIO --- GPIO --- ---

9 Ethernet XTAL32 RS232 GPIO --- GPIO --- JTAG

10 Ethernet SAI Audio CAN1 GPIO --- GPIO USB1 JTAG

11 Ethernet GPIO CAN1 --- GPIO USB1 USB1

12 GPIO GPIO FlexRay GPIO Ethernet GPIO Ethernet USB1

13 GPIO GPIO FlexRay GPIO Ethernet GPIO Ethernet ---

14 GPIO GPIO FlexRay GPIO USB1 Ethernet USB1 ---

15 GPIO GPIO FlexRay GPIO USB1 Ethernet USB1 ---

No Port I Port J

0 GPIO ---

1 GPIO ---

2 GPIO --- Key:

3 GPIO --- Pin not bonded out on 176QFP package

4 USB1 --- --- Pin not accessible on LCEVB

5 USB1

6 GPIO

7 USB1

8 GPIO

9

10

11 Ethernet

12 GPIO

13 GPIO

14 GPIO

15 GPIO

2 Shared with user switches

3 Shared with Hex Encoder Switch

4 Shared with user LED’s



8. Appendix

The MPC5748G LCEVB schematics, Rev B are shown below.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AFreescale AISG Applications, East Kilbride

Comms1 - CAN and LIN

Revision Information

x1DesignerAlasdair Robertson

CommentsRev Date

Power - MCU Power

Reset and JTAG

Sheet 8Sheet 9Sheet 10Sheet 11Sheet 12Sheet 13Sheet 14Sheet 15

These schematics are provided for reference purposes only. As such,NXP does not make any warranty, implied or otherwise, as to thesuitability of circuit design or component selection (type or value) used inthese schematics for hardware design using the NXP Calypso family ofMicroprocessors. Customers using any part of these schematics as abasis for hardware design, do so at their own risk and NXP does notassume any liability for such a hardware design.

Sheet 2Sheet 3Sheet 4Sheet 5Sheet 6Sheet 7MCU GPIO 1

Comms 4 - Ethernet (MII Mode)Comms 3 - USB Host Interface (device footprints only)Comms 2 - FTDI RS232 Interface

User notes are given throughtout the schematics.

Specific PCB LAYOUT notes are detailed in ITALICS

Caution:

MCU GPIO 2

Comms 5 - FlexRayUser - Switches, LED's and PotentiometerUser - GPIO Pin Matrix

Table Of Contents:

Notes:

MPC5748G Low Cost Evaluation Board (MPC5748G-LCEVB)

- All components and board processes are to be ROHS compliant- All small capacitors are 0402 unless otherwise stated- All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated- All jumpers are denoted Jx. Jumpers are 2mm pitch- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2. 2 Pin jumpers generally have the "source" on pin 1.- All switches are denoted SWx- All test points (SMT wire loop style) are denoted TPx- Test point Vias (just through hole pads) are denoted TPVx

Power - Main input and 3.3V regulator

Clocks

Start of capture, Working version (256BGA)14 Apr 2015

Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes.

3 Different test points used in design:

TPVx - Through Hole Pad small

TPHx - Through Hile Pad Large (for standard 0.1" header).Also used on IO Matrix (IOMx)

TPX - Surface Mount Wire Loop

Alasdair Robertsonx2 08 May 2015 Changed to 176 QFP Package and changed periperhal Matrixx3 18 May 2015 Alasdair Robertson

Alasdair RobertsonChanges required for initial placementTidy Up, Replaced some "hard to source" components19 May 2015x4Power - MCU DecouplingRenumber and Back Annoted from Layout26 May 2015x5 Alasdair Robertson

x6 27 May 2015 Alasdair Robertson Correction to GND on 3v3 Regulator circuitx7 29 May 2015 Alasdair Robertson Correction to CAN Test pointsx8 31 May 2015 Alasdair Robertson Few refdes changes after layout tweaksx9 01 Jun 2015 Alasdair Robertson Correction to user LED Refdes after re-numberx10 01 Jun 2015 Alasdair Robertson DNP Jumpers. 0 Ohm resistors added accross LIN jumpersA 11 Jun 2015 Andrew MacDonald Prototype Manufacture ReleaseAX1 29 Sep 2015 Alasdair Robertson Prodn Build changes (LIN0 default to Slave, LIN1 Master only)

PN Changed to MPC5748G-LCEVBAX2 26 Oct 2015 Alasdair Robertson Change to JTAG Pulls to meet latest RM SpecAX3 29 Oct 2015 Alasdair Robertson Changed RV1 current limit resistor. SW4 / SW5 refdes swapAX4 09 Dec 2015 Alasdair Robertson Pull DOWN on TCLK to mitigate against STANDBY exit issue. AX5 20 Jan 2016 Alasdair Robertson Updated NXP LogosB 12 Feb 2016 Alasdair Robertson Updated NXP Logos

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Automotive Microcontroller ApplicationsEast Kilbride, Scotland

This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

SCH-27897 PDF: SPF-27897 B

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Friday, February 12, 2016

Index and Title Page

A. Robertson

A. Robertson

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NXP General Business Use

Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



SCH-27897 PDF: SPF-27897 B

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A. Robertson

A. Robertson

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Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:



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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Main Power In (SR = Swithing Reg)

GND Test Points, Top Side

Power Input and Linear Voltage Regulators

2.1mm BarrelConnector

(Power Switch)

Power Supply Input

Test and reference points

GND Test Points,underside of board

3.3v Switching Regulator

Inoput Voltage 5V, Output 3.3V at 700mA. Ripple 1.4mV, Approx 90% efficient

Power ControlJumpers can be fitted tofacilitate power measurements

5V-IN

MCU_5V0

MCU_3V3

GND

5V0_SR

GND

GND

PER_HVA

PER_HVB

3V3_SR5V0_SR

5V0_SR

3V3_SR

5V0_SR

3V3_SR

GND

MCU_5V0 3

MCU_3V3 3

Drawing Title:


Date: Sheet of

Page Title:

Automotive MicrocontrollerApplicationsEast Kilbride, Scotland

SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



2 15

NXP General Business UseDrawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



2 15



Date: Sheet of

Page Title:


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MPC5748G-LCEVB

B



2 15


R138 178K

R47 0

C260.1UF

R49 0

R45 0DNP

P121

32

R43270

GND1

1

J4

HDR 1X2

DNP1 2

GND4

1

5v0

1

R46 0

DS5

LED GREEN

AC

R44 0DNP

GND2

1

R48 0

GND16

1

3v3

1

R142560

C2210UF10V

SW21 34 2

5

D4B340A

AC

GND15

1

C2322UF10V

C2110UF10V

TPS62082

U10

EN1

GND2

MODE3

FB4

VOS5

PG6

SW7

VIN8

EP9

J3

HDR 1X2

DNP1 2

L3 1.0uH1 2

GND3

1

DS6

LED GREEN

AC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Individual MCUsupply control

Default Configuration:

- ALL MCU supply voltages are set to 3.3V(ADC0, ADC1, VDD_HV_A, VDD_HV_B, VDD_HV_C,VBallast)- VDD_HV_FLA = External 3.3V supplied (jumperfitted)

The analogue pins can only be driven to thesame voltage as the VDD_HV_x domain they aresituated in (ie max 3.3V) so makes sense forthe analogue supply and reference to be 3.3V

3v3

5v0

Calypso MCU Power ConnectionsPower Supply Contraints:

- If VDD_HV_A is driven from 3.3V, VDD_HV_FLA mustalso be supplied from 3.3V- If VDD_HV_A is driven from 5V, the VDD_HV_FLA pin must be disconnected from 3.3V

- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V.This will trigger the ESD protectrion on that pad.For example if VDD_HV_A is set to 3.3V and theanalogue supplies are set to 5V, you cannot drive 5Vinto a pad in the VDD_HV_A domain

Notes on signal Grounds:

- The scheme shown has the analogue and digital grounds connected to the same plane - This results in better ADC performance than using an analogue grond plane with single entrypoint (or ferrite) to digital ground plane.

MCU_5V0

MCU_3V3

HVB

_CAP

HVF

LA_C

AP

LV_C

AP

ADC

0_C

AP

ADC

1_C

AP

ADC

1REF

_CAP

GND

HVA

_CAP

E_CAP

B_CAP

LVD

EC_C

AP

GND GNDGNDGND

C_CAP

MCU_3V32

MCU_5V02

Drawing Title:


Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso MCU Power

3 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso MCU Power

3 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso MCU Power

3 15


1.25v Core & External BallastAnalogue Calypso 6M 176QFPPackage 2of3 Power Pins

Flash

Central Pad for heatdissipation & GND

U20B

PPC5748GSK0MKU6

VRC

_CTR

L32

VSS_

LV_1

0910

9

VDD

_LV_

3131

VDD

_LV_

5454

VDD

_LV_

110

110

VDD

_LV_

152

152

VDD

_HV_

A_6

6

VDD

_HV_

A_59

59

VDD

_HV_

A_85

85

VDD

_HV_

A_15

115

1

VDD

_HV_

B_12

412

4

VSS_

HV_

ADC

089

VDD

_HV_

ADC

090

VDD

_HV_

ADC

199

VSS_

HV_

ADC

197

VDD

_HV_

FLA

27

VDD

_HV_

ADC

1_R

EF98

VSS_

HV_

77

VSS_

HV_

2828

VSS_

HV_

5555

VSS_

HV_

5757

VSS_

HV_

8686

VSS_

HV_

123

123

VSS_

HV_

150

150

VDD

_LP_

DEC

30

VSS_

HV_

VPP

26

EP17

7

R99 0DNP

R111 0DNP

Q50MJD31CT4

34

1

R1390

R101 0 R124 0

R114 0DNP

R98 0

R123 0

TPH3

1

R100 0

TPH21

R112 0

R103 0DNP

R122 0

R102 0

R97 0DNP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Capacitor Types:

4700pF - Ceramic X7R, 50V 10% 04020.1uF - Ceramic X7R, 16V 10% 0402 (Kemet C0402C104K4RAC)0.68uF - Ceramic X7R, 16V 10% 0805 (Murata GCM219R71C684KA37)1uF - Ceramic X7R, 10V 10% 0603 Low ESR (Taiyo Yuden LMK107B7105KA-T)2.2uF - Ceramic X7R, 10V 10% 0603 Low ESR (Taiyo Yuden LMK107B7225KA-TR)

Place small Caps as close as possible to MCU pins

ADC

VDD_HVA VDD_HVB

VDD_LV

VDD_LV (1.25V) Decoupling. Place one of the 0.1uF caps close to each VDD_LVpin. Place the 0.68uF caps on each side of the package such that there isno cap on the side with the ballast transistor

Ballast Transistor

Flash

Calypso MCU Decoupling and bulk storage

LP Internal Reg Cap

Place close to transistor

One 0.1uF cap per VDD_HV_x pin. Place as close as possible to pin

(lowESR)

(lowESR)

(For regulator stability the total capacitance should be around 2.2uF).

(lowESR)

ADC0_CAP ADC1REF_CAPADC1_CAP

GND

HVA_CAP

GND

HVB_CAP

LV_CAP

GND

HVFLA_CAP

B_CAP E_CAP

GND

LVDEC_CAP

GND

GND GND GND

C_CAP

GND

Drawing Title:


Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso MCU Decoupling

4 15



Date: Sheet of

Page Title:


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MPC5748G-LCEVB

B



4 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B



4 15


C1182.2UF

C1000.1UF

C1160.1UF

C1200.1UF

C270.68uF

C960.1UF

C980.1UF

C1100.68uF

C941uF

C920.1UF

C1090.1UF

C1130.1UF C117

1uF

C971uF

C1222.2UF

C951uF

C99

0.1UF

C1194700pF

C1110.68uF

C1122.2UF

C1080.1UF

C930.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TARGETRESETLED

Reset Switch(1.65 to 5.5v operation)

(MCU RESET)

Tri-State BufferedRESET signal toreset the MCU

Reset and External Clock In

Buffered RESET-out

Note:

The Reset pad on Calypso is in the VDD_HV_A domain which can be run from either 3.3V or 5V(selected by the VDD_HV_A and PER_HVA jumpers)

To maintian brightness on the LED's irrespective of the voltage setting, the LED's arepowered from constant 3.3V, grounded via the reset line.

Bi Directional resetline to/from MCU

Active reset drive (high / low)for any periperhals that need tobe reset when MCU is in reset

Reset fromDebugger

Reset Input / OutputPORSTConnect an external LVI to padwhen supplying external 1.25V sothat PORST is asserted untilexterbal 1.25V supply is atthreshold and stable

(2.5 to 5v operation)

(060350V)(0603

50V)

(060350V)

Reset is in theVDD_HVA domain.

TDITDOTCLK

(bufferedreset TO MCU)

(bidirectionalMCU reset)

OptionalConfig

EVTI

TMS

(RDY)

ONCE Connector

(N/C)(TMS)

(GND)(GND)(GND)

(GND)

(TDI)(TDO)(TCLK)(EVTI)(RESET)(VREF)

JTAG Standard 14-pin Connector

Note TCLK needs to be pulled down to allow exit from STANDBY in some corner cases

MCU-RSTxJTAG-RSTx

RST-SWITCHx

RST-OUTx

RST-INxSYSTEM-RSTx

PORSTx

PH9

PC0PC1

DBUG-RSTx

JTAG-RSTx

MCU-RSTx

JCOMP

PH10

PH10

GND

GND

GND

3V3_SR

GND

GND

PER_HVA

3V3_SR

PER_HVA

GND

PER_HVA

GND

JTAG-RSTx5MCU-RSTx 5,7

RST-OUTx 12

PORSTx 7

MCU-RSTx5,7

PH107

PH97

PC07PC17

JTAG-RSTx5

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


Reset Circuitry & External Clock In

5 15



Date: Sheet of

Page Title:


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MPC5748G-LCEVB

B



5 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



5 15


U12B

SN74LVC2G08DCT

5

63

C1210.1UF

TPH11

DS8

LED RED

A C

DS7YELLOW LED

AC

C250.1UF

TPV5

R13410.0K

R140270

U11

ADM6315-26D2ARTZR7

GND

1

RESET2

MR3 VCC

4

R5310.0K

R141 270

R5610.0KDNP

RST

1

R54 0

DNP

R13610.0K

R55 0

C240.1UF

R137 0

R5210.0K

VCC

GND

U12A

SN74LVC2G08DCT

1

27

84

R14710.0K

R5810.0K

SW3 B3WN-60021 2

R13510.0K

R5710.0K

R3710.0K

P1

CON_2X7

1 23 4

657 89 10

11 1213 14

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Oscillators

(XTAL32)

(EXTAL32)

NX8045GB-40.000M-STD-CSJ-1 XTAL(Optimised for Automotive, 8pF Load capacitance)

FC-255 32.7680K-A3(Load Capacitance 7pF)

Clocks

MCU-EXTAL

MCU-XTAL

PB8

PB9

GND

GND

MCU-XTAL7

PB87

PB97

MCU-EXTAL7

Drawing Title:


Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Clocks

6 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Clocks

6 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Clocks

6 15


R421.0MDNP

C20 12PF

Y332.768KHZ

12

C18 12PF

Y240.0MHZ

12

R411.0MDNP

C17 12PF

C19 12PF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Calypso GPIO 1 of 2

Key to text colours:Purple - Comms Physical Interfaces

Blue - Debug (JTAG & Nexus)

(LIN0_RX)(LIN0_TX)

(LIN1_TX)(LIN1_RX)

(XTAL32)(EXTAL32)

(FR_A_TX)

(FR_A_TX_EN)(FR_A_RX)

(FR_B_TX_EN)

(FR_B_RX)(FR_B_TX)

(USB1_CLK)

(USB1_D0)(USB1_D1)

(USB1_D2)(USB1_D3)

(USB1_D4)(USB1_D5)

(USB1_D6)(USB1_D7)

(USB1_DIR)

Orange - Other Peripherals and I/O

(RMII_RXD0)(RMII_RXD1)(MII_RXD2)

(MII_RXD3)(MII_CRS)

(RMII_TXD0)(RMII_TXD1)

(MII_TXD2)(MII_TXD3)

(RMII_TXEN)

(RMII_MDC)(RMII_TXCLK)

(RMII_RXDV)(RMII_MDIO)

(RMII_RXER)(MII_COL)

(MII_RXCLK)

(FR_DBG0)(FR_DBG1)(FR_DBG2)(FR_DBG3)

(TDI)(TDO)

(TCK)(TMS)

Black - Clock, Reset and Control

Green - I/O Matrix (dedicated)

(CLKOUT1 GPIO)

(HEX1 & GPIO)(HEX2 & GPIO)(HEX3 & GPIO)(HEX4 & GPIO)

(SW1 & GPIO**)(SW2 & GPIO)

(LED1 & GPIO)(LED2 & GPIO)(LED3 & GPIO)(LED4 & GPIO)

RED - I/O Matrix and other functions (eg LED)

(CLKOUT0 GPIO)

(ADC_POT)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(CAN0_TX)(CAN0_RX)

(CAN1_RX)(CAN1_TX)(RS232_RX)(RS232_TX)

(eMIOS E1UC_11_H)(eMIOS E1UC_12_H)(eMIOS E1UC_13_H)(eMIOS E1UC_14_H)

(WKPU2 / NMI0)(WKPU3)

(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(GPIO)

(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)

PA 12..15 has SPI

PD has ADC0 and ADC1

(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

PA0PA1

PA3PA2

PA4PA5

PA7PA6

PA8PA9

PA11PA10

PA12PA13

PA15PA14

PB0PB1

PB3PB2

PB4

PB8PB9

PC0PC1

PC3PC2

PC4PC5

PC7PC6

PC8PC9

PC11PC10

PC12PC13

PC15PC14

PD0PD1

PD3PD2

PD4PD5

PD7PD6

PD8PD9PD10

PD12PD13

PD15PD14

PE3PE2

PE4PE5

PE12PE13

PE15PE14

PF15PF14

PG0PG1

PG3PG2

PG4PG5

PG7PG6

PG11PG10

PG12PG13

PG15PG14

PH0PH1PH2

PH9

PH11PH10

PH12

MCU-EXTALMCU-XTAL

PORSTxMCU-RSTx

PB10PB11PB12PB13PB14PB15

PB5PB6PB7

PF13

PF11PF12

PF1PF0

PF3PF2

PF4PF5

PF7PF6

PF8PF9PF10

PH0 12

PORSTx5MCU-RSTx5

MCU-EXTAL6MCU-XTAL6

PB09PB19PB29PB39

PB86PB96

PA1112PA1215PA1315PA1415PA1515

PA712PA812PA912PA1012

PA114,15PA214,15PA312PA415

PB414

PC119PC1213PC1313PC1413PC1513

PC69PC79PC810PC910PC109

PC513PC413

PC05PC15PC211PC311

PD1215PD1315

PD615PD715PD815PD915PD1015

PD515PD415

PD014,15PD114,15PD214,15PD314,15

PH1 12PH2 12

PH9 5PH10 5PH11 11PH12 11

PG0 12PG1 12PG2 14PG3 14PG4 14PG5 14

PG10 11PG11 11PG12 12PG13 12PG14 11PG15 11

PF14 12PF15 12

PE2 13PE3 13PE4 13PE5 13

PE12 12PE13 12PE14 11PE15 11

PD1415PD1515

PA015

PA515PA615

PB515PB615PB715

PB1015PB1115PB1215PB1315PB1415PB1515

PF0 15PF1 15PF2 15PF3 15PF4 15PF5 15PF6 15PF7 15PF8 15PF9 15PF10 15PF11 15PF12 15PF13 15

Drawing Title:


Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 1of2

7 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 1of2

7 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 1of2

7 15


PG61

PG71

Calypso 176QFPPackage 1of3 GPIO Pins1

U20A

PPC5748GSK0MKU6

RESET29

PORST153

XTAL56

EXTAL58

PA024

PA119

PA217

PA3114

PA451

PA5146

PA6147

PA7128

PA8129

PA9130

PA10131

PA11132

PA1253

PA1352

PA1450

PA1548

PB039

PB140

PB2176

PB31

PB488

PB591

PB692

PB793

PB861

PB960

PB1062

PB1196

PB12101

PB13103

PB14105

PB15107

PC0154

PC1149

PC2145

PC3144

PC4159

PC5158

PC644

PC745

PC8175

PC92

PC1036

PC1135

PC12173

PC13174

PC143

PC154

PD077

PD178

PD279

PD380

PD481

PD582

PD683

PD784

PD887

PD994

PD1095

PD12100

PD13102

PD14104

PD15106

PE018

PE120

PE2156

PE3157

PE4160

PE5161

PE6167

PE7168

PE821

PE922

PE1023

PE1125

PE12133

PE13127

PE14136

PE15137

PF063

PF164

PF265

PF366

PF467

PF568

PF669

PF770

PF842

PF941

PF1046

PF1147

PF1243

PF1349

PF14126

PF15125

PG0122

PG1121

PG216

PG315

PG414

PG513

PG638

PG737

PG834

PG933

PG10138

PG11139

PG12116

PG13115

PG14134

PG15135

PH0117

PH1118

PH2119

PH3120

PH4162

PH5163

PH6164

PH7165

PH8166

PH9155

PH10148

PH11140

PH12141

PH139

PH1410

PH158

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Calypso GPIO 2 of 2

(USB1_NXT)(USB1_STP)

(USB1_RST)

(ENET_RST)

Green - I/O Matrix (dedicated)

Key to text colours:Purple - Comms Physical Interfaces

Blue - Debug (JTAG & Nexus)

RED - I/O Matrix and other functions (eg LED)

Orange - Other Peripherals and I/O

Black - Clock, Reset and Control


(GPIO)


PI4PI5

PI7

PI11

PI0

PI6

PI8

PI12PI13PI14PI15

PI1PI2PI3

PI1112

PI711

PI511PI411

PI015PI115PI215PI315

PI615

PI815

PI1215PI1315PI1415PI1515

Drawing Title:


Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 2of2

8 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 2of2

8 15



Date: Sheet of

Page Title:


SCH-27899 PDF: SPF-27899 B

MPC5748G-LCEVB

B


Calypso GPIO 2of2

8 15


Calypso 176QFPPackage 3of3 GPIO Pins2

U20C

PPC5748GSK0MKU6

PI0172

PI1171

PI2170

PI3169

PI4143

PI5142

PI611

PI712

PI8108

PI11111

PI12112

PI13113

PI1476

PI1575

PJ074

PJ173

PJ272

PJ371

PJ45

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(Enable)

CAN & LIN Physical

EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A

(LIN0_TX)(LIN0_RX)

(LIN1_RX)(LIN1_TX)

VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)

VI/O - determines the signal level on MCU TX and RX pinsand can range from 2.8 to 5.5V

STB - High for Standby mode, pulled low for normal mode.

CAN1 Physical Interface

(CAN0_RX)(CAN0_TX)

(CAN1_RX)(CAN1_TX)

(TXD_0)

LIN1 Physical Interface

CAN0 Physical Interface

3 pinheader(NOTMolex)

Master Mode Pullup EnableLIN0 Physical Interface

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(LEF = 20K Baud)

Total currentthrough resistors(LIN Bus at GND)= 12mA (0.144W)

Each resistor spec = 0.1W (0.2W total)

(Wake)

WAKE = GND ensures no spurious wakeups

(LEF = 20K Baud)

Total currentthrough resistors(LIN Bus at GND)= 12mA (0.144W)

Each resistor spec = 0.1W (0.2W total)

(Wake)(Enable)

EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A

Master Mode Pullup Enable

(060350V)

MC33662LEF LIN transceiver is newer version of 33661 offering:

- Full LIN compliance (33661 no longer compliant)- Improved ESD protection on LIN pin up to 15KV- Improved ESD on Wake and VSUP Pins- Other EMC and performance improvements

See freescale.com for more details

WAKE = GND ensures no spurious wakeups

BatteryReversepolarity &PulseProtection

BatteryReversepolarity &PulseProtection

All CAN and LIN signals arein power domain VDD_HV_A.

All interfaces will work at3.3V or 5.0V (PER_HVA)

CAN termination resistorfootprint. Place onunderside of PCB

CAN termination resistorfootprint. Place onunderside of PCB

VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)

VI/O - determines the signal level on MCU TX and RX pinsand can range from 2.8 to 5.5V

STB - High for Standby mode, pulled low for normal mode.

3 pinheader(NOTMolex)

Configired as SLAVE by default(Lin0 Supports Master and Slave)

Configired as MASTER by default(Lin1 only supports Master mode)

CAN0-CANLCAN0-S

PB0

LIN0-TX

PB1

PC10PC11

PB3PB2

PC7PC6

LIN0-RX

LIN0-LIN

CAN1_TX

CAN0_TX

CAN0_RX

LIN1-TX

LIN1-RX

LIN1-LIN

LIN0-VSUP

LIN1-VSUP

CAN0-CANH

CAN1-S

CAN1_RX CAN1-CANH

CAN1-CANL

PER_HVA

GND

GND

GNDGND

GND

GND

GNDGND

GND

GND

GNDGND

PER_HVA

GNDGND

GND

GND

PER_HVA5V0_SR

GND GND

PER_HVA5V0_SR

PB37PB27

PC77PC67

PC117

PB17PB07

PC107

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


CAN and LIN

9 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


CAN and LIN

9 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


CAN and LIN

9 15


C700.1UF

R2 120DNP

TPV16

P7

HDR_1X3

123

U2

MC33901WEF

GN

D2

TXD1

RXD4

STB8

CANH7

CANL6

VDD

3

VIO

5

C692.2UF10V

C510.1UF

R143 0DNP

R59 0

R1 120DNP

R18 2.0K

U1

MC33901WEF

GN

D2

TXD1

RXD4

STB8

CANH7

CANL6

VDD

3

VIO

5

C580.1UF

P3HDR_1X31

23

C572.2UF10V

J2

HDR 1X2

DNP1 2

R50 4.70K

VSUP2

1

C592.2UF10V

U3

MC33662BLEF

RXD1

EN2

WAKE3

TXD4

GND5LIN6VSUP7INH8

C560.1UF

R74 0

C600.1UF

D51 GF1AAC

R144 0P6

HDR_1X3

123

TPV15

D52 GF1AA C

R51 4.70K

R75 0

R64 0

R17 2.0K

R6 2.0K VSUP1

1

C552.2UF10V

R63 0

C522.2UF10V

D53 GF1AAC

U6

MC33662BLEF

RXD1

EN2

WAKE3

TXD4

GND5LIN6VSUP7INH8

D50 GF1AA C

P2HDR_1X31

23

R60 0

C530.1UF

R7 2.0K

R61 0

R62 0

C502.2UF10V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FTDI USB <-> Serial Interface- Self Powered mode. No power is taken from USB- Device efaults to Dual serial (RS232) mode ie RS232 on both A and B- Configurable I/O voltage on CHA / CHB via VDDIOA/B

Send Immediate / WakeupDisabled for CHB

Send Immediate / WakeupDisabled for CHA

Disable Receiver whenin USB suspend mode

USB RS232 (serial) Interface

(MCU_LIN2RX)(MCU_LIN2TX)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

FTDI Pin 40 (TXD)is Output fromFTDI Device,connect to MCU RXD

FTDI Pin 39 (RXD)is Input to FTDIdevice, connect toMCU TXD

All Signals are inpower domainVDD_HV_A.

FTDI interface willwork at 3.3V or 5.0V(PER_HVA)

USB_N

CLK_XTIN_6M

CLK_XTOUT_6M

USB_RNUSB_P USB_RP

FTDI_TXDFTDI_RXD PC8

PC9

5V0_SR

GND

GND

GND

5V0_SR

GND

GND

5V0_SR

GND

GND

5V0_SR

GND

GND

PER_HVA

PER_HVA

PER_HVA

PC9 7PC8 7

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


USB RS232 Interface

10 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


USB RS232 Interface

10 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


USB RS232 Interface

10 15


R12710.0K

C1022.2UF10V

C107

47PFDNP

C1010.1UF

R35 27

D2

D3D4

D1

D3BGX50A1

2

3

4

C1040.1UF

X16 MHZ

13

2

R116 0

R117 10.0KDNP

R341.5K

R126 10.0K

C1150.1UF

C1050.1UF

R115 0

C1030.1UF

12 3

4

+D-D

GV

P11

USB_TYPE_B

1

234

S1

S2

C106

47PFDNP

R38 27

R118 10.0K

R119470

R394.70K

U9

FT2232D

ADBUS024

ADBUS123

ADBUS222

ADBUS321

ADBUS420

ADBUS519

ADBUS617

ADBUS716

ACBUS015

ACBUS113

ACBUS212

ACBUS311

SI/WUA10

BCBUS030

BCBUS129

BCBUS228

BCBUS327

SI/WUB26

PWREN#41

3V3OUT6

USBDM8

USBDP7

RSTOUT#5

RESET#4

XTIN43

XTOUT44

EECS48

EESK1

EEDATA2

TEST47

AVC

C46

VCC

13

VCC

242

VCC

IOA

14

VCC

IOB

31

GN

D1

9

GN

D2

18

GN

D3

25

GN

D4

34

AGN

D45

BDBUS040

BDBUS139

BDBUS238

BDBUS337

BDBUS436

BDBUS535

BDBUS633

BDBUS732R

361.

0MR125 10.0K

C1140.033UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Adobe Acrobat Document

USB (Type A Host and Type AB OTG)

(10V0603lowESR)

(060350V)

Layout Note:Place caps &resistor asclose todevice aspossible

USB Power Switch

(USB1_DO)(USB1_D1)(USB1_D2)(USB1_D3)(USB1_D4)(USB1_D5)(USB1_D6)(USB1_D7)

(USB1_DIR)(USB1_STP)(USB1_NXT)

(Available on all packages)

(USB1_RST Active Low)

(060350V)

USB Host, Type A

(12102KV)

(50V0402)

(16VTANT)

(040250v)

(16VTANT)

(Select 60MHz CLKOUTwith 24MHz XTAL)

(1/10W 0603)

(060350V)

(10V0603lowESR)

(ID=GND for HOST mode)

(20K for HOST)

(Layout Note: Place SeriesTermination resistor closeto USB IC)

(Layout Note: Route DP and DM with90 Ohm Differential Pair. Keeptracks as short as possible)

General Layout Note. Recommendation is to keep alltracks between MCU and USB PHI less than 3" Seeadditional SMSC Layout guidelines PDF to the right

Crystals areFOXSDLF/240F-20(20pF LoadCapacitance)

USB Signalsare inpowerdomainVDD_HV_A

The USBinterfaceonly supports3.3Voperation.All I/Osignals mustbe 3.3V. IfVDD_HVA isset to 5V,USB MCU padsmust be leftas tri-state with nopullups.

(35VTANT)

USB_A_VDD1.8

USB_A_VDD3.3

USB_A_EN

USB_A_PWR

PI7

USB_A_EN

USB_A_VBUS

USB_A_DMUSB_A_DP

USB_A_DMUSB_A_5V

USB_A_DP

PG14PG15PE14PE15PG10PG11PH11PH12

PC3PI4PI5PC2

FLG_A

FLG_B

A_XOA_XI

USB1_CLK

3V3_SRGND

5V0_SR

5V0_SR

GND

GND

GND

GND GNDGND

GND

GND GNDGND

GND

GND

3V3_SR

3V3_SR

GND

PG157PE147PE157PG107PG117PH117PH127

PI48PI58PC27

PC37

PG147

PI78

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


USB Type A / Type AB

11 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



11 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



11 15


C50.1UF

R728.06K1%

C30.1UF

Y5024MHZ

12C64

33PF

R65 30

R701.0M

R81100

C41uF

C63

33PF

U5

MIC2026-1YM

ENA1

FLGA2

FLGB3

ENB4

OUTB5

GND6

IN7

OUTA8

R310.0K

TPV12C760.1UFC77

10UF

C610UF

TPV13

C781000pf

C651uF

C681000pF

R7110

L50 26OHM1 2

R73 20K

+C6610UF

V D- D+ G

USB_TYPE_A_FEMALE

P4

S1

A1A2A3A4

S2

C210UF

+

C54100UF

C11000pF

U50

USB83340

CPEN17

VBUS22

ID23

VBAT

_5V

21

DP18DM19

RESET27

NXT2

DIR31

STP29

CLKOUT1

VDD3V3_2020

VDD1V8_2828

XO25

REFCLK/XI26

VDD1V8_3030

RBIAS24

VDD

IO32

DATA713 DATA610 DATA5

9 DATA47 DATA36 DATA25 DATA14 DATA03

PAD

_GN

D33

SPK_L15 SPK_R16

REFSEL08

REFSEL111

REFSEL214

NC12

+

C671.0UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Ethernet (Configured for MII Mode)

Place Caps closeto connector

Series Termination Resistors:50 Ohms as per TI spec. Placeresistors as close to drivingsource as possible. Terminationrecommended for ALL MII signals

MCU OutputResistors Nextto MCU ondaughtercard

PHI OutputPlace Next toPHI

- Auto Negotiation Enable (All speeds / duplex supported) (AN_EN, AN0 and AN1 all Internal PullUP)

- Operating Mode (MII) (SNI_Mode Internal PullDown, MII_Mode control via PF15)

- LED Configuraiton (Mode1) (LED_CFG Internal PullUp)

- MDIX Enable (Auto MDIX Enabled) (MDIX_EN Internal PullUP)

- Physical Address (set to 0b00001) (PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown)

(MII_MODE)

Configured for MII Mode

Pulse J1011F21PNL(Includes built intransformer)

Layout Note - Place Capsand Resistors close to PHI

(RMII)

(RMII)(RMII)(RMII)(RMII)

(+MII)

(+MII)(+MII)

(+MII)

(RMII)(RMII)

(RMII)(RMII)

(+MII)(+MII)

(RMII)(+MII)

(RMII)(RMII)

(MII Clock)

(TANT)

Layout Note:Place 0.1uF cap close to each pin.10uF TANT as close to pin 23 aspossible as shown in diagram belowtaken from TI device specificaiton

PFBOUTPFBIN2PFBIN1Reset Control:- Reset from MCU Reset Out (will reset with MCU)- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in resetwhile reset config data can be driven onto pins to change mode etc.

Boot Configuration (using PHY internal Pulls)

MDIO Pullup

Layout Note:

MII Mode resistor and the MDIP ullup resistor should be placed as close as possible to thePF15 / PF14 tracks to reduce the effect of a stub on the transmission line.

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(060350V)

(MDIO)

All Ethernet Signals are in powerdomain VDD_HV_B

The Ethernet interface only supports3.3V operation. All I/O signals mustbe 3.3V. If VDD_HVA is set to 5V,Ethernet MCU pads must be left astri-state with no pullups.

(BulkStorage)

TDNTDP

RDN

LED_YLED_G

RBIAS

PA3PE12PA10PA11PF15PA9PA8PA7PE13

PG1

PF15

RDP

RST-OUTxRST-OUTx

X2

TXCLKTXENTXD0TXD1

RXDV

PFBOUTRXER

RXD1RXD0

CRS

TXD3TXD2

RXD3RXD2

COL

RXCLK

MDC

PFBOUT

PF14

PF14

PI11

CLKIN_X1

PG13PG12PH0PH1PH2

PG0

GND

3V3_SR

GNDGND

3V3_SR3V3_SR

GND

GND

GND

3V3_SR

GND

GND

3V3_SR

GND

GND 3V3_SR

GND

3V3_SR

GND

3V3_SR

3V3_SR

PE137

RST-OUTx5

PG07

PG17

PA77PA87PA97PF157PA117PA107PE127PA37

PF147

PI118

PG137PG127PH07PH17PH27

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


Ethernet

12 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


Ethernet

12 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


Ethernet

12 15


R8410.0K

P5 RJ45-8

TD+1

TD-2

CT_33

GND_44

GND_55

CT_66

RD+7

RD-8

YA9

YC10

GC

11

GA

12

GND1CG1

GND2CG2

C800.1UF

R109 50

R112.2K5%

R113 1.5K

R31 50

C740.1UF

C790.1UF

C15

33PF

R108 50R32 50

C720.1UF

R4270

R104.87K

R104 50

R122.2K

5%

C100.1UF

R30 50

Y125MHZ

21

R1349.91%

R106 50

R5270

R29 50

C14

33PF

R1449.91%

R105 50

R26 50

R107 50

C110.1UF

L51120OHM

21

R28 50

C7110UF

R82 50+C75

10UF

R27 50C70.1UF

R110

2.2K 5%

R25 50

TPV17

R23 0

C80.1UF

dp83848c

U8 10/100 single phy

RXCLK38

RSV

DPU

221

RSV

DPU

120

RSV

D5

12R

SVD

411

RSV

D3

10R

SVD

29

RSV

D1

8

RDN13RDP14

LEDACTCOL_ANEN28

IOVD

D33

_248

IOVD

D33

_132

IOG

ND

_247

IOG

ND

_135

DG

ND

36AV

DD

3322

AGN

D_2

15AG

ND

_119

TXD25

TXCLK1

LEDLINK_AN026

RXER_MDIXEN41

MDC31

RESET29

PWRDN_INT7

MDIO30

CRS/CRS_DV/LED_CFG40

RXD3_PHYAD346

RXD2_PHYAD245

RXD1_PHYAD144

RXD0_PHYAD143

RXDV_MIIMODE39

TXEN2 TXD03

LEDSPEED_AN127

PFBIN237

TXD3_SNIMODE6

TXD14

RBIAS24

COL_PHYAD042

PFBIN118

PFBOUT23

X233 X134

TDN16TDP17

25MHZ_OUT25

R22 50

R1549.91%

R83 0DNP

C810.1UF

C730.1UF

R24 50

R1649.91%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FlexRAY Physical Interface

FlexRAYdebugconnector

Decoupling Caps for BOTH IC's. Place next to power pins.

FlexRAY A

NormalEN STBN1

SleepGo to SleepRec Only 0

111

MODE

0 00

VBAT VBUF VCC VIO

(FR_A_TX)

(FR_A_RX)(FR_A_TX_EN)

(FR_B_TX)(FR_B_TX_EN)(FR_B_RX)

(FR_DBG0) (FR_DBG1)(FR_DBG2) (FR_DBG3)

FlexRAY B

(060350V)

(060350V)

(060350V)

(060350V)

Crimped lead - 279-9522Receptacle housing - 279-9156

Crimped lead - 279-9522Receptacle housing - 279-9156

(0603)

(0603)

(0603)

(0603)

(50V 0805)

(50V 0805)

Bus voltage +/- 12V (VBAT = 12v)Components spec'd for 12V operation

Bus voltage +/- 12V (VBAT = 12v)Components spec'd for 12V operation

All Signals are inpower domain VDD_HV_A.

FlexRAY interface willwork at 3.3V or 5.0V(PER_HVA)

BGE: Bus Guardian Enable. Pullhigh to enable transmitter

STBN: Standby Input. Pull Highfor non standby mode

EN: Enable Input. PUll high toenable

Note on VBAT:- Operational range is 6.5v to 60V- Undervoltage detection is max 4.5v

On EVB this is supplied from 5v, In theory thisshould be to battery with 60uS delay betweenapplying Vbat and I/O voltages. If necessary,12V can be externally supplied by removing theresistor and connecting pad to 12v

FRA-WAKE

FRA-INH1

PC5

FRA-JRXDPE2

FRA-BGE

PE3

FRA-JTXDFRA-JTXEN

FRA-BM FRA-DATA-BFRA-STBN

FRA-BP

FRB-INH2

PE4PC4

FRB-BGE

PE5

FRB-JTXDFRB-JTXENFRB-JRXD

FRB-BM FRB-DATA-BFRB-STBN

FRB-BP

FRB-EN

FRB-INH1

FRB-RXEN

FRB-DATA-A

FRB-ERRN

FRA-EN

FRB-WAKE

FRA-INH2

FRA-RXEN

FRA-DATA-A

FRA-ERRN

PC14PC12

PC15PC13

GND

GND

GND

GND

GND

PER_HVA 5V0_SR

PER_HVA 5V0_SR

GND

PER_HVA

FRBATA 5V0_SR PER_HVA

GND

GND

GND

PER_HVA

FRBATA

FRBATB

FRBATB

PC127PC147

PC157PC137

PC57PE27PE37

PE47PC47PE57

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



13 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



13 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B



13 15


C830.1UF

R76 10.0K

R85 0

TPV3

C1310PF

C8910UF

R91 10.0K

R86 10.0K

FRB2

R79 0

C910PFR80 10.0K

FRB1

TPV9

R78 0

C914700PF

C8710UF

P9

DNP

1 23 4

U7

TJA1080TS/N

TRXD011

TRXD110

TXD5

TXEN6

BGE8

STBN9

EN3

WAKE15

INH21

INH12

BP18

BM17

RXD7

ERRN13

RXEN12

VIO

4

VCC

19

VBU

F20

VBAT

14G

ND

16

L2

DLW43SH

21

4 3

C840.1UF

R3347.01%TPV7

P812

C8810UF

R120 0

TPV1 R1947.01%

L1

DLW43SH

21

4 3

C850.1UF

C1610PF

TPV4

U4

TJA1080TS/N

TRXD011

TRXD110

TXD5

TXEN6

BGE8

STBN9

EN3

WAKE15

INH21

INH12

BP18

BM17

RXD7

ERRN13

RXEN12

VIO

4

VCC

19

VBU

F20

VBAT

14G

ND

16

R90 0

C8610UF

C1210PF

C904700PF

R21 0

TPV8

R87 10.0K

R89 0

R847.01%

TPV6

P1012

R2047.01%

C820.1UF

R121 10.0K

R77 10.0K

R9 0

TPV2

R88 10.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Hex Encoded Switch (Active High)

Switches are hard wired to 3.3V rather than 5V so it's not possible to drive 5V into a 3.3V pad (which would cause damage)Similarly, the LED's are active low with 3.3v supply so can be safely coupled to pads on either 3.3V or 5V domainsThe ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage

PG[2..5] share eMIOS1UC[11..14] with PWMfunctionality

(eMIOS H / X)(eMIOS G / X)

User Pushbutton Switches (Active High)

User Peripheralls (Led's, Switches and ADC Pot)

LED's are SMD (1206) Yellow

User LED's (Active Low)

OMRON B3WN-6002 Pushbutton Switch

ADC Input Pot and Test Point

(ADC1_P[0])

Note - PA1 isalso the NMI pin!

Note that LED2 and LED4 (PG3 and PG5) can be controlled in LPU_RUN mode (and also have padkeepers in LPU_STANDBY)

(HEX_SW1)

(HEX_SW2)

(HEX_SW3)

(HEX_SW4)

(USR_LED1)(USR_LED2)(USR_LED3)(USR_LED4)

(PB_SW1)(PB_SW2)

Current limit resistors to ensureinjection spec of 5mA is notexceeded

PG2

PD2

PD3

PD1

PD0

PA1PA2

PG5

PG3PG4

PB4

GND

3V3_SR

3V3_SR

3V3_SR

GND

3V3_SR

GND

PG27PG37PG47PG57

PA2 7,15

PD1 7,15

PD2 7,15

PD3 7,15

PD0 7,15

PA1 7,15

PB4 7

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


User Peripherals

14 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


User Peripherals

14 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


User Peripherals

14 15


RV1 2K13

2

R133 270RVAR

1

R93 10.0K

SW4

1 2

R131 270

R128 10.0K

R92

100

R96 10.0K

R130 270

R40 1.5K

SW51 2

R94 10.0K

R146 1.5K

R129 270

0

351

246

789A

B C DE

F

SW1

DRS4016

C1

2

8

4

DS3AC

DS4AC

R132 10.0K

DS1AC

R95 10.0K

DS2AC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

All pads are DNP (Do Not Populate) 0.1" pitch headers placed on a 0.1" gridGPIO Pin Matrix

PORTA PORTD

Layout Notes: Pads must be placed in a 5 (W) x 16(H) matrix pattern, 2.54 mm pitch - one column for each port - 16 tall (1 row for each port number from 0 to 15). - GND pad at bottom of each colum - After production, pads should be through hole (not solder filled)

5 GND Pads (one at bottom of each colum)

PD[0..3] shared withHex Switch

PA[1,2] shared with user switches PORTB PortF PortI

PA1

PA2

PA4

PA12

PA13

PA14

PA15

PD0

PD1

PD3

PD2

PD4

PD5

PD7

PD6

PD8

PD9

PD10

PD12

PD13

PA1PA2PA4

PD0PD1

PD3PD2

PD4PD5

PD7PD6

PD8PD9PD10

PA0

PA0PA12PA13PA14PA15

PA5PA6

PA5

PA6

PD14

PD15

PI0PI1PI2PI3

PB6

PB7

PB10

PB11

PB5

PB12

PB13

PB14

PB15

PF8

PF0

PF1

PF6

PF7

PF11

PF9

PF10

PF2

PF3

PF4

PF5

PF12

PF13

PI8

PI0

PI1

PI6

PI2

PI3

PI13

PI14

PI15

PI12

PB5PB6PB7PB10PB11PB12PB13PB14PB15

PD14PD15

PD12PD13

PF13

PF11PF12

PF0PF1

PF3PF2

PF4PF5

PF7PF6

PF8PF9PF10

PI6PI8PI12PI13PI14PI15

GND

PA17,14PA27,14PA47

PD07,14PD17,14PD27,14PD37,14PD47PD57PD67PD77PD87PD97PD107

PA07

PA127PA137PA147PA157

PA57PA67

PI08PI18PI28PI38

PB57PB67PB77PB107PB117PB127PB137PB147PB157

PD147PD157

PD137PD127

PF137PF127PF117

PF07PF17PF27PF37PF47PF57PF67PF77PF87PF97PF107

PI68PI88PI128PI138PI148PI158

Drawing Title:


Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


GPIO Pin Matrix

15 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


GPIO Pin Matrix

15 15



Date: Sheet of

Page Title:


SCH-27897 PDF: SPF-27897 B

MPC5748G-LCEVB

B


GPIO Pin Matrix

15 15


IOM361

TPH5

1

IOM321

TPH8

1

IOM161

IOM81

IOM381

IOM221

IOM251

IOM201

IOM91

IOM521

IOM551

IOM101

IOM231

IOM241

IOM141

IOM571

IOM121

IOM301

IOM261

IOM291

IOM131

IOM111

IOM371

IOM271

TPH6

1

IOM281

IOM311

IOM391

IOM171

IOM401

TPH41

IOM491

IOM441

IOM181

IOM211

IOM21

IOM411

IOM331

IOM451

IOM531

IOM351

IOM501

IOM31

IOM11

IOM431

IOM461

IOM481

IOM511

IOM581

IOM561

IOM71

IOM41

IOM151

IOM541

TPH7

1

IOM421

IOM61

IOM191

IOM341

IOM51

IOM471

Document Number: MPC5748GLCEVBUG Rev. 0

05/2016

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Home Page:

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Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions.

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