Influence of gate geometry in integrated MOSvaractors on accumulation mode for RF

E. Amselem, B. Gonzalez, J. Garcia, I. Aldea, M. Marrero, A.G. Iturri, J. del Pino,S.L. Khemchandani, and A. Hernaindez

Institute for Applied Microelectronics, and Departamento de Ingenieria Electronica y Automaitica,Universidad de Las Palmas de Gran Canaria, Campus Universitario de Tafira,

35017, Las Palmas de Gran Canaria, Spain (benito@iuma.ulpgc.es).

Abstract- Driven by the many applications that varactorshave in RF integrated blocks, this work analyzes the influence ofgate geometry (width and length) on integrated accumulationMOS varactors. For this purpose, a number of varactors havebeen designed and fabricated on a 0.8 ,Im CMOS standardtechnology. The most relevant parameters: quality factor, tuningrange, and capacitance, are simulated and compared againstmeasurements. Some design considerations are reported.

Index Terms- integrated circuit, MOS, RF, varactor.

I. INTRODUCTION

N OWADAYS silicon integrated circuits find manyapplications in the gigahertz range of frequencies,

particularly at the standards GPS, UMTS, Bluetooth and LAN,where varactors are needed. In some RF integrated blocks,such us tunable filters or LC tanks for voltage controlledoscillators (VCOs), varactors are essential [1, 2]. They canalso be used as simple capacitors in others RF blocks such aslow noise amplifiers, mixers, or for impedance matchingnetworks [3].

The studied MOS varactors operate in accumulation mode.The drain and source terminals are connected, Vd5= 0, and thegate to drain/source voltage, Vgs, set the required capacitance.By changing the operation mode from depletion toaccumulation, the capacitance rises from a minimum to amaximum value. When a negative voltage is applied betweenthe gate and drain/source contacts, Vg, < 0, the totalcapacitance is the series connection of the oxide capacitance,COX, and the depletion capacitance, Cj. When the appliedvoltage is reversed, Vg, > 0, electrons coming from the two n+diffusion regions and the n-well accumulate under the oxide.In this case the gate capacitance reaches its maximum value,Cox.

In section II the classical design flow used so far isreviewed. The practical considerations assumed to develop thework are explained in Section III, together with the simulatedand measured results when varying the gate geometry. Finally,some conclusions about this work are reported in Section IV.

II. FABRICATION, MEASUREMENT AND SIMULATION

A. FabricationOur varactors have been designed interconnecting basic

cells in 0.8 ptm CMOS standard technology. Figure 1 showsthe layout of a basic cell. It is a symmetric set of sixMOSFETs, having all drain/source terminals interconnected toground: six single accumulation mode varactors in parallel.The resulting structure is surrounded by a contact metal thatconnects a buried layer under it to the drain/source terminals.Table I shows the gate geometry and number of basic cellsused for all fabricated varactors. In order to consider theinfluence of the gate geometry on the most relevantcharacteristic parameters (capacitance, C, quality factor, Q,and tuning range, TR), the gate width, w, is scaled in M2

Fig. 1. Layout of the MI basic cell.

TABLE IGEOMETRICAL PARAMETERS OF THE MOS VARACTORS

Varactor wv (jm) / (~tm) Number ofvaractorw (m) Z (m) ~~~~~~basiccellsMl 10 0.8 40M2 20 0.8 24M3 30 0.8 16M4 10 1.6 35M5 10 2.4 30

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Fig. 2. Microphotograph of the integrated MOS varactor MI with the guard-ring.

(double) and M3 (triple), and the gate length, 1, is scaled in M4(double) and M3 (triple) than that for Ml.

B. MeasurementVaractors characterization has been carried out with a

measurement system based on the Agilent 8720ES VectorNetwork Analyzer. The calibration was performed followingthe Short-Open-Load-Through (SOLT) method. As figure 2shows, the varactors have been designed and fabricatedsurrounded by guard rings, in order to use the Cascade ACP40GSG microprobes. The de-embedding method determinatesthe parasitic elements that appear in the measurement structureof the device under test. We have selected a de-embeddingmethod [4], based on the four-step de-embedding technique[5], to extract the guard-ring influence. Thus, resistance andreactance of every varactor are measured from S-parameters.As far as our varactors have a different number of cells, it is

necessary to normalize the measurements to just one basic cellin order to compare them. As all cells are shunt-connected, thevalue of the resistance of one basic cell, Rcell is calculated bymultiplying the number of cells, n, of the correspondingvaractor, by the total resistance, R. Therefore:

Rcell = n R (1)

The basic cell capacitance, Cce,11 is obtained by dividing thetotal capacitance, C, among the number of cells, as equation(2) shows:

frequency.

C. SimulationThree dimensional numerical simulations have been carried

out for every basic cell with Taurus Device [6]. The simulatedresults for their capacitance, quality factor and tuning rangeare compared with measurements.Due to symmetry, it is only necessary to simulate half of a

basic cell, as figure 3 shows for varactor MI. As the buriedlayer, connected to ground, electrically de-couples thesubstrate from the n-well, the structure has been simulatedreplacing all layers beneath the n-well by a grounded ohmiccontact (p-substrate influence is neglected). Thus CPU time isreduced and more precise simulations are performed (a highernumber of nodes, limited to 40.000, can be used in half a basiccell).

Obviously, the resistance and capacitance of a basic cellsimulated will be the half and double of the simulated values,respectively.

III. RESULTS

A. Preliminary considerationsParasitic capacitance, mainly due to interconnections, is not

taken into account in simulations. Figure 4 shows thecharacteristic curve, capacitance versus frequency, measuredand simulated for the basic cell of MI. Notice how thesimulated curve is vertically down displaced by parasiticcapacitances: Cparai in inversion mode and Cpara2 inaccumulation mode. However, for simplicity, the sameparasitic capacitance, Cpara. is assumed for all operationregions, equal to the average value of Cparal and Cpara2:

C - Cparal + Cpara2para 2

which is added to the simulated capacitance of the basic cell,Csim, as they are considered shunt-connected. Thus, thesimulated capacitance to be compared with the measured inthe characteristic curve of a basic cell is:

(5)

Ccell-_Cn (2)

Besides, following equations (3) and (4) the tuning range,TRcell and the quality factor Qcell, for a basic cell, do notdepend on the number of cells:

TRcell =TR Cmax Cmin .100(%)max + min

Qcell = Q = 2 RC

(3)

(4)

where Cmax and Cmin are the respective maximum andminimum capacitance of the varactor, R and C, are theresistance and capacitance respectively, andf is the operating

16.5l1 6.4-5=l

Fig. 3. 3D dimensional structure of half a MI basic cell. The meshing grid isincluding; w 10,um, / =0.8 ,m.

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Then, the parasitic inductance of a basic cell, Lcell, can beapproximated from the mesured C-fcurves as:

-5 -4 -3 -2 -1 0 1 2 3 4 5 6

Gate Voltage (V)

Fig. 4 Measured and simulated capacitance vesus gate voltage for a MI basiccell, including the parasitic capacitances;f= 2.1 GHz.

Csim = Csim + Cpara (6)

Particularly, the basic cell of MI Cparal and Cpara2 are 35.78fF and 36.46 fF respectively. From (5) Cpara is 36.12 fF, whichis considered in figure 4 to representCs,i. Notice how therelative errors with Ccell are drastically reduced: 1.63 %0 for thecapacitance in inversion mode and 0.32 °0 in accumulationmode. The resulting relative error for the tuning range is only1.5 00.The parasitic inductance of interconnections is not eitherconsidered in our simulations, but is critical at highfrequencies.From measured S-parameters all varactor reactance is

considered capacitive in C. Thus, when the gate voltage is set,C is nearly constant at low frequencies, C ; Cl>f and increases

drastically for frequencies close to the resonance frequency, fr.

(7)(2jfr) n Clf

Table 2 includes f, and L,e11 from (7) for every varactor. Withequation (7) the frequency dependence can be now consideredin the constant simulated capacitance of a basic cell, to becompared with Cce,. For that purpose, an effectivecapacitance, Cejsim, is defined as:

CC - sim

ef sim 1(2rf)2 Lg nf

(8)

Finally, as interconnections are excluded from simulations, thedifference between the measured resistance of a basic cell,Rcell and the corresponding simulated one is considerable.Thus, for the simulated quality factor of a basic cell, in orderto achieve proper relative errors, Rcell is used. The effectivesimulated quality factor in a basic cell is then given by:

1Qjsm2FTf -RcelliCef im

(9)

B. When varying the gate widthThe influence of the gate width is studied increasing the gate

length of varactor MI, w = 10 gim, to 20 gm and 30 gm invaractors M2 and M3 respectively. The gate length in all casesis set to I = 0.8gm.Figures 5 show the frequency dependence of capacitance (a)

and quality factor (b) of a basic cell in Ml, M2 and M3varactors. Note how simulations qualitatively predict themeasured results: the capacitance increases with the gate

-U U UF

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(b)Fig. 5. (a) Measured and simulated C-f curves for a basic cell in MI, M2 and M3 varactors; Vg = OV.

(b) Measured and simulated Q-fcurves for a basic cell in MI, M2 and M3 varactors; Vg = OV

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-o-M2 simulated* M2 measured

-A-M3 simulatedA M3 measured

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Fig. 6. (a) Measured and simulated C-f curves for a basic cell in MI, M4 and M5 varactors; Vg = 0V.(b) Measured and simulated Q-f curves for a basic cell in MI, M4 and M5 varactors; Vg = 0V

width, and the quality factor diminishes. But the relative error

is quite considerable.

C. When varying the gate lengthFigures 6 show the frequency response of capacitance (a)

and quality factor (b) of a basic cell in varactors MI, M4 andM5. The influence of the gate length is analyzed increasing thegate length of varactor MI, = 0.8 gim, to 1.6 gm and 2.4 tm

in varactors M4 and M5 respectively. The gate width in allcases is set to w =10Inm.Once again simulations qualitatively predict the measured

results in figures 6: the capacitance increases with the gatewidth, and the quality factor diminishes.

IV. CONCLUSIONS

Simulation results predict a direct scaling betweencapacitance and area in our structures, but as compared withmeasurements this is not precise. It is true when the area

increases due to increase in gate width, but not when the gatelength increases (the measured capacitance becomes smaller).On the other hand, the tuning range and quality factor

increases more with the gate length than with the gate width,whereas the resonance frequency remains nearly constant.Therefore, for a given area, the varactor performance is biggerfor gates longer than wider.

Simulated dependences of capacitances and quality factorswith gate voltage and operating frequency are qualitativelypredicted. However, in order to reduce their relative errors,

not only a better simulation of the basic cell is necessary

(realistic diffusion profiles, precise physical parameters, etc.),but also the parasitic elements due to interconnections shouldbe simulated and better modelled.

ACKNOWLEDGEMENTS

This reported work is supported in part by the Spanish MECunder projects TEC-2005-08091 -C03-02 and TEC-2005-06784-C02-02.

REFERENCES

[1] P. Andreani et al. "On the use ofMOS varactors in RF VCOs". IEEE J.of Solid-State circuits, vol. 35, pp 905-910, June 2000.

[2] P. Andreani and S. Mattisson, "On the use ofMOS varactors in RFVCO's", IEEE Journal of Solid-State Circuits, vol. 35, pp. 905-910,June 2000.

[3] R. Aparicio and A. Hajimiri, "Capacity limits and matching properties ofintegrated capacitors", IEEE Journal of Solid-State Circuits, vol. 37, pp.

384-393, March 2002.[4] T. E. Kolding, "A four-step method for de-embedding gigahertz on

wafer CMOS measurement", IEEE Trans. on Electronic Devices, vol.47, pp. 734-740, April 2000.

[5] I. Gutierrez, J. Garcia, N. Sainz, J.R. Sendra, J. de No and A. Hernandez,"PN Juction Integrated Varactors for RF Applications at DifferentStandar Frecuencies" IEEE Conference IV Topical Meetinbg on SiliconMonolithic Integrated Circuits in RF Systems. SIRF03, pp. 118-121,Germany, March 2003.

[6] Synopsys, Taurus Device Manual, 2006.

TABLE IIDERIVED PARAMETERS FROM MEASUREMENTS OF THE MOS VARACTORS

Varactor f (GHz) Lce,i (nH) TR (%)

Ml 6.20 7.07 37.23M2 5.73 4.04 47.09M3 5.58 2.84 47.75M4 6.39 5.59 60.31M5 4.82 5.07 70.12

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