microsoft powerpoint - eece426_flash_all

Introduction to Flash Memory OperationOperation

March 19, 2008Sungjoo Yoo

Embedded System Architecture Lab.

Lecture Goals

• Understanding

– Operations of Flash memory

Agenda

• Comparison of Flash memory cells

• Flash memory organization

• Flash commands

– Read, program, and erase– Read, program, and erase

• ECC (error correction code)

• Weal leveling

• Bad sector management

Context: SSD in Notebook and PDA

• SSD Benefits

– High performance, low power, and reliability

10 Flash memory chips

An Example: Intel SSD

• Especially good for random accesses w.r.t. HDD

NOR vs. NAND Summary• NOR Flash

� Random, direct access interface

� Fast random reads

� Slow erase and write

� Mainly for code storage

• NAND Flash� Block I/O access

� Higher density, lower cost

� Better performance for erase and write

� Mainly for (sequential) data storage

[Source: J. Lee, 2007]

� Mainly for code storage storage

Area Efficiency

• Metal contacts in NOR cell are the limiting factor: 2.5X difference in area/cell

[Source: Samsung, 2000]

NAND/NOR Characteristics

• NAND is currently favored thanks to better write (erase) performance and area efficiency

[Source: Micron, 2006]

NAND vs. NOR: Required Pins

• NAND utilizes multiplexed I/O (I/O[7:0] in the table) for commands and data

– NAND operation: command � address � data

• NOR has separate address and data buses


• NOR has separate address and data buses

NAND Flash Cells

Flash Operations• Operations

– Read

– Write or Program

• Changes a desired state from 1 to 0

– Erase write

1 1 1 1 1 1 1 1

[Source: J. Lee, 2007]

– Erase

• Changes all the states from 0 to 1

• Unit

– Page (sector)

• Read/Write unit (in NAND)

– Block

• Erase unit

erase

1 0 1 1 0 0 1 0

1 1 1 1 1 1 1 1

NAND Flash Architecture: 2Gb Case


tR

ttPROG

Small vs. Large Block

[Source: Micron, 2007e]

Performance Comparison


tR = 15ustPROG = 200us

Small block12.65MB/s for read2.33MB/s for program

tR = 25us

Large block16.13MB/s for read

Runtimereduction!

tR = 25ustPROG = 300us

16.13MB/s for read5.20MB/s for program

Note:The same erase timeper block!

Read Operation

25us


Data

25us

Pin Description


Commands & I/O Multiplexing


Erase Operation


Program Operation


Program with Random Data Input

• Often used for partial page program


Page Storage Methods


Read Operation (Revisited)


Page Read Cache Mode


Comparison between Normal Read and Page Mode Cache Read




Page Read Cache Mode Operation


Performance Comparison[Source: Micron, 2007]

Program Page Cache Mode


Overlapping Program Data Cycles and tPROG




Program Page Cache Mode Operation

[Source: Micron, 2007b]

Performance Comparison


Internal Data Move

[Source: Micron, 2007c]

Error…Single Page Write Case

• Remember “erase-before-write” means “no overwrite”!

(tR + tRC + tWC + tPROG )*(# pages/block) + tERASE= (25us + 105.6us*2 + 300us)*64 + 2ms= 36.32ms for a single-page (2KB) write operation



Internal Data Move Operations

• Internal data move


• Internal data move with random data input

Removed!


Removed!

Read Status

• Read status can be issued during other operations

[Source: Micron, 2007d]

The Simplest NAND Flash Controller

• NAND Flash Control by Processor


Command, Address, and Data Selection

• Which operation?int *cmd = 0xFFF010;

int *addr = 0xFFF020;

int *data = 0xFFF000;

*cmd = 0x80;*cmd = 0x80;

*addr = ColL;

*addr = ColH;

…

NAND Program & Erase


SLC vs. MLC

• SLC (single level cell) vs. MLC

1 0 11 10 00 01

SLC MLCprobability

[Source: Z. Wu, 2007]

-Fast, less error-Low bit density

-Slow, more error-High bit density

ECC (error correction code)E.g., RS, LDPC, BCH, …E.g., 4bit ECC for 512B

+

voltageVth

NAND Flash Lifetime

• # of erase operations is limited due to degradation � wear leveling & ECC are needed!


MLC vs. SLC: Characteristics

• MLC

– 2x inferior performance to SLC

– 10x shorter lifetime than SLC


Two Methods to Enhance Endurance (& Effective Capacity)

• ECC (error correction code)

• Wear leveling

ECC Algorithms

• SLC: Hamming

• MLC: RS, BCH, LDPC, etc.


Hamming Code of A Single Data

[Source: Micron, 2007f]

0

0

0

0^1^0^0

0^0^0^1 1^1^0^1 101

010

Old ECC

New ECC with the corrupted data

Corruption: 01010001 � 01010101

0

New ECC with the corrupted data

Error detection by XORing old and new ECCs

1 bit error location (=correction) by XORing old and new odd ECCs

2n data �� 2*n bits for ECC

Hamming Code on a Byte-Wide Data Packet




Hamming Code:Single Bit Error Correction Case


Spare Area to Store ECC

• Total 24 bits (=18+6)

– Byte: 512 � 29 � 2*9 = 18, Bit: 8 � 23 � 2*3 = 6

[Source: Micron, 2007g]

ECC for MLC (Example)

[Source: Z. Wu, 2007]

4 level (2 bit) cell vs. 8 level (3 bit) cell

(511, 451) Reed-Solomon code -Applied to 8 level cell-Code rate = 451/511 = 0.883-Effective bits = 3*451/511 ~ 2.6 bits/cell

>30% better capacity than 2 bit MLC

Copyback to Enhance Data Integrity

• If # errors (of a block) increases, then read data and re-write it (to the same or other block)

– Similar to self refresh in DRAM


Wear Leveling

• Two scenarios of MLC NAND Flash usage (512MB, 4096 blocks, 10k erase cycles)

– Update 6 files/hour, 50 blocks/file, 24 hours

• Only 200 blocks are used


• Only 200 blocks are used

• All 2096 blocks are evenly used

Two Wear Leveling Methods

• Method #1– Monitor the erase counts of

all blocks– On write, select the one with

the least count– Additional data migration is

needed– Lifetime is maximized with


– Lifetime is maximized with write performance overhead

• Method #2– Use only a part (e.g., 25%)

of total storage as a pool of available blocks

– On write, use the available (free of data) block with the least count

– No write performance overhead, but gives a shorter life time

Initial Bad Block Identification


The first page in the block

The data @ 2048

• Performed on boot up

• If(data at 0x2048 on Pages 0 and 1 == 0xFF)

It’s a good block

Block Degradation and Tracking at Runtime

• Important to track the blocks that go bad during normal device operation

• When and how to check?– Issue a Read Status command after any Erase and Program operation

• Two types of failure


• Two types of failure– Permanent: add the block to the bad block table– Temporary

• Program disturb: e.g., neighbor page data are corrupted• Read disturb: e.g., due to too many reads of a single page• Over-programming: e.g., all data look like ‘0’• Data loss: e.g., due to charge loss or gain• Solution: erase the corresponding block and re-program it

Reference

• [Samsung, 2000] Samsung Electronics, Samsung NAND Flash Memory, 2000.• [Micron, 2006] Micron, NAND Flash 101 - An Introduction to NAND Flash and How to

Design It In to Your Next Product, Nov. 2006.• [Micron, 2007] Micron, NAND Flash Performance Increase - Using the Micron® PAGE READ

CACHE MODE Command, June 2007.• [Micron, 2007b] Micron, NAND Flash Performance Increase with PROGRAM PAGE CACHE

MODE Command, June 2007.• [Micron, 2007c] Micron, NAND Flash Performance Improvement Using Internal Data Move,

June 2007.June 2007.• [Micron, 2007d] Micron, Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash

Devices, June 2007.• [Micron, 2007e] Micron, Small Block vs. Large Block NAND Devices, June 2007.• [Micron, 2006b] Micron, NAND Flash Design and Use Considerations, Aug. 2006.• [Micron, 2006e] Micron, Wear-Leveling Techniques in NAND Flash Devices, Aug. 2006.• [Micron, 2007f] Micron, Hamming Codes for NAND Flash Memories, June 2007.• [Z. Wu, 2007] Flash memory with coding and signal processing, US Patent 2007/0171714

A1, Published, 2007• [Micron, 2008] Micron, Using COPYBACK Operations to Maintain Data Integrity in NAND

Flash Devices, Oct. 2008.• [Micron, 2007g] Micron, Micron ECC Module for NAND Flash via Xilinx™ Spartan™-3 FPGA,

June 2007.

microsoft powerpoint - eece426_flash_all

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