microprocessor technique. bibliography arnold ken - embedded controller hardware design, isbn:...

Microprocessor Technique

Bibliography

Arnold Ken - Embedded Controller Hardware Design, ISBN: 1878707523; 246 p,

2001, Elsevier Newnes.

Stuart Ball - Embedded Microprocessor Systems, ISBN: 0750675349; 432 p, 2002,

Elsevier Newnes.

William Buchanan - Computer Busses, ISBN: 0340740760; 632 p, 2000, Elsevier

Butterworth-Heinemann.

Ted Van Sickle - Programming Microcontrollers in C, ISBN: 1878707574; chapter

1 & 2,, 2001, Elsevier Newnes

William Stallings - Computer Organization and Architecture

Betty Prince - High Performance Memories

Lecture 1 1/37

Microprocessor acting

History

Architectures

Basic definitions

Processor types

Microprocessor construction and acting 1/6

1011

Σ

A B

RR=(A+B+CIN) mod 16

CIN

COUT

COUT=(A+B+CIN) / 16

A+B+CIN = R+16·COUT

0111

0

0010

1

10010


ALU

A B

R

COUT CIN

S2..S0

S2S1S0 W COUT

0 0 0 A B 00 0 1 A B 00 1 0 A B 00 1 1 ~A 01 0 0 A + B + CIN 0/11 0 1 A - B - CIN 0/11 1 0 A + 1 0/11 1 1 A - 1 0/1


S2..S0

ALUCOUT CIN

A B

R


ABCDEF

TEMP2TEMP1

instruction

S2..S0

1. 1st operand reading

2. 2nd operand reading

3. Working ALU

4. Storing the result

Sequence of the operations

sequentialcontrol unit

ALUCY

instruction register


sequentialcontrol unit

instruction

3a. 1st operand reading3b. 2nd operand reading4. Working ALU5. Storing the result

1. Instruction fetching

Programme counter

Programmememory

01234.....

n-1n

ABCDEF

TEMP2TEMP1

ALUCY

2. Instruction decoding


Assumption:

register coding:

000

001

010

011

100

101

ABCDEF

Programme example:

PROBLEM: The sum of 3 numbers stored in registers B, C & D placed in register A

RESOLVING: For A := B + C + D the following operations are needed:

1. CY := 0 , for example A:=AA

2. A := B + C

3. CY := 0 , for example A:=AA

4. A := A + D

Instruction codes:

A:=AA:

A:=B+C:

A:=AA:

A:=A+D:

000 000 000 000

100 001 010 000

000 000 000 000

100 000 011 000

History 1/5

1670

1854

1889

1643

Pascal’smechanical

adder

1833

Boole’s algebra

Leibnitz’s calculating machine

1820

Thomas calculator

Babbage’s design: “arithmetic mill”

Hollerith’s calculating machines

applied during census in USA

History 2/5

1943

1958

1965

1971

1938

..41

Programmable calculators

Z1 , Z2 , Z3Konrad Zuse,

England

1974

1976

1944

1972

8008200kHz

40401MHz

80802MHz

80853MHz

Z802,5MHz

1900

ENIACPennsylvaniafinished 1946

MARK1Harvard

Transistor logic

SSI & MSIlogic

4004108kHz

Alan TuringJohn von Neumann

Historia 3/5

1978

1979

1981

1985

80861MB RAM5-10MHz

8088

8028616MB RAM

6-16MHz

803864GB RAM

multitasking16-33MHz

804864GB RAM

FP unit, 8kB L116-133MHz

Pentium P54GB RAMsuperscalar

FP unit, 8kB/8kB L160-200MHz

RISC 1 i 2Berkeley

1993

the first ARM

1990

1989

Am486DXx80-133MHz

History 4/5

Athlon0,5-1GHz

Pentium MMXfor video, audio,

graphic data166-266MHz

1995

1997

1998

1999

1993

Pentium P54GB RAMsuperscalar

FP unit, divided cache60-200MHz

2000

2001

Pentium Prosuperscalarextension

150-200MHz

Pentium IItechn. MMX233-450MHz

Celeron266-533MHz

Pentium IIItechn. 3D-FP0,45-1,1GHz

1996

Pentium 4for multi-media data processing

1,3-1,8GHz

Itaniumtechn. IA-641,3-1,8GHz

Celeron II433-700MHzAMD K5

75-166MHz

AMD K6166-500MHz

History 5/5

6809

1979

1984

1987

1990

6800032MB RAM

8-20MHz32b ALU

16b DATA-BUS

680204GB RAM

32b DATA-BUS16-33MHz

680304GB RAM20-50MHz

1974

1977

6800

68040FP unit

8kBcachedo 50MHz

1992

68060FP unit

8kBcachedo 75MHz

PROCESSOR MAIN MEMORY

I/O DEVICES

von Neuman’s computer structure - original conception

PROCESSOR MAIN MEMORYURZĄDZENIA

WE/WY

von Neuman’s computer structure - real solution

I/O DEVICES

SYSTEM BUS

Architectures 1/8

Architectures - definitions 2/8

Main memory - stores:

• programs during execution;

• program data;

• program results.

I/O devices – devices used for information exchange between microcomputer system and:

• man, user (operator devices);

• controlled environment (process devices);

• other systems (communication devices).

Architectures 3/8

modern computer with von Neuman’s structure

working registers

internal bus

I/O devices

data & programme

memory

flags

ext.

sign.

buffers

A

B

ALUinstruction

register

control unit

address register

PC prog. counter

commondata, address & control buses

processor

Architectures 4/8

Harvard computer structure

working registers

internal data bus

I/O devicesdata

memory

flags

A

B

ALU


control unit

data address register

PC prog. counter

common bus for data memory and I/O devices

processor ext.

sign.

buffers

internal instruction busprogramme

memory

dedicated programme memory bus

Architectures 5/8

Harvard computer structure - economical common met version

working registers

internal data bus

I/O devicesdata

memory

flags

A

B

ALU


control unit

data address register

PC prog. counter

processor ext.

sign.

buffers

internal instruction busprogramme

memory

separate control lines

common data & address buses

Architectures 6/8

Typical internal components of the processor

Inside the processor we usually can find:• universal working registers;• dedicated registers (accumulator, programme counter, stack pointer,

addressing registers, status and control registers, shifting registers);• decoders (for instruction code decoding);• counters;• ALU;• sequential control unit;• external signals buffers;• internal buses.rarely:• built-in data and programme memories.

Architectures 7/8

Example of the status register

S Z - H - P/V N C

S – sign flag

Z – zero flag, =1 when result =0

H – additional carry (or borrow) between 3rd & 4th bits

P/V – parity flag after logic operations (=1 on even number of „1” in result) either overflow flag after arithmetic operations

N – subtraction flag

C – carry flag

Architectures - definitions 8/8

Universal (general-purpose) microprocessor – device which needs external:

• main memory;

• I/O devices.

Single-chip microcomputer – device which contains in one structure:

• processor (eg. core of general-purpose microprocessor);

• main memory (all available or only part of it);

• any I/O devices (I/O ports);

• basic control devices (like: interrupt controller, address decoder, reset circuit, clocking circuit).

Microprocessor acting - instruction processing 1/14

Operation sequence of processor during processing of the single instruction

CF - instruction code fetch (k*INC(PC)) [k*MC]

ID - instruction decoding

AR - arguments reading [n*MC]

IE - instruction execution

SR - storing result [m*MC]

instructioncycle (IC)

instruction cycle (IC) - the time interval needed for complete instruction processing (fetching & execution)machine cycle (MC) - the time interval needed for single access to memory or I/O device port


working registers

I/O devices

data & programme memories

flags

ALU

IR

CU

addr.reg.PC

processor

ID

Instruction execution - presentation

instruction fetch

instruction decoding

argument reading

execution

storing the result

working registers

I/O devices

data & programme memories

flags

ALU

IR

CU

addr. reg.PC

processor

ID

IR

CU

addr.reg.PC

ID

addrreg.

IR

ID

temp.regaddr.reg.

temp.reg

working registers flags

ALUaddrreg.


Instruction execution - presentation

instruction fetch


instruction fetch

argument reading


execution

argument reading

storing the result

execution

storing the resultflags

addr.reg.ALU


instruction fetch[PC+1]


Instruction execution - presentation for Harvard architecture

workingregisters

I/Odata

memory

flaggs

ALU

IR

CU

rej.adr

PC

processor

programme memory

ID

instruction fetch


argument reading

execution

storing the result

instruction fetch[PC]


instruction fetch[PC+1]

argument reading


execution

storing the result

temp.registers

addr.reg.temp.

registers


Instruction queue processing

instructionsto execution

k+2

k+1

k t

classical solution - sequential processing

CF AR SRIEID

CF AR SRIEID

CF AR SRIEID


Instruction queue processing - cont.

Realizability condition:

• division of the processor structure into independent acting blocks

• preferred Harvard architecture


k+2

k+1

k

- waiting for free data bus

t

pipelining

CF AR SRIEID

CF AR SRIEID

CF AR SRIEID


Instruction queue processing - cont.

Realizability condition :

• multiplied internal processor blocks;

• suitable software (compilers, operating systems)


k+2

k+1

k t

parallel processing

IF AR SRIEID

IF AR SRIEID

IF AR SRIEID

Microprocessor acting - definitions 8/14

processor word (machine word) width - the number of bits in binary words, which can be processed by majority of the instructions

address space - processor address range for accesses to memory or I/O devices

stack - specific data structure, working as LIFO register, realised like: built-in register file (hardware) either programme stack (software)

Microprocessor acting - addressing modes 9/14

types of the addressing modes:

• simple - single-component (one binary word pointing the location);

• double-component (operand location - address is the sum of 2 binary words);

• multi-component (operand address is the sum of more than 2 binary words).

addressing mode - the method of pointing in instruction code the location of the operands and results

opcode arg1 arg2 resultinstruction code:


Single-component addressing modes

• immediate opcode operand

• direct opcode addressMEM

• indirect opcode address”address’

MEM

MEM• register indirectaddress opcode

Rx:

• register operand opcodeRx:


Double-component addressing modes

operand_address = base + offset

Components are called variable, if they are taken from registers, or constant (fixed) - if they come with instruction code.

base - should be a binary word with length allowing to access to

whole memory space

offset - can be shorter than base, in NB or C2 code

Basic double-component modes:

offset fixed offset variable

base fixed - index

base variable base base-index


Double-component addressing modes - examples

• index mode

d

opcode base MEM

Ry:

• base mode base

opcode d

MEM

Rx:

• base-index modebase

opcode

d

MEM

Rx:

Ry:


Double-component addressing modes - examples

PC:• relative-index mode

d

opcode

MEM

base

Ry:

• relative mode base

opcode dU2

MEM

PC:

• page mode - operand location is the address - offset from the start of the selected memory page

• segment mode - operand location is the address - offset from the start of the selected memory segment


Multi-component addressing modes - examples

• base-index with offset mode

base

opcode d

index

MEM

Rx:

Ry:

• base-index scalable with offset mode

base

opcode d

index

S

SRy

MEM

Rx:

Ry:

Processor types - CISC 1/11

CISC - Complex Instruction Set Computer - general-purpose processors with extended (200...300) instruction list

EX AF,AF’

internal address bus

internal data bus D0-D7

IR

ID

CU

A FA’ F’

tmp at

B CD EH L

B’ C’D’ E’H’ L’

IXIYSPPC

ALU

+

MPXI R

+1

A0-A15

internal control bus

EXX

8-bit general-purpose microprocessor CISC - Z80


Processors 8086/88

multiplexeddata & address bus(16b data lines in 8086, 8b data lines in 8088)

AH ALBH BLCH CLDH DL

SPBPDISI

address bus 20b

CSDSSSESIP

internalregisters

ALU

temp. registers

flags

EUcontrol

unit

internal data bus

EUExecution

Unit

1 2 3 4 5 6

instruction queue:6B in 8086, 4B in 8088

BIUBus Interface

Unit

bus control

& buffers


L1 data cache 8kB

FP registers fileInteger registers file

FPU/MMXunit

complex

integer

ALU

simple

integer

ALU

simple

integer

ALU

addressloading

unit

addressstoring

unit

FPmoveunit

L2 cache

256kB

Micro-instruction cache L1

12k micro-operat.

Instructionfetch & decode

unit

Queuing &

scheduling unit

256b

64b

systembus

Processor Pentium 4

Processor types - RISC 4/11

RISC - Reduced Instruction Set Computer - processors with “short” (about 100) instruction list

Features of the RISC instruction list:

• access to memory allowed only by MOVE instructions;

• all operands should be placed in internal processor registers;

• opcodes have fixed (the same) format (bit-length);

• minimal number of addressing modes.


Differences between RISC and CISC processors:

• pipelining processing reduces execution time;

• due to: little number of instructions of fixed format and simple addressing modes, control unit is much smaller and faster;

• Harvard architecture in RISC is very popular;

• RISC processor has many working registers, also hardware stack can be implemented, what causes fast calling and interrupt service.

Examples of RISC processors:IBM801, AM29000, Intel 80960, MIPS R2000/R3000, Motorola 88100, Sun SPARC (1988/89), PowerPC family


8-bit single-chipmicrocomputerRISC Harvardfrom AVR family (Atmel)

ZYX

WORKINGREGISTERS

SRAM128B

PSW

TIMERS/COUNTERS

INTERRUPTUNIT

EEPROM128B

PB7 .. PB0

COMPAR. ANAL.

PROGRAMMMEMORYFLASH

2kB

PROCESSORCONTR.REG.

OSCILLATOR

INTERNALOSCILLATOR

RESETXTAL1XTAL2

WATCHDOG CLOCKINGCIRCUIT

Vcc

GND

8

ALU

INSTRUCTION DECODER

DIR.REG.DDRB

OUT.REG.PORTB

BUFFFERS

PROGRAMMINGUNIT

SPI slave UART

INP.REG.PINB

USI

SP

PC

INSTR.REGISTER

CONTROLUNIT

PD6 .. PD0

DIR.REG.DDRD

OUT.REG.PORTD

BUFFERS

INPREG.PIND

BUFF.

OUT.REG.PORTA

DIR.REG.DDRA

INP.REG.PINA


Itanium 2

B B B M M I I F F

branch &predicate 128 integer registers 128 FP registers

branchunits

integer& MMU

units 16kB dual-port

L1 data

cache

ALATFP units

bus controller

96kB L2

cache

IA-32decode

andcontrol

branchprediction

scor

eboa

rd, p

redi

cate

NaT

s,

exce

ptio

ns

4MB L3

cache

16kB L1 instruction cache

& fetch/prefetchITLB

Processor types - DSP 8/11

Features of DSP (Digital Signal Processing) processors :

• fixed-point (16b) or floating-point (32b) arithmetic;

• extended ALU - parallel, fast hardware multiplier;

• “longer” arithmetic working registers;

• ALU can calculate sum & difference of operands;

• built-in shifting register, for fast shifts and rotations;

Features of DSP - cont.

• at least doubled addressing units (for faster access to memories);

• Harvard architecture;

• built-in dual-port RAM, with appropriate size;

• many external interrupt allowed;

• multilevel & priority interrupt system;

• built-in hardware unit for programme loop;

• in some processors basic instructions have conditional execution;

• built-in fast interfaces for A/D & D/A converters;



Application fields of DSP processors:

• control of the inductive motors;

• GPS;

• sound processing;

• speech processing;

• sound measures;

• video processing;

• modems;

• electric power meters 1- & 3-phase.


32-bit DSP processor ADSP2106x SHARC

microprocessor technique. bibliography arnold ken - embedded controller hardware design, isbn:...

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