microelectronic circuits ii ch 7 : differential and...

CNU EE 7.1-1

Microelectronic Circuits II

Ch 7 : Differential and Multistage Amplifiers

7.1 The MOS Differential Pair 7.2 Small-signal Operation of the MOS Differential Pair7.4 Other Nonideal Characteristics of the Differential Amplifier

CNU EE 7.1-2

Differential AmplifierDifferential-pair or differential amplifier- Building block in analog integrated-circuit design- Input stage of every op amp

Differential amplifier suited for IC fabrication- Its performance depends critically on the matching between the two sides of the circuit

à matched device whose parameters track over wide ranges of changes in environmental conditions- Utilize more components (approaching twice as many) than single-ended circuits

à availability of large numbers of transistors at relatively low cost

Why Differential ?- Much less sensitive to noise and interference than single-ended circuits à Only the difference signal between the two wires are sensed

- Enable to bias and couple amplifier stages together without the need for bypass and coupling capacitorsà large capacitors are impossible to fabricate economically

- Major topic : differential amplifiers in both its MOS and bipolar implementations

CNU EE 7.1-3

The MOS Differential Pair

MOS differential-pair amplifier- Two matched transistors, Q1 and Q2- Sources are joined together & biased by a

constant-current source I- Resistance RD à active (current-source)

load- MOSFETSs not enter the triode region of

operation

CNU EE 7.1-4

- Two gates : VCM , common-mode voltage- Q1 & Q2 are matched à- Voltage at the source à

Operation with a Common Mode Input Voltage221 Iii DD ==

GSCMS VVV -=

( ) 2'2'

21

21

2 OVntGSn VL

WkVVL

WkI=-=

( )LWkIV nOV'=

DDDDD RIVvv221 -==

- Difference in voltage between the two drains are zero- Differential- pair does not respond to (it rejects )common-mode input signal

§ I/2 by gate-source voltage VGS

2maxIRVVv DDDtCM -+=

(For Q1 and Q2 in saturation region, VG-VD ≤ Vt)

OVtCSSS

GSCSSSCM

VVVVVVVv+++-=

++-=min

§ Voltage at each drain

overdrive voltage corresponding to a drain current of I/2

§ Input common-mode range

(sufficient VCS : voltage across the current source)

CNU EE 7.1-5

Operation with a Differential Input Voltage§ vid=vGS1-vGS2 (by setting vG2=0)

If vid is positive (vGS1 > vGS2) à iD1 > iD2à output voltage (vD2 – vD1) is positive

If vid is negative (vGS1 < vGS2) à iD1 < iD2à output voltage (vD2 – vD1) is negative

Differential pair responds to difference-mode ordifferential input signals by providing a correspondingdifferential output signal between the two drains

§ vid that causes the entire bias current I to flow in Q1- vGS1 for id1=I- vGS2 =threshold voltage Vt à vS at S = - Vt

( )21'

21

tGSn VvL

WkI -=

( ) OVtn

tGS VVL

WkIVv 22

'1 +=+=

overdrive voltage for iD=I/2

If vid is increased beyond , iD1 = I, vGS1 = vS rises correspondingly , thus keeping Q2 off

OVtOVtSGSid VVVVvvv 221max =-+=+=

OVidOV VvV 22 <<-

OVV2 OVt VV 2+

§ Range of differential-mode operation

CNU EE 7.1-6

Large Signal Operation§ Transfer characteristics : iD1 & iD2 versus vid=vG1-vG2- Q1 & Q2 operate in the saturation region- Differential pair is perfectly matched- Neglect channel-length modulation (l=0) & body

effects- Drain currents of Q1 & Q2

idGGGSGS vvvvv =-=- 2121

Iii DD =+ 21

( )211 21

tGSnD VvL

Wki -¢=

( )211 21

tGSnD VvL

Wki -¢=

( )tGSnD VvL

Wki -¢= 22 21

idnDD vL

Wkii ¢=-21

21

à

By combining above 3 equations

( )222 21

tGSnD VvL

Wki -¢= à

( )tGSnD VvL

Wki -¢= 11 21

Constraint by constant-current bias

(Eq. 7.16)

CNU EE 7.1-7

Iii DD =+ 21

( )

÷øö

çèæ ¢

-÷øö

çèæ¢+=

LWkI

vvIL

WkIin

ididnD

2

12/1

22

221 2

12 idnDD vL

WkIii ¢-=

At bias (quiescent) point, vid = 0

221Iii DD ==

2

12/1

22 ÷÷ø

öççè

æ-÷

ø

öçè

æ÷÷ø

öççè

æ+=

OV

idid

OVD V

vvV

IIi

2

22/1

22 ÷÷ø

öççè

æ-÷

ø

öçè

æ÷÷

ø

ö

çç

è

æ-=

OV

idid

OVD V

vvV

IIi

§Alternative form of iD1 & iD2

GSGSGS Vvv == 21

Large Signal OperationBy squaring both sides of (Eq. 7.16) and substituting for

By iD2=I-iD1 and squaring both sides of the above equation à quadratic equation in iD1

From iD2=I-iD1 ( ) 22

21

21

2 OVntGSn VL

WkVVL

WkI ¢=-¢=

where

2''

OVnnOV V

IL

WkL

WkIV =÷øö

çèæ

÷øö

çèæ= >

( )

÷øö

çèæ ¢

-÷øö

çèæ¢-=

LWkI

vvIL

WkIin

ididnD

2

22/1

22

CNU EE 7.1-8

2

12/1

22 ÷÷ø

öççè

æ-÷

ø

öçè

æ÷÷ø

öççè

æ+=

OV

idid

OVD V

vvV

IIi

2

22/1

22 ÷÷ø

öççè

æ-÷

ø

öçè

æ÷÷

ø

ö

çç

è

æ-=

OV

idid

OVD V

vvV

IIi

nonlinear

tGSid VVv -<<2/Linear amplification by small signal approximation

÷ø

öçè

æ÷÷ø

öççè

æ+@

221id

OVD

vV

IIi ÷ø

öçè

æ÷÷

ø

ö

çç

è

æ-@

222id

OVD

vV

IIi

÷ø

öçè

æ=÷ø

öçè

æ÷÷ø

öççè

æ=

22id

mid

OVd

vgvV

Ii

transconductance gm and vid/2 by vgs1=vid/2 & vgs2=-vid/2, ID= I/2

OV

Dm V

Ig 2=

Large Signal Operation§ Effect of applying a differential input signal vid on the currents iD1 & iD2

Normalized plots, iD1/I & iD2/I versus vid/VOV- at vid=0, iD1/I = iD2/I = I/2- Positive vid à iD1 increase & iD2 decrease by equal amounts so as to keep the sum constant, iD1+ iD2 =I

- iD1 increases by an increment id & iD2 decreasesby the same amount id

- id is proportional to differential input signal vid

CNU EE 7.1-9

§ Plots of transfer characteristics iD1,2/I versus vid for various of VOV- Linear range of operation is extended by operating the MOSFET at a higher VOV (by using smaller W/L ratios) at the expense of reducing gm and hence the gain

Large Signal Operation- Linearity can be increased by increasing overdrive voltage VOV à smaller (W/L) ratio à reduction in gmà reduction in gain :: linearity- transconductance trade-off

CNU EE 7.1-10

Small-Signal Operation of the MOS Differential Pair

21id

CMGvVv +=

22id

CMGvVv -=

VCM : common-mode dc voltage & middle value of power supply à typically 0 V for two complementary suppliesvid : differential input signal in a complementary (or balanced) manner à vG1increases vid/2 & vG2 decreases vid/2

- Single-ended outputs vo1 & vo2 is riding on top of the dc voltage at the drains, (VDD-IRD/2)- Differential output vod has a 0V dc component & only signal component

§ Differential-pair as a linear amplifier

CNU EE 7.1-11

- Differential pair operation provides complementary current signals in the drains à two current signals passesthrough a pair of matched resistors, RD

- If the output is taken in a single-ended fashion : or

- If the output is taken differentially : à increase in gain by a factor of 2 (6dB)

Small-Signal Operation of the MOS Differential Pair- Power supplies is grounded, bias current-source I is removed, VCM is eliminated, ro is neglected

- Q1 & Q2 are biased at I/2 & overdrive voltage VOV- Virtual ground at the joint source connection bysymmetry of circuits & balanced manner of vid à

vgs1=vid /2 & vgs2=- vid /2- Assuming vid/2 << VOV, changes of drain currents at Q1 &Q2 are proportional to vgs1 & vgs2 à Q1 has a drain current increment gm(vid/2) & Q2 has a drain current decrementgm(vid/2) , where transconductance gm :

- Signal ground is established at the source of transistors w/o resorting to the use of a large bypass capacitor

Did

mo Rvgv21 -= D

idmo Rvgv

22 =

Dmid

o Rgvv

211 -=

§ Differential voltage gain

( )OVOVOV

Dm V

IVI

VIg ===

222

Dmid

oo

id

odd Rg

vvv

vvA =

-=º 12

Dmid

o Rgvv

212 =

CNU EE 7.1-12

§ Differential half-circuit- Symmetrical differential amplifier with a balanced

differential signal à equivalent differential half-circuit- Virtual ground on the common source à grounded source - Q1 : drain bias current I/2 & overdrive voltage VOV- Differential gain Ad from the half circuit

- Differential gain Ad with ro taken in account ( )oDmd rRgA ||=

Small-Signal Operation of the MOS Differential Pair

§ Differential pair in response to a differential input signal vid- Resistance between the gate & the source, looking into

the source = 1/gm- Total resistance between G1 & G2 in the source circuit = 2/gm- Current id is obtained by dividing vid by 2/gm

Dmd RgA =

÷øö

çèæ=

2id

mdvgi

CNU EE 7.1-13

Differential Amplifier with Current-Source Loads

- Higher gain : passive resistance RD à current sources- Current source : PMOS transistors Q3 & Q4, and dc bias voltage VG à Q3 & Q4 each conducts I/2- Differential voltage gain Ad from the differential half-circuit (b) : ( )311 || oom

id

odd rrg

vvA =º

CNU EE 7.1-14

Cascode Differential Amplifier

- Cascoding applies to the amplifying transistors Q1 & Q2 via Q3 & Q4, and to the current-sourcetransistors Q7 & Q8 via Q5 & Q6

- Differential voltage gain Ad from the differential half-circuit (b) :

( ) ( ) ( ) 7551331 || oomopoomonoponmid

odd rrgRrrgRwhereRRg

vvA ===º

CNU EE 7.1-15

- Differential amplifier with ideal current-source : VCM over a wide range à No change in the voltage at either of the two drains

- Differential amplifier with current-source having a finite output resistance RSS : à common-mode gain is no longer zero

Common-Mode Gain & CMRR

- DC input VCM + incremental signal vicm- Common-mode input signal vicm : interference signal or noise that is picked up by both inputs

Objective : how much of vicm makes its way to the output of the amplifier

§ Effect of RSS on the bias current of Q1 & Q2 :- With vicm = 0, bias current in Q1 & Q2 = I/2 + an

amount determined by VCM & RSS- Since RSS >> 1, bias current in Q1 & Q2 ~ I/2 § Effect of RSS on the differential gain Ad :- Virtual ground results in zero signal current through

RSS à RSS has no effect on the value of Ad

CNU EE 7.1-16

§ Small-signal analysis for response to vicm- VDD, VSS à 0, I à open circuit - Symmetrical circuit à Q1 & Q2 carry equal signal currents, i- i determination by Q1 & Q2 à its T model w/o ro (c)

- Drain voltages at Q1 & Q2 :

- Both vo1 & vo2 corrupted by vicm à

- Since vo1 = vo2 , the differential output voltage vodremains free of common-mode interference

- The circuit still rejects common-mode signals when the circuit is perfectly symmetrical


mSSSS

D

icm

o

icm

o gRceRR

vv

vv 12sin

221 >>-»=

SSm

icmSS

micm Rg

viiRgiv

212

+=+= >

icmSSm

DDoo v

RgRiRvv

2121 +-=-==

021 =-= oood vvv

àRSS

CNU EE 7.1-17


Common-mode half-circuit

- Two half-circuits of the differential amplifier for common-mode analysis in (d)- Two half-circuits carry a current i, and the source voltages are equal (vs = 2iRSS)

à two sources can be joined, returning to the original form in (b)

Differential half-circuit

CNU EE 7.1-18

§ Effect of RD mismatch on CMRR- Mismatch of DRD à finite CMRR even in the differential output

icmSS

Doood v

RRvvv

212D

-=-=

÷÷ø

öççè

æ D-=

D-=º

D

D

SS

D

SS

D

icm

odcm R

RRR

RR

vvA

22

SSDcmDmd RRARgA 2D-==( ) ( )DDSSm

cm

d

cm

d

RRRgCMRRAA

dBCMRRAA

CMRR

D=

=º

2

log20)(

icmSS

Do v

RRv

21 -@ icmSS

DDo v

RRRv

22D+

-@

DD RR =1 DDD RRR D+=2

§ The drain signal voltage arising from vicm


A mismatch in RD causes a finite common-mode gain = a portion of the interference or noise signal vicm appears as a component of vod

- CMRR resulting from a mismatch (DRD/RD)à

§ common-mode gain Acm

- Common-mode rejection ratio (CMRR)

CNU EE 7.1-19

Since the voltages between gate & source are equal,

Since the voltage between gate of Q1 and ground = vicm

Differential output voltage :

Common-mode gain from Dgm :

§ Effect of gm mismatch on CMRR

- Circuit is no longer symmetrical à no use of common-mode half circuit à original circuit w/ T model

( ) ( ) ÷÷ø

öççè

æ+=+=

1

21212211 111

m

mmm g

giiigigi >

( ) SSm

mmSSmicm R

ggigiRiigiv ÷÷

ø

öççè

æ++=++=

1

21112111 1

Common-Mode Gain & CMRRmmmmmmmmm ggggggggg D=-D-=D+= 2121 2

121

>

( ) ( ) SSmm

icmm

SSmm

icmm

Rggvgi

Rggvgi

21

22

21

11 11 ++

=++

=

( ) ( ) icmSSmm

DmDoicm

SSmm

DmDo v

RggRgRivv

RggRgRiv

21

222

21

111 11 ++

-=-=++

-=-=

( )( ) icm

SSm

Dmicm

SSmm

Dmmoood v

RgRgv

RggRggvvv

211 21

2112 +

D=

++-

=-=

( ) ÷÷ø

öççè

æ D=º÷÷

ø

öççè

æ D÷÷ø

öççè

æ»

+D

==ºm

mSSm

cm

d

m

m

SS

D

SSm

Dm

icm

odcm g

gRgAACMRR

gg

RR

RgRg

vvA 2

221>

A biasing current source with a high output resistance RSS à high CMRR

Dmd RgA -@

CNU EE 7.1-20

Other Nonideal Characteristics of Differential Amp.

§Input offset voltage of the MOS differential pair

§ If the two sides of the differential pair were perfectly matched (i.e., Q1 & Q2 identical and RD1= RD2 = RD), then current I would split equally between Q1 and Q2, and VO would be zero.

§ Practical circuits exhibit mismatches that result in a dc output voltage VO even with both inputs grounded.à VO : output dc offset voltageà input offset voltage VOS = VO / Adà if we apply a voltage - VOS between the input

terminals of the differential amplifier, then theoutput voltage will be reduced to zero

§ Causes for offset voltage- mismatch in load resistance - mismatch in W/L- mismatch in Vt

CNU EE 7.1-21

§ Mismatch in Load resistance- RD1 & RD2 shows a mismatch DRD

21D

DDRRR D

+=22

DDD

RRR D-=

÷øö

çèæ D

+-=221

DDDDD

RRIVV

÷øö

çèæ D

--=222

DDDDD

RRIVV

DDDO RIVVV D÷øö

çèæ=-=\

212

÷÷ø

öççè

æ D÷ø

öçè

æ==D

DOV

d

OOS R

RVAVV

2

DO RIV D=2 ( ) D

OVD

tGSDmd R

VIR

VVIRgA =-

==


- Q1 & Q2 are matched à I will split equally

- Corresponding input offset voltage

- Ex: Differential pair w/ VOV=0.2 V & 0.02D

D

RRD

= V 0.1 0.02 2 mVOS = ´ =à

VOS is proportional to VOV & DRD/RD

CNU EE 7.1-22

÷øö

çèæD+=÷

øö

çèæ

LW

LW

LW

21

1

( )( ) 222

121

IILWLWII D

+=úû

ùêë

é D+=

( )( ) ÷

÷ø

öççè

æ D÷øö

çèæ=\

LWLWVV OV

OS 2

÷øö

çèæD-=÷

øö

çèæ

LW

LW

LW

21

2

§ Mismatch in W/L ratios of Q1 & Q2


- Since I is no longer divided equally between Q1 & Q2

- Dividing the current difference DI by gm (=I/VOV)à the input offset voltage (due to mismatch in

W/L values)

- VOS is proportional to VOV & D(W/L)

( )( ) 222

122

IILWLWII D

+=úû

ùêë

é D-=

( )( ) úû

ùêë

éD=D

LWLWII

2

CNU EE 7.1-23

21t

ttVVV D

+=

( ) ( )

( ) ÷÷ø

öççè

æ-

D--»

÷÷ø

öççè

æ-

D--=

÷ø

öçè

æ D--=

tGS

ttGSn

tGS

ttGSn

ttGSn

VVVVV

LWk

VVVVV

LWk

VVVL

WkI

121

21

21

221

2'

22'

2'

1

22t

ttVVV D

-=

OV

t

tGS

t

VVI

VVVII D

=-

D=D

22

tOS VV D=

§ Mismatch in DVt between the two threshold voltages

for DVt << 2(VGS-Vt) [i.e., DVt << 2VOV ]

( ) ÷÷ø

öççè

æ-

D+-»

tGS

ttGSn VV

VVVL

WkI 121 2'

2

( )21 V V2 2n GS t

W IkL

¢ - =- Since , and current increment (decrement) in Q2 (Q1) is

- Dividing 2DI by gm à the input offset voltage (due to DVt)

- Total input offset voltage : ( )2 2

2V VV V ( / )V V (7.121)2 2 /O OD

OS tD

R W LR W L

æ öD Dæ ö= + + Dç ÷ ç ÷è øè ø


( ) ×××++-»- 22 211 xxx

microelectronic circuits ii ch 7 : differential and...

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