microcontroller systems engineering science 2nd year …dwm/courses/2co_2014/2co-l4.pdf ·...

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Microcontroller Systems

Engineering Science

2nd year A2 Lectures

Prof David Murray

[email protected]/∼dwm/Courses/2CO

Michaelmas 2014


Lecture 4

Input/Output, Interfacing, and Applications


Introduction

We have learned how a computer’s CPU and memory function andinteract, but as yet we have not considered methods of gettinginformation into or out of the computer ...

... without which the whole exercise is pointless.

Computer I/O can be described at a number of levels. Layers ofsoftware protocols build on yet more layers of hardware definition.

Our first aim here is to consider I/O the lowest level, which means ...


Register transfers — yet again

We’ve learned that the CPU is able tooutput to memory input from memoryusing

an address bus and decoder to select a particular register inmemory,a data bus to transfer the register’s contents in or out of the CPUa control bus to carry control signals (OEmem, Write/Read)

Decoder

MBR Location

MAR

CPU Memory


Exactly the same idea can be exploited for output to a particulardevice — printer, DAC, video display, etc.

Decoder

ParallelizerSerializer

Parallel link

Serial link

ORMBR

MAR

IO Register

CPU Device

Data transfer to memory is performed in parallel — high bandwidthoption is suited to devices which are physically close to CPU.

For longer distances, the output can be “serialized”.

(For many years serial communications were s l o w, but fast seriallinks are nowadays available over Universal Serial Buses (USB) andFirewire.)


Buses

In a modern desktop PC, the bus typically consists of 50 to 100separate lines in these three functional groups, and made availableon the “motherboard”

A microcontroller will have the same buses, but there is no equivalentmotherboard —

I/OCPU Memory I/O

Control Bus

Data Bus

Address Bus

— buses, memory and i/o devices tend to be held within a single ICpackage.


Bus DesignsBus design made awkward by the intricacies of timing ...... different device speeds plus accumulated “transport delay”

td = gate delay (3-6 ns) + capacitance delay (5 ns) + transit delay (6 ns m−1).

At the lowest level there are two major design approaches:

Synchronous design — requires devices to respond within aspecified time.

No continuous checks of whether the device received the data.Unsuitable when a mix of fast and slow devices sit on the bus.

Asynchronous design — devices are considered to have theirown clocks, and they a treated as separate RTL modules.

CPU and IO device negotiates transmission and receipt usingtwo control bus signals that continually monitor readiness to sendand receive data. (Hardware handshaking.)


Strategies for I/O: a comparison


Strategies for I/OOur main concern is with I/O that directly involves the CPU.

We’ll discussProgrammed I/O (uses CPU), not Direct Memory Access.

Port−mapped

I/O

Memory−

Mapped I/O

Polled

I/O

Interrupt−

driven I/O

Direct MemoryAccess

ProgrammedI/O

Within programmed I/O we compare ...Port-mapped I/O with Memory-mapped I/O

How can peripherals avoid wasting CPU time? We compare ...Polled I/O with Interrupt-driven I/O


Register-based I/O — towards port-mapped I/OConsider eight I/O registers that sit in a special “port address space”.

We’ll need a special 3-bit address bus & decoder to determine whichto I/O with, and a special data bus.

No need to group them together — they can sit separately on the bus.

0

1

2

3

4

5

6

7

Selection

Data to and from registers

3

16

spaceaddressPort

R/W

by p

eriphera

ls

I/O registers

0

1

2


5

6

3

4

7

3

16

But we would need a special PortMAR and PortMBR ...


Port-mapped I/OMore economical to use the main data and address buses, and justconnecting the lowest 3 address lines A0-A2 to the IO Registers.

567


24

012

34

3 3 3

USEmem/USEport

16

01

Main Memory IO RegistersAddress

Data

CS

BUT the addresses of the IO registers overlap those of main memory

... so we require a USEmem/USEport control level.

This will feed into the memory’s ChipSelect, and we need a similarChipSelect on each set of IO Registers.


Port-mapped I/OPort-mapping CPUs have IN and OUT instructions.For example:

LDA# 0x9A80 ;; shove hex 9A80 into ACOUT 0x007 ;; and send it to the PORT with address 0x07

567


24

012

34

3 3 3

USEmem/USEport

16

01

Main Memory IO RegistersAddress

Data

CS

Each IO register needs to be readable and writeable both by the cpuand by the external peripheral.

⇒ Use dual-ported registers.


Port-mapped I/OUsually a device will not use just one port address, but many —

— most for the transfer of “proper” data— others transfer status info on the device.

Status info used to implement hand shaking.

E.g.12 address lines (of our usual 24) are used to address 212 ≡4K I/Oregisters.

DeviceIORegisters

Main

Memory

DP

Decoder

Decoder

000000

FFFFFFAddressA0−A23

IORIOW

ControlUSEmem

AddressA0−A11

USEport

28F

000

FFF

Data


Memory-mapped I/ORecall that the memory address space may have gaps where there isno physical main memory.

We could do away with the need to select between USEmem orUSEport if we put the I/O Registers into available gaps in the memoryaddress space.

I/O registers

I/O registers

MemoryMain

spaceaddressMemory

R/W

by p

eriphera

ls

24 24 24

I/O registers I/O registersMemoryMain

peripheralsR/W by

(a) (b)


Memory-mapped I/O /ctd

As earlier, dual Ported registers are required

Now, writing and reading to a device can use the standard instructionfor loading from and storing into memory.

For example

LDA# 0x9A80 ;; get 9A80 hex into accumulatorSTA 0x00CC00 ;; and send to IO reg at address CC00 hex


The methods comparedBoth methods have a mix of memory and i/o registers on the samebus — and port-mapped requires that extra control wire.

24 3 3

24 24 24

Data

Address

USEmem/USEport

Data

Address



So why is port-mapping used?

1 In µcontrollers, main memory address space often full2 The hardware cost of decoding (here, 3bits vs 24bits)

Remember, each device requires its own decoder.


Polled versus Interrupt-driven I/O

Port−mapped

I/O

Memory−

Mapped I/O

Polled I/O

Interrupt−driven I/O

Direct MemoryAccess

ProgrammedI/O


Handshaking

When there is a mix of fast and slow devices on a bus one needs amethod of handshaking between the CPU and device.

Full handshaking involve conversations like ...CPU: “Are you ready?”IOdev: “I’m ready”CPU: “Have you got it?”IOdev: “I’ve got it”

The notes describe how handshaking is implemented at the lowestlevel on asynchronous buses.

But we don’t want to rely on nano-second timescale handshaking tocope with communication with devices which are orders of magnitudeslower.


Example: Buffered I/OOne approach to bridging the speed gap is to output data in bursts,buffering it in fast memory on the slow device.

The FIFO buffer must be biggerthan the volume of data that mightbe output in one burst

Emptiedslowly

quicklyFilled

FIFO buffer

. . .

Slowpart ofdevice

Peripheral

But the arrangement is not wholly robust ...

... at very least the IOdevice must have a bit in a device statusregister indicating READY or NOTREADY.

We consider two ways of handling handshaking at this higher level:Polling and Interrupts.


PollingThe CPU periodically checks the status of the device.

Code transfers 100 Bytes of data from an array at address 0x200 toan output register at Port 0x500. The status word is at Port 0x501.

LDA #200 ; Load base address into ACSTA 22 ; Loc22 hold address of array element

LOOP: IN 501 ; read device status word <<<<<<<<<AND #1 ; is the lowest bit equal to 1? <<<<<<<<<BZ LOOP ; if not, jump to LOOP <<<<<<<<<LDA (22) ; Load contents of array locationOUT 500 ; write them to deviceLDA 22 ; Load andADD #1 ; increment the locationSTA 22 ; and store it backSUB #300 ; Have we gone too far?BNZ LOOP ; If not, carry on looping

BIG SNAG: If the processor is fast and the device slow, the pollingloop will be executed many times before the status bit changes.


How wasteful could this be?Er, VERY!Suppose the IO device handles some 1000 Bytes per second.To handle one Byte takes 10−3s.A 2 GHz CPU taking 4 clock cycles per instruction will take only

(3instructions ∗ 4cycles)/(2× 109) ≈ 10−8s

to handle computation the polling loop.

⇒The polling loop executesapprox 105 times while wait-ing for the device to beready again!

Could try to be more ef-ficient by completing othertasks before re-polling ...

statusCheck device

Ready?

to deviceTransfer data

No

Yes

statusCheck device

Ready?

to deviceTransfer data

No

Yes

useful taskComplete n−thIncrement

n

(a) (b)


Interrupt-driven i/oFetch Decode Execute

Normal instruction cycle

Jump to IntService Rtne

IRQ=1?

No Yes

Much more efficient to allow the peripheral to signal to the CPU that itis ready to input or output– the peripheral interrupts the processor from its usual grind throughthe programmed instructions.

In program memory are a set of interrupt service subroutines— each contains the instructions to handle a particular deviceinterrupt.

When the interrupt occurs the processor jumps to the subroutine andthen returns to carry on with the programmed instructions.

Although it is a subroutine ... it could appear at any time!The machine must make sure the programmer’s data in the CPUregisters is saved before the interrupt and restore after the interrupt.


Interfacing for Real-time Control


Microcontroller architectureWe can now appreciate the architecture of a typical microcontrollerwhich integrates onto a single chip:

CPU and Memory (ROM, RAM and (E)EPROM)IO Ports (digital and A/D, pulse, serial/parallel comms, etc)IO control and status registersTimersInternal buses to connect the components

I/O PortsSerial

Comms

InterruptController

DataMemory(RAM)

Clock

(EPROM)MemoryProgram

CPU

HardwareTimers

External bus


Connecting the microcontroller to peripherals

Now we need to think about devices which might be connected to theI/O ports

not printers etc, (most texts will discuss in some detail devicessuch as keyboards, printers, disks, etc), but

devices used as part of a general engineering system for dataacquisition and control output.


Simple Digital I/O: Input

“Simple” means input from switches or similar that produce a few bitsto indicate their state.

♣ Eg: A safety management system may wish to monitor pairs ofswitches indicating that a seat is occupied and a a seat-belt buckled.

5 switches are connect to bits D0 ... D4 of the input register.The device clocks the input register, butthe CPU output-enables it for transfer to the AC

Decoder

Digital inputs

Select

Enable

CPU

Data

Control

Address

Plant

Sensors

Output

Input registerD0D4 13 2


Simple Digital I/O: Input

Decoder

Digital inputs

Select

Enable

CPU

Data

Control

Address

Plant

Sensors

Output

Input registerD0D4 13 2

Supposethe port has address 0xFAall D[4:0] are meant to be highalarm set off if any of the 5 inputs is low

again: IN 0xFA ;; read the register into the AC.;; If all well, the AC should contain 11111

SUB #0x1F ;; subtract 0x1F or 11111BNZ alarm ;; the answer should be 0, if it isn’t, panic!JMP again

alarm: ..


Simple Digital I/O: Output

Output Here a relay for switching a large current is controlled.

PLANT

Decoder

Select

CPU

Output register

Data

Address

Control

Digital outputs

WRITE

reset

Solidstaterelay

data8 +

Select

Write

registerOutput

Q7

Q0

−

D−type


Simple Digital I/O: Output

reset

Solidstaterelay

data8 +

Select

Write

registerOutput

Q7

Q0

−

D−type

Supposethe port is at OxFB,all output lines are used andthe current status is stored in memory location 0x0123.We want to send the entire current status to the register, exceptthat we must ensure that the MSB is 1 to turn on the relay.

The code is

LDA 0x0123 ;; get desired status from memoryOR #0x80 ;; OR with binary 1000 0000OUT 0xFB ;; out to portSTA 0x0123 ;; store status for future use


Analogue Input: From an A-to-D

Recall the role on the computer as part of a digital compensatorEngineered transfer function

Well behaved

Computer Controlled

Plant’sTransfer Function

Plant’sTransfer FunctionComputer

Compensator

DAC

then

ZOH

S&H+ADC

S&H+ADC

Sensing

Sensing


Analogue Input: From an A-to-D

IOInterface CPU Plant

Analogue

Sensor

SampleandHold

Multiplexer

Sample

AnalogueDemand Convert

ADC

EofC

Channel select

The I/O interface just contains an address decoder, data register, andsome timing circuitry.

The multiplexer allows the ADC to access several inputs — here theanalogue demand and the sensor feedback.


Analogue input: S&H and Flash Converter

Sample

Vin

Vsh

V

tHold

Track

Vin

Vsh

3−bit binaryoutput

8−3priority

encoder

1

3

2

4

5

6

7

gnd

0

VshVref


Analogue I/O: Output with a D-to-AProvides continuous voltage control ...

DAC

DAC

CPU IO Interface

Select

Plant

ZOH

Sample

Sample

Vin

Vsh

Vref

10V

R R R 2R

2R2R 2R 2R

1248

LSBMSB

R

DACVZOH


Digital Control System


Digital control

The continuous output y(t) is sampled and held, then digitized, givingdiscrete time samples of the input y(kT ) ...

Plant’sComputer G(s)

S&H+ADC

S&H+ADC

DAC

then

ZOH

Sensing

r(t)

y(t)

r(kT)

y(kT)

c(kT) c(t)

1

y(t)

But what computations are done in the computer box?


Controller implementation ... eg PID controlAn important quantity to derive is the error between the output(kT )and the demand r(kT ). Dropping the sampling interval T ...

e(k) = r(k)− y(k) .

A common method of control is to let the output of the compensatorbe the sum of three terms which are proportional (i) the error betweenthe output and the demand, (ii) to its integral and (iii) to its derivative

c(t) = K(

e(t) +1Ti

∫e(t)dt + Td e(t)

)⇒ c(t) = K

(e(t) +

1Ti

e(t) + Td e(t))

Now substitute backward differences for the derivatives ...

c(k) ≈ c(k)− c(k − 1)T

and e(k) ≈ e(k)− e(k − 1)T

and

e(k) ≈ e(k)− e(k − 1)T

≈ e(k)− 2e(k − 1) + e(k − 2)T 2


Controller implementation ... eg PID controlPlug these into

c(t) = K(

e(t) +1Ti

e(t) + Td e(t))

and rearrange to obtain

c(k) = c(k − 1) +

K[(

1 +TTi

+Td

T

)e(k)−(

1 + 2Td

T

)e(k − 1) +(

Td

T

)e(k − 2)

]

A few LDA’s and STA’s later ...


What have we learned in this course ...

Separation of data from control

The data section of the CPU containsnothing but a few registers and an ALU

Aim is to shovel Bytes around! Pathwaysset up by Levels, Registers clocked byPulses

CSLs and CSPs come from the controlunit. Their sequence determine by theinstruction

Memory — just a bunch of registers

I/O — just a bunch of registers

microcontroller systems engineering science 2nd year …dwm/courses/2co_2014/2co-l4.pdf ·...

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